# Generated by Yosys 0.8+615 (git sha1 6538671c, clang 7.0.1-8 -march=native -mtune=native -O2 -fpermissive -fPIC -Os)

.model top_module
.inputs CLK SPI_SS SPI_SCK SPI_IO0 SPI_IO1 SPI_IO2 SPI_IO3 USBP USBN PIN_1 PIN_2 PIN_3 PIN_4 PIN_5 PIN_6 PIN_7 PIN_8 PIN_9 PIN_11 PIN_12 PIN_13 PIN_14 PIN_21 PIN_22 PIN_23 PIN_24 PIN_25 PIN_26 PIN_27 PIN_28 PIN_29 PIN_30 PIN_31
.outputs USBPU LED PIN_10 PIN_15 PIN_16 PIN_17 PIN_18 PIN_19 PIN_20
.names $false
.names $true
1
.names $undef
.gate SB_LUT4 I0=$false I1=$false I2=$abc$44715$auto$dff2dffe.cc:158:make_patterns_logic$29217 I3=common.pb.timer_idle[1] O=$abc$44715$auto$ice40_ffinit.cc:140:execute$43998
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:46"
.param LUT_INIT 0000000011110000
.gate SB_LUT4 I0=$false I1=$false I2=common.pb.n_reset I3=common.pb.softreset O=$abc$44715$auto$dff2dffe.cc:158:make_patterns_logic$29217
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:46"
.param LUT_INIT 0000000011110000
.gate SB_LUT4 I0=$false I1=$false I2=pll.locked I3=PIN_1 O=common.pb.n_reset
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:46"
.param LUT_INIT 1111000000000000
.gate SB_LUT4 I0=$false I1=$false I2=$abc$44715$auto$dff2dffe.cc:158:make_patterns_logic$29217 I3=common.pb.timer_idle[2] O=$abc$44715$auto$ice40_ffinit.cc:140:execute$44002
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:46"
.param LUT_INIT 0000000011110000
.gate SB_LUT4 I0=$false I1=$false I2=$abc$44715$auto$dff2dffe.cc:158:make_patterns_logic$29217 I3=common.pb.timer_idle[3] O=$abc$44715$auto$ice40_ffinit.cc:140:execute$44006
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:46"
.param LUT_INIT 0000000011110000
.gate SB_LUT4 I0=$false I1=$false I2=$abc$44715$auto$dff2dffe.cc:158:make_patterns_logic$29217 I3=common.pb.timer_idle[4] O=$abc$44715$auto$ice40_ffinit.cc:140:execute$44010
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:46"
.param LUT_INIT 0000000011110000
.gate SB_LUT4 I0=$false I1=$false I2=$abc$44715$auto$dff2dffe.cc:158:make_patterns_logic$29217 I3=common.pb.timer_idle[5] O=$abc$44715$auto$ice40_ffinit.cc:140:execute$44014
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:46"
.param LUT_INIT 0000000011110000
.gate SB_LUT4 I0=$false I1=$false I2=$abc$44715$auto$dff2dffe.cc:158:make_patterns_logic$29217 I3=common.pb.timer_idle[6] O=$abc$44715$auto$ice40_ffinit.cc:140:execute$44018
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:46"
.param LUT_INIT 0000000011110000
.gate SB_LUT4 I0=$false I1=$false I2=$abc$44715$auto$dff2dffe.cc:158:make_patterns_logic$29217 I3=common.pb.timer_idle[7] O=$abc$44715$auto$ice40_ffinit.cc:140:execute$44022
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:46"
.param LUT_INIT 0000000011110000
.gate SB_LUT4 I0=$false I1=$false I2=$abc$44715$auto$dff2dffe.cc:158:make_patterns_logic$29217 I3=common.pb.timer_idle[8] O=$abc$44715$auto$ice40_ffinit.cc:140:execute$44026
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:46"
.param LUT_INIT 0000000011110000
.gate SB_LUT4 I0=$false I1=$false I2=$abc$44715$auto$dff2dffe.cc:158:make_patterns_logic$29217 I3=common.pb.timer_idle[9] O=$abc$44715$auto$ice40_ffinit.cc:140:execute$44030
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:46"
.param LUT_INIT 0000000011110000
.gate SB_LUT4 I0=$false I1=$false I2=$abc$44715$auto$dff2dffe.cc:158:make_patterns_logic$29217 I3=common.pb.timer_idle[10] O=$abc$44715$auto$ice40_ffinit.cc:140:execute$44034
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:46"
.param LUT_INIT 0000000011110000
.gate SB_LUT4 I0=$false I1=$false I2=$abc$44715$auto$dff2dffe.cc:158:make_patterns_logic$29217 I3=common.pb.timer_idle[11] O=$abc$44715$auto$ice40_ffinit.cc:140:execute$44038
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:46"
.param LUT_INIT 0000000011110000
.gate SB_LUT4 I0=$false I1=$false I2=$abc$44715$auto$dff2dffe.cc:158:make_patterns_logic$29217 I3=common.pb.timer_idle[12] O=$abc$44715$auto$ice40_ffinit.cc:140:execute$44042
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:46"
.param LUT_INIT 0000000011110000
.gate SB_LUT4 I0=$false I1=$false I2=$abc$44715$auto$dff2dffe.cc:158:make_patterns_logic$29217 I3=common.pb.timer_idle[13] O=$abc$44715$auto$ice40_ffinit.cc:140:execute$44046
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:46"
.param LUT_INIT 0000000011110000
.gate SB_LUT4 I0=$false I1=$false I2=$abc$44715$auto$dff2dffe.cc:158:make_patterns_logic$29217 I3=common.pb.timer_idle[14] O=$abc$44715$auto$ice40_ffinit.cc:140:execute$44050
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:46"
.param LUT_INIT 0000000011110000
.gate SB_LUT4 I0=$false I1=$false I2=$abc$44715$auto$dff2dffe.cc:158:make_patterns_logic$29217 I3=common.pb.timer_idle[15] O=$abc$44715$auto$ice40_ffinit.cc:140:execute$44054
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:46"
.param LUT_INIT 0000000011110000
.gate SB_LUT4 I0=$false I1=$false I2=$abc$44715$auto$dff2dffe.cc:158:make_patterns_logic$29217 I3=common.pb.timer_idle[16] O=$abc$44715$auto$ice40_ffinit.cc:140:execute$44058
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:46"
.param LUT_INIT 0000000011110000
.gate SB_LUT4 I0=$false I1=$false I2=$abc$44715$auto$dff2dffe.cc:158:make_patterns_logic$29217 I3=common.pb.timer_idle[17] O=$abc$44715$auto$ice40_ffinit.cc:140:execute$44062
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:46"
.param LUT_INIT 0000000011110000
.gate SB_LUT4 I0=$false I1=$false I2=$abc$44715$auto$dff2dffe.cc:158:make_patterns_logic$29217 I3=common.pb.timer_idle[18] O=$abc$44715$auto$ice40_ffinit.cc:140:execute$44066
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:46"
.param LUT_INIT 0000000011110000
.gate SB_LUT4 I0=$false I1=$false I2=$abc$44715$auto$dff2dffe.cc:158:make_patterns_logic$29217 I3=common.pb.timer_idle[19] O=$abc$44715$auto$ice40_ffinit.cc:140:execute$44070
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:46"
.param LUT_INIT 0000000011110000
.gate SB_LUT4 I0=$false I1=$false I2=$abc$44715$auto$dff2dffe.cc:158:make_patterns_logic$29217 I3=common.pb.timer_idle[20] O=$abc$44715$auto$ice40_ffinit.cc:140:execute$44074
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:46"
.param LUT_INIT 0000000011110000
.gate SB_LUT4 I0=$false I1=$false I2=$abc$44715$auto$dff2dffe.cc:158:make_patterns_logic$29217 I3=common.pb.timer_idle[21] O=$abc$44715$auto$ice40_ffinit.cc:140:execute$44078
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:46"
.param LUT_INIT 0000000011110000
.gate SB_LUT4 I0=$false I1=$false I2=$abc$44715$auto$dff2dffe.cc:158:make_patterns_logic$29217 I3=common.pb.timer_idle[22] O=$abc$44715$auto$ice40_ffinit.cc:140:execute$44082
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:46"
.param LUT_INIT 0000000011110000
.gate SB_LUT4 I0=$false I1=$false I2=$abc$44715$auto$dff2dffe.cc:158:make_patterns_logic$29217 I3=common.pb.timer_idle[23] O=$abc$44715$auto$ice40_ffinit.cc:140:execute$44086
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:46"
.param LUT_INIT 0000000011110000
.gate SB_LUT4 I0=$false I1=$false I2=$abc$44715$auto$dff2dffe.cc:158:make_patterns_logic$29217 I3=common.pb.timer_idle[0] O=$abc$44715$auto$ice40_ffinit.cc:140:execute$44090
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:46"
.param LUT_INIT 0000000011110000
.gate SB_LUT4 I0=$false I1=common.pb.uart.tx_mod.sym_count[3] I2=common.pb.uart.tx_mod.sym_count[2] I3=common.pb.uart.tx_mod.sym_count[1] O=$abc$44715$techmap\common.pb.uart.tx_mod.$logic_or$uart_mod.v:353$9121_Y_new_
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:51"
.param LUT_INIT 0011001100111100
.gate SB_LUT4 I0=common.pb.n_reset I1=common.pb.uart.tx_mod.tx_active I2=common.pb.uart.arb_mod.rx I3=common.pb.uart.rx_mod.rx_active O=$abc$44715$auto$rtlil.cc:1969:NotGate$44285
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:56"
.param LUT_INIT 0111011101010111
.gate SB_LUT4 I0=common.pb.uart.tx_mod.tx_buf[5] I1=common.pb.uart.tx_mod.tx_buf[0] I2=$abc$44715$new_n1429_ I3=$abc$44715$new_n1428_ O=$abc$44715$common.pb.uart.tx_mod.calc_tx_parity_new_inv_
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:56"
.param LUT_INIT 0110100110010110
.gate SB_LUT4 I0=$false I1=common.pb.uart.tx_mod.tx_buf[3] I2=common.pb.uart.tx_mod.tx_buf[2] I3=common.pb.uart.tx_mod.tx_buf[4] O=$abc$44715$new_n1428_
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:51"
.param LUT_INIT 1100001100111100
.gate SB_LUT4 I0=$false I1=common.pb.uart.tx_mod.tx_buf[7] I2=common.pb.uart.tx_mod.tx_buf[6] I3=common.pb.uart.tx_mod.tx_buf[1] O=$abc$44715$new_n1429_
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:51"
.param LUT_INIT 0011110011000011
.gate SB_LUT4 I0=$false I1=$false I2=$abc$44715$auto$simplemap.cc:309:simplemap_lut$17004[0]_new_ I3=$abc$44715$techmap\common.pb.uart.tx_mod.$logic_or$uart_mod.v:353$9121_Y_new_ O=$abc$44715$new_n1430_
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:46"
.param LUT_INIT 0000000000001111
.gate SB_LUT4 I0=$false I1=common.pb.uart.tx_mod.sym_count[1] I2=common.pb.uart.tx_mod.sym_count[2] I3=common.pb.uart.tx_mod.sym_count[0] O=$abc$44715$auto$simplemap.cc:309:simplemap_lut$17004[0]_new_
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:51"
.param LUT_INIT 0000000000001100
.gate SB_LUT4 I0=$false I1=$false I2=common.pb.uart.tx_mod.sym_count[0] I3=$abc$44715$auto$simplemap.cc:127:simplemap_reduce$40245[0]_new_ O=$abc$44715$auto$simplemap.cc:250:simplemap_eqne$40309[1]_new_inv_
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:46"
.param LUT_INIT 1111000000000000
.gate SB_LUT4 I0=$false I1=common.pb.uart.tx_mod.sym_count[3] I2=common.pb.uart.tx_mod.sym_count[2] I3=common.pb.uart.tx_mod.sym_count[1] O=$abc$44715$auto$simplemap.cc:127:simplemap_reduce$40245[0]_new_
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:51"
.param LUT_INIT 0000000000000011
.gate SB_LUT4 I0=$false I1=$false I2=common.pb.spirx_lencalc_n_reset I3=$abc$44715$auto$dff2dffe.cc:158:make_patterns_logic$29217 O=$abc$44715$auto$rtlil.cc:1969:NotGate$44229
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:46"
.param LUT_INIT 0000111111111111
.gate SB_LUT4 I0=$false I1=$false I2=$abc$44715$auto$simplemap.cc:127:simplemap_reduce$41156[0]_new_ I3=common.pb.uart.rx_mod.sym_count[0] O=$abc$44715$auto$rtlil.cc:1969:NotGate$44581
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:46"
.param LUT_INIT 0000000011110000
.gate SB_LUT4 I0=$false I1=$false I2=$abc$44715$new_n1437_ I3=common.pb.uart.rx_mod.sym_count[3] O=$abc$44715$auto$simplemap.cc:127:simplemap_reduce$41156[0]_new_
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:46"
.param LUT_INIT 0000000011110000
.gate SB_LUT4 I0=$false I1=$false I2=common.pb.uart.rx_mod.sym_count[2] I3=common.pb.uart.rx_mod.sym_count[1] O=$abc$44715$new_n1437_
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:46"
.param LUT_INIT 0000000000001111
.gate SB_LUT4 I0=$false I1=$false I2=common.pb.n_reset I3=common.pb.uart.tx_mod.tx_active O=$abc$44715$auto$rtlil.cc:1969:NotGate$44281
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:46"
.param LUT_INIT 1111111100001111
.gate SB_LUT4 I0=$false I1=$abc$44715$auto$alumacc.cc:491:replace_alu$16036[5] I2=$abc$44715$new_n1440_ I3=common.pb.spi.bit_count[3] O=$abc$44715$auto$rtlil.cc:1836:ReduceOr$16042
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:51"
.param LUT_INIT 1111001100110011
.gate SB_LUT4 I0=$false I1=$abc$44715$new_n1441_ I2=common.pb.spi.bit_count[1] I3=common.pb.spi.bit_count[0] O=$abc$44715$new_n1440_
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:51"
.param LUT_INIT 0000000000001100
.gate SB_LUT4 I0=$false I1=common.pb.spi.bit_count[5] I2=common.pb.spi.bit_count[4] I3=common.pb.spi.bit_count[2] O=$abc$44715$new_n1441_
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:51"
.param LUT_INIT 0000000000000011
.gate SB_LUT4 I0=$abc$44715$new_n1455_ I1=$abc$44715$new_n1454_ I2=$abc$44715$new_n1451_ I3=$abc$44715$new_n2662_ O=$abc$44715$new_n1443_
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:56"
.param LUT_INIT 1000000000000000
.gate SB_LUT4 I0=common.pb.tsyn_clks[4] I1=common.pb.tsyn_clks[12] I2=$abc$44715$auto$ice40_ffinit.cc:141:execute$44043 I3=$abc$44715$auto$ice40_ffinit.cc:141:execute$44011 O=$abc$44715$new_n1449_
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:56"
.param LUT_INIT 0001010000101000
.gate SB_LUT4 I0=common.pb.tsyn_clks[16] I1=common.pb.tsyn_clks[21] I2=$abc$44715$auto$ice40_ffinit.cc:141:execute$44079 I3=$abc$44715$auto$ice40_ffinit.cc:141:execute$44059 O=$abc$44715$new_n1450_
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:56"
.param LUT_INIT 0001010000101000
.gate SB_LUT4 I0=$abc$44715$new_n1453_ I1=$abc$44715$new_n1452_ I2=common.pb.tsyn_clks[10] I3=$abc$44715$auto$ice40_ffinit.cc:141:execute$44035 O=$abc$44715$new_n1451_
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:56"
.param LUT_INIT 0000100010000000
.gate SB_LUT4 I0=common.pb.tsyn_clks[5] I1=$abc$44715$auto$ice40_ffinit.cc:141:execute$44015 I2=common.pb.tsyn_clks[11] I3=$abc$44715$auto$ice40_ffinit.cc:141:execute$44039 O=$abc$44715$new_n1452_
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:56"
.param LUT_INIT 0000011101110111
.gate SB_LUT4 I0=common.pb.tsyn_clks[13] I1=common.pb.tsyn_clks[22] I2=$abc$44715$auto$ice40_ffinit.cc:141:execute$44083 I3=$abc$44715$auto$ice40_ffinit.cc:141:execute$44047 O=$abc$44715$new_n1453_
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:56"
.param LUT_INIT 0001010000101000
.gate SB_LUT4 I0=common.pb.tsyn_clks[3] I1=common.pb.tsyn_clks[23] I2=$abc$44715$auto$ice40_ffinit.cc:141:execute$44087 I3=$abc$44715$auto$ice40_ffinit.cc:141:execute$44007 O=$abc$44715$new_n1454_
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:56"
.param LUT_INIT 0001010000101000
.gate SB_LUT4 I0=common.pb.tsyn_clks[8] I1=common.pb.tsyn_clks[15] I2=$abc$44715$auto$ice40_ffinit.cc:141:execute$44055 I3=$abc$44715$auto$ice40_ffinit.cc:141:execute$44027 O=$abc$44715$new_n1455_
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:56"
.param LUT_INIT 0001010000101000
.gate SB_LUT4 I0=$abc$44715$new_n1462_ I1=$abc$44715$new_n1461_ I2=common.pb.tsyn_clks[18] I3=$abc$44715$auto$ice40_ffinit.cc:141:execute$44067 O=$abc$44715$new_n1460_
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:56"
.param LUT_INIT 0000100010000000
.gate SB_LUT4 I0=common.pb.tsyn_clks[9] I1=common.pb.tsyn_clks[14] I2=$abc$44715$auto$ice40_ffinit.cc:141:execute$44051 I3=$abc$44715$auto$ice40_ffinit.cc:141:execute$44031 O=$abc$44715$new_n1461_
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:56"
.param LUT_INIT 0001010000101000
.gate SB_LUT4 I0=common.pb.tsyn_clks[11] I1=$abc$44715$auto$ice40_ffinit.cc:141:execute$44039 I2=common.pb.tsyn_clks[19] I3=$abc$44715$auto$ice40_ffinit.cc:141:execute$44071 O=$abc$44715$new_n1462_
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:56"
.param LUT_INIT 0000111011101110
.gate SB_LUT4 I0=$false I1=$abc$44715$new_n1464_ I2=$abc$44715$new_n1478_ I3=$abc$44715$new_n1489_ O=$abc$44715$techmap$techmap\common.pb.$procmux$12803.$reduce_or$/home/mb/fpga-toolchain/yosys/bin/../share/yosys/techmap.v:441$19144_Y
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:51"
.param LUT_INIT 1111111100111111
.gate SB_LUT4 I0=$abc$44715$new_n1465_ I1=$abc$44715$new_n1477_ I2=$abc$44715$techmap\common.pb.$xor$crc8_func.v:32$6095_Y_new_inv_ I3=$abc$44715$new_n1474_ O=$abc$44715$new_n1464_
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:56"
.param LUT_INIT 0010100010101010
.gate SB_LUT4 I0=$abc$44715$new_n1466_ I1=$abc$44715$techmap\common.pb.$xor$crc8_func.v:25$5966_Y_new_inv_ I2=$abc$44715$techmap\common.pb.$xor$crc8_func.v:32$6007_Y_new_inv_ I3=$abc$44715$auto$rtlil.cc:1835:ReduceAnd$16071_new_ O=$abc$44715$new_n1465_
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:56"
.param LUT_INIT 0100000101010101
.gate SB_LUT4 I0=$false I1=$false I2=common.pb.spitx_bytecount[0] I3=$abc$44715$auto$simplemap.cc:127:simplemap_reduce$35840[0]_new_ O=$abc$44715$new_n1466_
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:46"
.param LUT_INIT 1111000000000000
.gate SB_LUT4 I0=$abc$44715$auto$simplemap.cc:127:simplemap_reduce$19217[1]_new_inv_ I1=common.pb.spitx_bytecount[2] I2=common.pb.spitx_bytecount[1] I3=common.pb.spitx_bytecount[3] O=$abc$44715$auto$simplemap.cc:127:simplemap_reduce$35840[0]_new_
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:56"
.param LUT_INIT 0000000000000010
.gate SB_LUT4 I0=common.pb.spitx_bytecount[7] I1=common.pb.spitx_bytecount[6] I2=common.pb.spitx_bytecount[5] I3=common.pb.spitx_bytecount[4] O=$abc$44715$auto$simplemap.cc:127:simplemap_reduce$19217[1]_new_inv_
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:56"
.param LUT_INIT 0000000000000001
.gate SB_LUT4 I0=$false I1=common.pb.spitx_ctrl_reply_data[31] I2=common.pb.spitx_crc[7] I3=$abc$44715$techmap\common.pb.$xor$crc8_func.v:31$6000_Y_new_inv_ O=$abc$44715$techmap\common.pb.$xor$crc8_func.v:32$6007_Y_new_inv_
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:51"
.param LUT_INIT 1100001100111100
.gate SB_LUT4 I0=$false I1=$false I2=common.pb.spitx_ctrl_reply_data[30] I3=common.pb.spitx_crc[6] O=$abc$44715$techmap\common.pb.$xor$crc8_func.v:31$6000_Y_new_inv_
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:46"
.param LUT_INIT 1111000000001111
.gate SB_LUT4 I0=$abc$44715$auto$simplemap.cc:127:simplemap_reduce$19284[0]_new_inv_ I1=$abc$44715$auto$simplemap.cc:127:simplemap_reduce$19217[1]_new_inv_ I2=common.pb.spitx_bytecount[2] I3=common.pb.spitx_bytecount[3] O=$abc$44715$auto$rtlil.cc:1835:ReduceAnd$16071_new_
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:56"
.param LUT_INIT 0000000000001000
.gate SB_LUT4 I0=$false I1=$false I2=common.pb.spitx_bytecount[1] I3=common.pb.spitx_bytecount[0] O=$abc$44715$auto$simplemap.cc:127:simplemap_reduce$19284[0]_new_inv_
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:46"
.param LUT_INIT 1111000000000000
.gate SB_LUT4 I0=$false I1=$false I2=common.pb.spitx_ctrl_reply_data[24] I3=common.pb.spitx_crc[0] O=$abc$44715$techmap\common.pb.$xor$crc8_func.v:25$5966_Y_new_inv_
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:46"
.param LUT_INIT 1111000000001111
.gate SB_LUT4 I0=common.pb.spitx_bytecount[2] I1=$abc$44715$auto$simplemap.cc:127:simplemap_reduce$19217[1]_new_inv_ I2=$abc$44715$auto$simplemap.cc:127:simplemap_reduce$19236[0]_new_inv_ I3=common.pb.spitx_bytecount[3] O=$abc$44715$new_n1474_
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:56"
.param LUT_INIT 0000000010000000
.gate SB_LUT4 I0=$false I1=$false I2=common.pb.spitx_bytecount[0] I3=common.pb.spitx_bytecount[1] O=$abc$44715$auto$simplemap.cc:127:simplemap_reduce$19236[0]_new_inv_
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:46"
.param LUT_INIT 0000000011110000
.gate SB_LUT4 I0=$false I1=$false I2=common.pb.spitx_crc[7] I3=common.pb.spitx_ctrl_reply_data[15] O=$abc$44715$techmap\common.pb.$xor$crc8_func.v:32$6095_Y_new_inv_
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:46"
.param LUT_INIT 1111000000001111
.gate SB_LUT4 I0=common.pb.spitx_crc[0] I1=common.pb.spitx_crc[6] I2=common.pb.spitx_ctrl_reply_data[14] I3=common.pb.spitx_ctrl_reply_data[8] O=$abc$44715$new_n1477_
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:56"
.param LUT_INIT 0110100110010110
.gate SB_LUT4 I0=$abc$44715$new_n1479_ I1=$abc$44715$new_n1488_ I2=$abc$44715$techmap\common.pb.$xor$crc8_func.v:32$6050_Y_new_inv_ I3=$abc$44715$techmap\common.pb.$procmux$10686_CMP_new_ O=$abc$44715$new_n1478_
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:56"
.param LUT_INIT 0001010001010101
.gate SB_LUT4 I0=$false I1=$abc$44715$techmap\common.pb.$procmux$10684_CMP_new_ I2=$abc$44715$techmap\common.pb.$xor$crc8_func.v:25$6101_Y_new_inv_ I3=$abc$44715$techmap\common.pb.$xor$crc8_func.v:32$6142_Y_new_inv_ O=$abc$44715$new_n1479_
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:51"
.param LUT_INIT 0000110011000000
.gate SB_LUT4 I0=$false I1=common.pb.spitx_crc[7] I2=common.pb.spitx_ctrl_reply_data[7] I3=$abc$44715$techmap\common.pb.$xor$crc8_func.v:31$6135_Y_new_inv_ O=$abc$44715$techmap\common.pb.$xor$crc8_func.v:32$6142_Y_new_inv_
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:51"
.param LUT_INIT 1100001100111100
.gate SB_LUT4 I0=$false I1=$false I2=common.pb.spitx_crc[6] I3=common.pb.spitx_ctrl_reply_data[6] O=$abc$44715$techmap\common.pb.$xor$crc8_func.v:31$6135_Y_new_inv_
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:46"
.param LUT_INIT 1111000000001111
.gate SB_LUT4 I0=common.pb.spitx_bytecount[2] I1=$abc$44715$auto$simplemap.cc:127:simplemap_reduce$19217[1]_new_inv_ I2=$abc$44715$auto$simplemap.cc:127:simplemap_reduce$19260[0]_new_inv_ I3=common.pb.spitx_bytecount[3] O=$abc$44715$techmap\common.pb.$procmux$10684_CMP_new_
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:56"
.param LUT_INIT 0000000010000000
.gate SB_LUT4 I0=$false I1=$false I2=common.pb.spitx_bytecount[1] I3=common.pb.spitx_bytecount[0] O=$abc$44715$auto$simplemap.cc:127:simplemap_reduce$19260[0]_new_inv_
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:46"
.param LUT_INIT 0000000011110000
.gate SB_LUT4 I0=$false I1=$false I2=common.pb.spitx_crc[0] I3=common.pb.spitx_ctrl_reply_data[0] O=$abc$44715$techmap\common.pb.$xor$crc8_func.v:25$6101_Y_new_inv_
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:46"
.param LUT_INIT 1111000000001111
.gate SB_LUT4 I0=common.pb.spitx_bytecount[2] I1=$abc$44715$auto$simplemap.cc:127:simplemap_reduce$19217[1]_new_inv_ I2=$abc$44715$auto$simplemap.cc:127:simplemap_reduce$19212[0]_new_inv_ I3=common.pb.spitx_bytecount[3] O=$abc$44715$techmap\common.pb.$procmux$10686_CMP_new_
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:56"
.param LUT_INIT 0000000010000000
.gate SB_LUT4 I0=$false I1=$false I2=common.pb.spitx_bytecount[1] I3=common.pb.spitx_bytecount[0] O=$abc$44715$auto$simplemap.cc:127:simplemap_reduce$19212[0]_new_inv_
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:46"
.param LUT_INIT 0000000000001111
.gate SB_LUT4 I0=$false I1=$false I2=common.pb.spitx_crc[7] I3=common.pb.spitx_ctrl_reply_data[23] O=$abc$44715$techmap\common.pb.$xor$crc8_func.v:32$6050_Y_new_inv_
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:46"
.param LUT_INIT 1111000000001111
.gate SB_LUT4 I0=common.pb.spitx_crc[0] I1=common.pb.spitx_crc[6] I2=common.pb.spitx_ctrl_reply_data[22] I3=common.pb.spitx_ctrl_reply_data[16] O=$abc$44715$new_n1488_
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:56"
.param LUT_INIT 0110100110010110
.gate SB_LUT4 I0=$abc$44715$new_n1490_ I1=common.pb.spitx_crc[0] I2=common.pb.spitx_ctrl_reply[0] I3=$abc$44715$techmap\common.pb.$xor$crc8_func.v:32$5962_Y_new_ O=$abc$44715$new_n1489_
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:56"
.param LUT_INIT 1000001000101000
.gate SB_LUT4 I0=$abc$44715$auto$simplemap.cc:127:simplemap_reduce$19260[0]_new_inv_ I1=$abc$44715$auto$simplemap.cc:127:simplemap_reduce$19217[1]_new_inv_ I2=common.pb.spitx_bytecount[2] I3=common.pb.spitx_bytecount[3] O=$abc$44715$new_n1490_
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:56"
.param LUT_INIT 0000000000001000
.gate SB_LUT4 I0=common.pb.spitx_crc[7] I1=common.pb.spitx_crc[6] I2=common.pb.spitx_ctrl_reply[7] I3=common.pb.spitx_ctrl_reply[6] O=$abc$44715$techmap\common.pb.$xor$crc8_func.v:32$5962_Y_new_
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:56"
.param LUT_INIT 0110100110010110
.gate SB_LUT4 I0=$abc$44715$new_n1498_ I1=$abc$44715$new_n1493_ I2=$abc$44715$techmap\common.pb.$procmux$10686_CMP_new_ I3=$abc$44715$techmap\common.pb.$xor$crc8_func.v:26$6020_Y_new_ O=$abc$44715$techmap$techmap\common.pb.$procmux$12803.$reduce_or$/home/mb/fpga-toolchain/yosys/bin/../share/yosys/techmap.v:441$19145_Y
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:56"
.param LUT_INIT 1111011101110111
.gate SB_LUT4 I0=$abc$44715$new_n1494_ I1=$abc$44715$new_n1466_ I2=$abc$44715$auto$rtlil.cc:1835:ReduceAnd$16071_new_ I3=$abc$44715$techmap\common.pb.$xor$crc8_func.v:26$5975_Y_new_inv_ O=$abc$44715$new_n1493_
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:56"
.param LUT_INIT 0001000100000001
.gate SB_LUT4 I0=$false I1=$false I2=$abc$44715$techmap\common.pb.$procmux$10684_CMP_new_ I3=$abc$44715$techmap\common.pb.$xor$crc8_func.v:26$6110_Y_new_inv_ O=$abc$44715$new_n1494_
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:46"
.param LUT_INIT 0000000011110000
.gate SB_LUT4 I0=$false I1=$abc$44715$techmap\common.pb.$xor$crc8_func.v:26$6106_Y_new_inv_ I2=$abc$44715$techmap\common.pb.$xor$crc8_func.v:31$6135_Y_new_inv_ I3=$abc$44715$techmap\common.pb.$xor$crc8_func.v:25$6101_Y_new_inv_ O=$abc$44715$techmap\common.pb.$xor$crc8_func.v:26$6110_Y_new_inv_
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:51"
.param LUT_INIT 1100001100111100
.gate SB_LUT4 I0=$false I1=$false I2=common.pb.spitx_crc[1] I3=common.pb.spitx_ctrl_reply_data[1] O=$abc$44715$techmap\common.pb.$xor$crc8_func.v:26$6106_Y_new_inv_
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:46"
.param LUT_INIT 1111000000001111
.gate SB_LUT4 I0=common.pb.spitx_ctrl_reply_data[25] I1=common.pb.spitx_crc[1] I2=$abc$44715$techmap\common.pb.$xor$crc8_func.v:31$6000_Y_new_inv_ I3=$abc$44715$techmap\common.pb.$xor$crc8_func.v:25$5966_Y_new_inv_ O=$abc$44715$techmap\common.pb.$xor$crc8_func.v:26$5975_Y_new_inv_
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:56"
.param LUT_INIT 1001011001101001
.gate SB_LUT4 I0=$abc$44715$techmap\common.pb.$xor$crc8_func.v:26$6065_Y_new_ I1=$abc$44715$new_n1474_ I2=$abc$44715$techmap\common.pb.$xor$crc8_func.v:26$5930_Y_new_ I3=$abc$44715$new_n1490_ O=$abc$44715$new_n1498_
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:56"
.param LUT_INIT 0000011101110111
.gate SB_LUT4 I0=$false I1=$false I2=$abc$44715$techmap\common.pb.$xor$crc8_func.v:26$6061_Y_new_inv_ I3=$abc$44715$new_n1477_ O=$abc$44715$techmap\common.pb.$xor$crc8_func.v:26$6065_Y_new_
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:46"
.param LUT_INIT 1111000000001111
.gate SB_LUT4 I0=$false I1=$false I2=common.pb.spitx_crc[1] I3=common.pb.spitx_ctrl_reply_data[9] O=$abc$44715$techmap\common.pb.$xor$crc8_func.v:26$6061_Y_new_inv_
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:46"
.param LUT_INIT 1111000000001111
.gate SB_LUT4 I0=$false I1=common.pb.spitx_crc[1] I2=common.pb.spitx_ctrl_reply[1] I3=$abc$44715$new_n1502_ O=$abc$44715$techmap\common.pb.$xor$crc8_func.v:26$5930_Y_new_
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:51"
.param LUT_INIT 1100001100111100
.gate SB_LUT4 I0=common.pb.spitx_crc[0] I1=common.pb.spitx_crc[6] I2=common.pb.spitx_ctrl_reply[6] I3=common.pb.spitx_ctrl_reply[0] O=$abc$44715$new_n1502_
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:56"
.param LUT_INIT 0110100110010110
.gate SB_LUT4 I0=$false I1=common.pb.spitx_crc[1] I2=common.pb.spitx_ctrl_reply_data[17] I3=$abc$44715$new_n1488_ O=$abc$44715$techmap\common.pb.$xor$crc8_func.v:26$6020_Y_new_
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:51"
.param LUT_INIT 1100001100111100
.gate SB_LUT4 I0=$false I1=$abc$44715$new_n1505_ I2=$abc$44715$new_n1510_ I3=$abc$44715$techmap$techmap\common.pb.$procmux$12803.$and$/home/mb/fpga-toolchain/yosys/bin/../share/yosys/techmap.v:434$19140_Y[2]_new_ O=$abc$44715$techmap$techmap\common.pb.$procmux$12803.$reduce_or$/home/mb/fpga-toolchain/yosys/bin/../share/yosys/techmap.v:441$19146_Y
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:51"
.param LUT_INIT 1111111111110011
.gate SB_LUT4 I0=$abc$44715$techmap$techmap\common.pb.$procmux$12803.$and$/home/mb/fpga-toolchain/yosys/bin/../share/yosys/techmap.v:434$19138_Y[2]_new_ I1=$abc$44715$techmap$techmap\common.pb.$procmux$12803.$and$/home/mb/fpga-toolchain/yosys/bin/../share/yosys/techmap.v:434$19141_Y[2]_new_ I2=$abc$44715$new_n1506_ I3=$abc$44715$new_n1466_ O=$abc$44715$new_n1505_
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:56"
.param LUT_INIT 0000000000000001
.gate SB_LUT4 I0=$abc$44715$new_n1474_ I1=common.pb.spitx_crc[2] I2=common.pb.spitx_ctrl_reply_data[10] I3=$abc$44715$techmap\common.pb.$xor$crc8_func.v:26$6065_Y_new_ O=$abc$44715$new_n1506_
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:56"
.param LUT_INIT 1000001000101000
.gate SB_LUT4 I0=$abc$44715$auto$rtlil.cc:1835:ReduceAnd$16071_new_ I1=common.pb.spitx_ctrl_reply_data[26] I2=common.pb.spitx_crc[2] I3=$abc$44715$techmap\common.pb.$xor$crc8_func.v:26$5975_Y_new_inv_ O=$abc$44715$techmap$techmap\common.pb.$procmux$12803.$and$/home/mb/fpga-toolchain/yosys/bin/../share/yosys/techmap.v:434$19141_Y[2]_new_
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:56"
.param LUT_INIT 0010100010000010
.gate SB_LUT4 I0=$abc$44715$techmap\common.pb.$procmux$10684_CMP_new_ I1=common.pb.spitx_crc[2] I2=common.pb.spitx_ctrl_reply_data[2] I3=$abc$44715$techmap\common.pb.$xor$crc8_func.v:26$6110_Y_new_inv_ O=$abc$44715$techmap$techmap\common.pb.$procmux$12803.$and$/home/mb/fpga-toolchain/yosys/bin/../share/yosys/techmap.v:434$19138_Y[2]_new_
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:56"
.param LUT_INIT 0010100010000010
.gate SB_LUT4 I0=$abc$44715$techmap\common.pb.$procmux$10686_CMP_new_ I1=common.pb.spitx_crc[2] I2=common.pb.spitx_ctrl_reply_data[18] I3=$abc$44715$techmap\common.pb.$xor$crc8_func.v:26$6020_Y_new_ O=$abc$44715$techmap$techmap\common.pb.$procmux$12803.$and$/home/mb/fpga-toolchain/yosys/bin/../share/yosys/techmap.v:434$19140_Y[2]_new_
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:56"
.param LUT_INIT 1000001000101000
.gate SB_LUT4 I0=$abc$44715$new_n1490_ I1=common.pb.spitx_crc[2] I2=common.pb.spitx_ctrl_reply[2] I3=$abc$44715$techmap\common.pb.$xor$crc8_func.v:26$5930_Y_new_ O=$abc$44715$new_n1510_
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:56"
.param LUT_INIT 1000001000101000
.gate SB_LUT4 I0=$abc$44715$new_n1515_ I1=$abc$44715$new_n1512_ I2=$abc$44715$techmap$techmap\common.pb.$procmux$12803.$and$/home/mb/fpga-toolchain/yosys/bin/../share/yosys/techmap.v:434$19138_Y[3]_new_ I3=$abc$44715$new_n1521_ O=$abc$44715$techmap$techmap\common.pb.$procmux$12803.$reduce_or$/home/mb/fpga-toolchain/yosys/bin/../share/yosys/techmap.v:441$19147_Y
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:56"
.param LUT_INIT 1111111111110111
.gate SB_LUT4 I0=$abc$44715$new_n1466_ I1=$abc$44715$new_n1514_ I2=$abc$44715$techmap\common.pb.$xor$crc8_func.v:28$5940_Y_new_inv_ I3=$abc$44715$new_n1490_ O=$abc$44715$new_n1512_
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:56"
.param LUT_INIT 0100000101010101
.gate SB_LUT4 I0=common.pb.spitx_crc[2] I1=common.pb.spitx_crc[3] I2=common.pb.spitx_ctrl_reply[3] I3=common.pb.spitx_ctrl_reply[2] O=$abc$44715$techmap\common.pb.$xor$crc8_func.v:28$5940_Y_new_inv_
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:56"
.param LUT_INIT 1001011001101001
.gate SB_LUT4 I0=common.pb.spitx_crc[1] I1=common.pb.spitx_crc[7] I2=common.pb.spitx_ctrl_reply[7] I3=common.pb.spitx_ctrl_reply[1] O=$abc$44715$new_n1514_
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:56"
.param LUT_INIT 1001011001101001
.gate SB_LUT4 I0=$abc$44715$new_n1516_ I1=$abc$44715$new_n1520_ I2=$abc$44715$techmap\common.pb.$xor$crc8_func.v:28$5985_Y_new_inv_ I3=$abc$44715$auto$rtlil.cc:1835:ReduceAnd$16071_new_ O=$abc$44715$new_n1515_
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:56"
.param LUT_INIT 0100000101010101
.gate SB_LUT4 I0=$false I1=$abc$44715$techmap\common.pb.$procmux$10686_CMP_new_ I2=$abc$44715$techmap\common.pb.$xor$crc8_func.v:28$6030_Y_new_inv_ I3=$abc$44715$new_n1517_ O=$abc$44715$new_n1516_
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:51"
.param LUT_INIT 0000110011000000
.gate SB_LUT4 I0=$false I1=common.pb.spitx_crc[1] I2=common.pb.spitx_ctrl_reply_data[17] I3=$abc$44715$techmap\common.pb.$xor$crc8_func.v:32$6050_Y_new_inv_ O=$abc$44715$new_n1517_
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:51"
.param LUT_INIT 1100001100111100
.gate SB_LUT4 I0=common.pb.spitx_crc[2] I1=common.pb.spitx_crc[3] I2=common.pb.spitx_ctrl_reply_data[19] I3=common.pb.spitx_ctrl_reply_data[18] O=$abc$44715$techmap\common.pb.$xor$crc8_func.v:28$6030_Y_new_inv_
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:56"
.param LUT_INIT 1001011001101001
.gate SB_LUT4 I0=common.pb.spitx_ctrl_reply_data[26] I1=common.pb.spitx_ctrl_reply_data[27] I2=common.pb.spitx_crc[2] I3=common.pb.spitx_crc[3] O=$abc$44715$techmap\common.pb.$xor$crc8_func.v:28$5985_Y_new_inv_
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:56"
.param LUT_INIT 1001011001101001
.gate SB_LUT4 I0=common.pb.spitx_ctrl_reply_data[25] I1=common.pb.spitx_ctrl_reply_data[31] I2=common.pb.spitx_crc[1] I3=common.pb.spitx_crc[7] O=$abc$44715$new_n1520_
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:56"
.param LUT_INIT 1001011001101001
.gate SB_LUT4 I0=$abc$44715$new_n1474_ I1=$abc$44715$techmap\common.pb.$xor$crc8_func.v:28$6075_Y_new_inv_ I2=$abc$44715$techmap\common.pb.$xor$crc8_func.v:26$6061_Y_new_inv_ I3=$abc$44715$techmap\common.pb.$xor$crc8_func.v:32$6095_Y_new_inv_ O=$abc$44715$new_n1521_
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:56"
.param LUT_INIT 0010100010000010
.gate SB_LUT4 I0=common.pb.spitx_crc[2] I1=common.pb.spitx_crc[3] I2=common.pb.spitx_ctrl_reply_data[11] I3=common.pb.spitx_ctrl_reply_data[10] O=$abc$44715$techmap\common.pb.$xor$crc8_func.v:28$6075_Y_new_inv_
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:56"
.param LUT_INIT 1001011001101001
.gate SB_LUT4 I0=$false I1=$abc$44715$techmap\common.pb.$procmux$10684_CMP_new_ I2=$abc$44715$techmap\common.pb.$xor$crc8_func.v:28$6120_Y_new_inv_ I3=$abc$44715$new_n1524_ O=$abc$44715$techmap$techmap\common.pb.$procmux$12803.$and$/home/mb/fpga-toolchain/yosys/bin/../share/yosys/techmap.v:434$19138_Y[3]_new_
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:51"
.param LUT_INIT 0000110011000000
.gate SB_LUT4 I0=$false I1=common.pb.spitx_crc[7] I2=common.pb.spitx_ctrl_reply_data[7] I3=$abc$44715$techmap\common.pb.$xor$crc8_func.v:26$6106_Y_new_inv_ O=$abc$44715$new_n1524_
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:51"
.param LUT_INIT 1100001100111100
.gate SB_LUT4 I0=common.pb.spitx_crc[2] I1=common.pb.spitx_crc[3] I2=common.pb.spitx_ctrl_reply_data[3] I3=common.pb.spitx_ctrl_reply_data[2] O=$abc$44715$techmap\common.pb.$xor$crc8_func.v:28$6120_Y_new_inv_
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:56"
.param LUT_INIT 1001011001101001
.gate SB_LUT4 I0=$false I1=$abc$44715$new_n1527_ I2=$abc$44715$techmap$techmap\common.pb.$procmux$12803.$and$/home/mb/fpga-toolchain/yosys/bin/../share/yosys/techmap.v:434$19140_Y[4]_new_ I3=$abc$44715$new_n1466_ O=$abc$44715$techmap$techmap\common.pb.$procmux$12803.$reduce_or$/home/mb/fpga-toolchain/yosys/bin/../share/yosys/techmap.v:441$19148_Y
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:51"
.param LUT_INIT 1111111111110011
.gate SB_LUT4 I0=$abc$44715$new_n1531_ I1=$abc$44715$new_n1530_ I2=$abc$44715$techmap$techmap\common.pb.$procmux$12803.$and$/home/mb/fpga-toolchain/yosys/bin/../share/yosys/techmap.v:434$19141_Y[4]_new_ I3=$abc$44715$new_n1528_ O=$abc$44715$new_n1527_
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:56"
.param LUT_INIT 0000000000000001
.gate SB_LUT4 I0=$abc$44715$new_n1474_ I1=common.pb.spitx_crc[4] I2=common.pb.spitx_ctrl_reply_data[12] I3=$abc$44715$techmap\common.pb.$xor$crc8_func.v:28$6075_Y_new_inv_ O=$abc$44715$new_n1528_
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:56"
.param LUT_INIT 0010100010000010
.gate SB_LUT4 I0=$abc$44715$auto$rtlil.cc:1835:ReduceAnd$16071_new_ I1=common.pb.spitx_ctrl_reply_data[28] I2=common.pb.spitx_crc[4] I3=$abc$44715$techmap\common.pb.$xor$crc8_func.v:28$5985_Y_new_inv_ O=$abc$44715$techmap$techmap\common.pb.$procmux$12803.$and$/home/mb/fpga-toolchain/yosys/bin/../share/yosys/techmap.v:434$19141_Y[4]_new_
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:56"
.param LUT_INIT 0010100010000010
.gate SB_LUT4 I0=$abc$44715$new_n1490_ I1=common.pb.spitx_crc[4] I2=common.pb.spitx_ctrl_reply[4] I3=$abc$44715$techmap\common.pb.$xor$crc8_func.v:28$5940_Y_new_inv_ O=$abc$44715$new_n1530_
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:56"
.param LUT_INIT 0010100010000010
.gate SB_LUT4 I0=$abc$44715$techmap\common.pb.$procmux$10684_CMP_new_ I1=common.pb.spitx_crc[4] I2=common.pb.spitx_ctrl_reply_data[4] I3=$abc$44715$techmap\common.pb.$xor$crc8_func.v:28$6120_Y_new_inv_ O=$abc$44715$new_n1531_
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:56"
.param LUT_INIT 0010100010000010
.gate SB_LUT4 I0=$abc$44715$techmap\common.pb.$procmux$10686_CMP_new_ I1=common.pb.spitx_crc[4] I2=common.pb.spitx_ctrl_reply_data[20] I3=$abc$44715$techmap\common.pb.$xor$crc8_func.v:28$6030_Y_new_inv_ O=$abc$44715$techmap$techmap\common.pb.$procmux$12803.$and$/home/mb/fpga-toolchain/yosys/bin/../share/yosys/techmap.v:434$19140_Y[4]_new_
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:56"
.param LUT_INIT 0010100010000010
.gate SB_LUT4 I0=$false I1=$abc$44715$new_n1534_ I2=$abc$44715$new_n1543_ I3=$abc$44715$new_n1466_ O=$abc$44715$techmap$techmap\common.pb.$procmux$12803.$reduce_or$/home/mb/fpga-toolchain/yosys/bin/../share/yosys/techmap.v:441$19149_Y
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:51"
.param LUT_INIT 1111111111110011
.gate SB_LUT4 I0=$abc$44715$new_n1541_ I1=$abc$44715$new_n1539_ I2=$abc$44715$new_n1537_ I3=$abc$44715$techmap$techmap\common.pb.$procmux$12803.$and$/home/mb/fpga-toolchain/yosys/bin/../share/yosys/techmap.v:434$19140_Y[5]_new_ O=$abc$44715$new_n1534_
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:56"
.param LUT_INIT 0000000000000001
.gate SB_LUT4 I0=$abc$44715$techmap\common.pb.$procmux$10686_CMP_new_ I1=common.pb.spitx_crc[3] I2=common.pb.spitx_ctrl_reply_data[19] I3=$abc$44715$techmap\common.pb.$xor$crc8_func.v:30$6042_Y_new_inv_ O=$abc$44715$techmap$techmap\common.pb.$procmux$12803.$and$/home/mb/fpga-toolchain/yosys/bin/../share/yosys/techmap.v:434$19140_Y[5]_new_
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:56"
.param LUT_INIT 0010100010000010
.gate SB_LUT4 I0=common.pb.spitx_crc[4] I1=common.pb.spitx_crc[5] I2=common.pb.spitx_ctrl_reply_data[21] I3=common.pb.spitx_ctrl_reply_data[20] O=$abc$44715$techmap\common.pb.$xor$crc8_func.v:30$6042_Y_new_inv_
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:56"
.param LUT_INIT 1001011001101001
.gate SB_LUT4 I0=$abc$44715$new_n1490_ I1=common.pb.spitx_crc[3] I2=common.pb.spitx_ctrl_reply[3] I3=$abc$44715$techmap\common.pb.$xor$crc8_func.v:30$5952_Y_new_inv_ O=$abc$44715$new_n1537_
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:56"
.param LUT_INIT 0010100010000010
.gate SB_LUT4 I0=common.pb.spitx_crc[4] I1=common.pb.spitx_crc[5] I2=common.pb.spitx_ctrl_reply[5] I3=common.pb.spitx_ctrl_reply[4] O=$abc$44715$techmap\common.pb.$xor$crc8_func.v:30$5952_Y_new_inv_
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:56"
.param LUT_INIT 1001011001101001
.gate SB_LUT4 I0=$abc$44715$techmap\common.pb.$procmux$10684_CMP_new_ I1=common.pb.spitx_crc[3] I2=common.pb.spitx_ctrl_reply_data[3] I3=$abc$44715$techmap\common.pb.$xor$crc8_func.v:30$6132_Y_new_inv_ O=$abc$44715$new_n1539_
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:56"
.param LUT_INIT 0010100010000010
.gate SB_LUT4 I0=common.pb.spitx_crc[4] I1=common.pb.spitx_crc[5] I2=common.pb.spitx_ctrl_reply_data[4] I3=common.pb.spitx_ctrl_reply_data[5] O=$abc$44715$techmap\common.pb.$xor$crc8_func.v:30$6132_Y_new_inv_
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:56"
.param LUT_INIT 1001011001101001
.gate SB_LUT4 I0=$abc$44715$auto$rtlil.cc:1835:ReduceAnd$16071_new_ I1=common.pb.spitx_ctrl_reply_data[27] I2=common.pb.spitx_crc[3] I3=$abc$44715$techmap\common.pb.$xor$crc8_func.v:30$5997_Y_new_inv_ O=$abc$44715$new_n1541_
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:56"
.param LUT_INIT 0010100010000010
.gate SB_LUT4 I0=common.pb.spitx_ctrl_reply_data[28] I1=common.pb.spitx_ctrl_reply_data[29] I2=common.pb.spitx_crc[4] I3=common.pb.spitx_crc[5] O=$abc$44715$techmap\common.pb.$xor$crc8_func.v:30$5997_Y_new_inv_
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:56"
.param LUT_INIT 1001011001101001
.gate SB_LUT4 I0=$abc$44715$new_n1474_ I1=common.pb.spitx_crc[3] I2=common.pb.spitx_ctrl_reply_data[11] I3=$abc$44715$techmap\common.pb.$xor$crc8_func.v:30$6087_Y_new_inv_ O=$abc$44715$new_n1543_
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:56"
.param LUT_INIT 0010100010000010
.gate SB_LUT4 I0=common.pb.spitx_crc[4] I1=common.pb.spitx_crc[5] I2=common.pb.spitx_ctrl_reply_data[13] I3=common.pb.spitx_ctrl_reply_data[12] O=$abc$44715$techmap\common.pb.$xor$crc8_func.v:30$6087_Y_new_inv_
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:56"
.param LUT_INIT 1001011001101001
.gate SB_LUT4 I0=$false I1=$abc$44715$new_n1546_ I2=$abc$44715$techmap$techmap\common.pb.$procmux$12803.$and$/home/mb/fpga-toolchain/yosys/bin/../share/yosys/techmap.v:434$19138_Y[6]_new_ I3=$abc$44715$new_n1466_ O=$abc$44715$techmap$techmap\common.pb.$procmux$12803.$reduce_or$/home/mb/fpga-toolchain/yosys/bin/../share/yosys/techmap.v:441$19150_Y
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:51"
.param LUT_INIT 1111111111110011
.gate SB_LUT4 I0=$abc$44715$new_n1550_ I1=$abc$44715$new_n1549_ I2=$abc$44715$techmap$techmap\common.pb.$procmux$12803.$and$/home/mb/fpga-toolchain/yosys/bin/../share/yosys/techmap.v:434$19141_Y[6]_new_ I3=$abc$44715$new_n1547_ O=$abc$44715$new_n1546_
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:56"
.param LUT_INIT 0000000000000001
.gate SB_LUT4 I0=$abc$44715$new_n1474_ I1=common.pb.spitx_crc[6] I2=common.pb.spitx_ctrl_reply_data[14] I3=$abc$44715$techmap\common.pb.$xor$crc8_func.v:30$6087_Y_new_inv_ O=$abc$44715$new_n1547_
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:56"
.param LUT_INIT 0010100010000010
.gate SB_LUT4 I0=$false I1=$abc$44715$auto$rtlil.cc:1835:ReduceAnd$16071_new_ I2=$abc$44715$techmap\common.pb.$xor$crc8_func.v:30$5997_Y_new_inv_ I3=$abc$44715$techmap\common.pb.$xor$crc8_func.v:31$6000_Y_new_inv_ O=$abc$44715$techmap$techmap\common.pb.$procmux$12803.$and$/home/mb/fpga-toolchain/yosys/bin/../share/yosys/techmap.v:434$19141_Y[6]_new_
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:51"
.param LUT_INIT 0000110011000000
.gate SB_LUT4 I0=$abc$44715$new_n1490_ I1=common.pb.spitx_crc[6] I2=common.pb.spitx_ctrl_reply[6] I3=$abc$44715$techmap\common.pb.$xor$crc8_func.v:30$5952_Y_new_inv_ O=$abc$44715$new_n1549_
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:56"
.param LUT_INIT 0010100010000010
.gate SB_LUT4 I0=$abc$44715$techmap\common.pb.$procmux$10686_CMP_new_ I1=common.pb.spitx_crc[6] I2=common.pb.spitx_ctrl_reply_data[22] I3=$abc$44715$techmap\common.pb.$xor$crc8_func.v:30$6042_Y_new_inv_ O=$abc$44715$new_n1550_
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:56"
.param LUT_INIT 0010100010000010
.gate SB_LUT4 I0=$false I1=$abc$44715$techmap\common.pb.$procmux$10684_CMP_new_ I2=$abc$44715$techmap\common.pb.$xor$crc8_func.v:30$6132_Y_new_inv_ I3=$abc$44715$techmap\common.pb.$xor$crc8_func.v:31$6135_Y_new_inv_ O=$abc$44715$techmap$techmap\common.pb.$procmux$12803.$and$/home/mb/fpga-toolchain/yosys/bin/../share/yosys/techmap.v:434$19138_Y[6]_new_
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:51"
.param LUT_INIT 0000110011000000
.gate SB_LUT4 I0=$false I1=$abc$44715$auto$simplemap.cc:127:simplemap_reduce$24617_new_inv_ I2=$abc$44715$new_n1560_ I3=$abc$44715$new_n1466_ O=$abc$44715$techmap$techmap\common.pb.$procmux$12803.$reduce_or$/home/mb/fpga-toolchain/yosys/bin/../share/yosys/techmap.v:441$19151_Y
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:51"
.param LUT_INIT 1111111111110011
.gate SB_LUT4 I0=$abc$44715$new_n1558_ I1=$abc$44715$new_n1557_ I2=$abc$44715$new_n1555_ I3=$abc$44715$techmap$techmap\common.pb.$procmux$12803.$and$/home/mb/fpga-toolchain/yosys/bin/../share/yosys/techmap.v:434$19138_Y[7]_new_ O=$abc$44715$auto$simplemap.cc:127:simplemap_reduce$24617_new_inv_
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:56"
.param LUT_INIT 0000000000000001
.gate SB_LUT4 I0=$abc$44715$techmap\common.pb.$procmux$10684_CMP_new_ I1=common.pb.spitx_crc[5] I2=common.pb.spitx_ctrl_reply_data[5] I3=$abc$44715$techmap\common.pb.$xor$crc8_func.v:32$6142_Y_new_inv_ O=$abc$44715$techmap$techmap\common.pb.$procmux$12803.$and$/home/mb/fpga-toolchain/yosys/bin/../share/yosys/techmap.v:434$19138_Y[7]_new_
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:56"
.param LUT_INIT 0010100010000010
.gate SB_LUT4 I0=$abc$44715$new_n1474_ I1=common.pb.spitx_crc[5] I2=common.pb.spitx_ctrl_reply_data[13] I3=$abc$44715$techmap\common.pb.$xor$crc8_func.v:32$6097_Y_new_ O=$abc$44715$new_n1555_
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:56"
.param LUT_INIT 1000001000101000
.gate SB_LUT4 I0=$false I1=common.pb.spitx_crc[6] I2=common.pb.spitx_ctrl_reply_data[14] I3=$abc$44715$techmap\common.pb.$xor$crc8_func.v:32$6095_Y_new_inv_ O=$abc$44715$techmap\common.pb.$xor$crc8_func.v:32$6097_Y_new_
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:51"
.param LUT_INIT 0011110011000011
.gate SB_LUT4 I0=$abc$44715$auto$rtlil.cc:1835:ReduceAnd$16071_new_ I1=common.pb.spitx_ctrl_reply_data[29] I2=common.pb.spitx_crc[5] I3=$abc$44715$techmap\common.pb.$xor$crc8_func.v:32$6007_Y_new_inv_ O=$abc$44715$new_n1557_
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:56"
.param LUT_INIT 0010100010000010
.gate SB_LUT4 I0=$abc$44715$techmap\common.pb.$procmux$10686_CMP_new_ I1=common.pb.spitx_crc[5] I2=common.pb.spitx_ctrl_reply_data[21] I3=$abc$44715$techmap\common.pb.$xor$crc8_func.v:32$6052_Y_new_ O=$abc$44715$new_n1558_
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:56"
.param LUT_INIT 1000001000101000
.gate SB_LUT4 I0=$false I1=common.pb.spitx_crc[6] I2=common.pb.spitx_ctrl_reply_data[22] I3=$abc$44715$techmap\common.pb.$xor$crc8_func.v:32$6050_Y_new_inv_ O=$abc$44715$techmap\common.pb.$xor$crc8_func.v:32$6052_Y_new_
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:51"
.param LUT_INIT 0011110011000011
.gate SB_LUT4 I0=$abc$44715$new_n1490_ I1=common.pb.spitx_crc[5] I2=common.pb.spitx_ctrl_reply[5] I3=$abc$44715$techmap\common.pb.$xor$crc8_func.v:32$5962_Y_new_ O=$abc$44715$new_n1560_
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:56"
.param LUT_INIT 1000001000101000
.gate SB_LUT4 I0=$false I1=$false I2=$abc$44715$new_n1571_ I3=$abc$44715$auto$simplemap.cc:250:simplemap_eqne$30621[1]_new_ O=$abc$44715$techmap$techmap\common.pb.$procmux$12992.$reduce_or$/home/mb/fpga-toolchain/yosys/bin/../share/yosys/techmap.v:441$18830_Y
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:46"
.param LUT_INIT 0000000000001111
.gate SB_LUT4 I0=$false I1=$false I2=$abc$44715$new_n1567_ I3=$abc$44715$auto$simplemap.cc:250:simplemap_eqne$32324[1]_new_ O=$abc$44715$auto$simplemap.cc:250:simplemap_eqne$30621[1]_new_
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:46"
.param LUT_INIT 0000000011110000
.gate SB_LUT4 I0=$false I1=$false I2=$abc$44715$auto$simplemap.cc:127:simplemap_reduce$17870[1]_new_inv_ I3=$abc$44715$auto$simplemap.cc:127:simplemap_reduce$18777[0]_new_inv_ O=$abc$44715$auto$simplemap.cc:250:simplemap_eqne$32324[1]_new_
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:46"
.param LUT_INIT 1111000000000000
.gate SB_LUT4 I0=$false I1=$abc$44715$auto$simplemap.cc:127:simplemap_reduce$18772[1]_new_inv_ I2=common.pb.spirx_ctrl[0] I3=common.pb.spirx_ctrl[1] O=$abc$44715$auto$simplemap.cc:127:simplemap_reduce$18777[0]_new_inv_
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:51"
.param LUT_INIT 0000000000001100
.gate SB_LUT4 I0=$false I1=$false I2=common.pb.spirx_ctrl[2] I3=common.pb.spirx_ctrl[3] O=$abc$44715$auto$simplemap.cc:127:simplemap_reduce$18772[1]_new_inv_
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:46"
.param LUT_INIT 0000000011110000
.gate SB_LUT4 I0=common.pb.spirx_ctrl[7] I1=common.pb.spirx_ctrl[6] I2=common.pb.spirx_ctrl[5] I3=common.pb.spirx_ctrl[4] O=$abc$44715$auto$simplemap.cc:127:simplemap_reduce$17870[1]_new_inv_
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:56"
.param LUT_INIT 0000000000000001
.gate SB_LUT4 I0=$false I1=$false I2=$abc$44715$new_n1570_ I3=$abc$44715$auto$simplemap.cc:256:simplemap_eqne$18746_new_inv_ O=$abc$44715$new_n1567_
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:46"
.param LUT_INIT 0000000000001111
.gate SB_LUT4 I0=common.pb.spirx_ctrl[0] I1=$abc$44715$auto$simplemap.cc:127:simplemap_reduce$17870[1]_new_inv_ I2=$abc$44715$auto$simplemap.cc:127:simplemap_reduce$17865[1]_new_inv_ I3=common.pb.spirx_ctrl[1] O=$abc$44715$auto$simplemap.cc:256:simplemap_eqne$18746_new_inv_
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:56"
.param LUT_INIT 0000000010000000
.gate SB_LUT4 I0=$false I1=$false I2=common.pb.spirx_ctrl[3] I3=common.pb.spirx_ctrl[2] O=$abc$44715$auto$simplemap.cc:127:simplemap_reduce$17865[1]_new_inv_
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:46"
.param LUT_INIT 0000000000001111
.gate SB_LUT4 I0=$false I1=common.pb.spirx_ctrl[1] I2=$abc$44715$auto$simplemap.cc:127:simplemap_reduce$18772[1]_new_inv_ I3=$abc$44715$auto$simplemap.cc:127:simplemap_reduce$17870[1]_new_inv_ O=$abc$44715$new_n1570_
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:51"
.param LUT_INIT 1100000000000000
.gate SB_LUT4 I0=$abc$44715$auto$simplemap.cc:250:simplemap_eqne$19803_new_inv_ I1=common.pb.spitx_ctrl_reply_data[6] I2=$abc$44715$new_n1570_ I3=common.pb.spirx_ctrl_data[6] O=$abc$44715$new_n1571_
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:56"
.param LUT_INIT 0001101110111011
.gate SB_LUT4 I0=$false I1=$false I2=common.pb.spitx_ctrl_pending I3=common.pb.spitx_ctrl_pending_ack O=$abc$44715$auto$simplemap.cc:250:simplemap_eqne$19803_new_inv_
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:46"
.param LUT_INIT 1111000000001111
.gate SB_LUT4 I0=$false I1=$false I2=$abc$44715$new_n1574_ I3=$abc$44715$auto$simplemap.cc:250:simplemap_eqne$30621[1]_new_ O=$abc$44715$techmap$techmap\common.pb.$procmux$12992.$reduce_or$/home/mb/fpga-toolchain/yosys/bin/../share/yosys/techmap.v:441$18831_Y
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:46"
.param LUT_INIT 0000000000001111
.gate SB_LUT4 I0=$abc$44715$auto$simplemap.cc:250:simplemap_eqne$19803_new_inv_ I1=common.pb.spitx_ctrl_reply_data[7] I2=$abc$44715$new_n1570_ I3=common.pb.spirx_ctrl_data[7] O=$abc$44715$new_n1574_
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:56"
.param LUT_INIT 0001101110111011
.gate SB_LUT4 I0=$false I1=$false I2=$abc$44715$new_n1576_ I3=$abc$44715$auto$simplemap.cc:250:simplemap_eqne$30621[1]_new_ O=$abc$44715$techmap$techmap\common.pb.$procmux$12992.$reduce_or$/home/mb/fpga-toolchain/yosys/bin/../share/yosys/techmap.v:441$18832_Y
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:46"
.param LUT_INIT 0000000000001111
.gate SB_LUT4 I0=$abc$44715$auto$simplemap.cc:250:simplemap_eqne$19803_new_inv_ I1=common.pb.spitx_ctrl_reply_data[8] I2=$abc$44715$new_n1570_ I3=common.pb.spirx_ctrl_data[8] O=$abc$44715$new_n1576_
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:56"
.param LUT_INIT 0001101110111011
.gate SB_LUT4 I0=$false I1=$false I2=$abc$44715$new_n1578_ I3=$abc$44715$auto$simplemap.cc:250:simplemap_eqne$30621[1]_new_ O=$abc$44715$techmap$techmap\common.pb.$procmux$12992.$reduce_or$/home/mb/fpga-toolchain/yosys/bin/../share/yosys/techmap.v:441$18833_Y
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:46"
.param LUT_INIT 0000000000001111
.gate SB_LUT4 I0=$abc$44715$auto$simplemap.cc:250:simplemap_eqne$19803_new_inv_ I1=common.pb.spitx_ctrl_reply_data[9] I2=$abc$44715$new_n1570_ I3=common.pb.spirx_ctrl_data[9] O=$abc$44715$new_n1578_
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:56"
.param LUT_INIT 0001101110111011
.gate SB_LUT4 I0=$false I1=$false I2=$abc$44715$new_n1580_ I3=$abc$44715$auto$simplemap.cc:250:simplemap_eqne$30621[1]_new_ O=$abc$44715$techmap$techmap\common.pb.$procmux$12992.$reduce_or$/home/mb/fpga-toolchain/yosys/bin/../share/yosys/techmap.v:441$18834_Y
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:46"
.param LUT_INIT 0000000000001111
.gate SB_LUT4 I0=$abc$44715$auto$simplemap.cc:250:simplemap_eqne$19803_new_inv_ I1=common.pb.spitx_ctrl_reply_data[10] I2=$abc$44715$new_n1570_ I3=common.pb.spirx_ctrl_data[10] O=$abc$44715$new_n1580_
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:56"
.param LUT_INIT 0001101110111011
.gate SB_LUT4 I0=$false I1=$false I2=$abc$44715$new_n1582_ I3=$abc$44715$auto$simplemap.cc:250:simplemap_eqne$30621[1]_new_ O=$abc$44715$techmap$techmap\common.pb.$procmux$12992.$reduce_or$/home/mb/fpga-toolchain/yosys/bin/../share/yosys/techmap.v:441$18835_Y
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:46"
.param LUT_INIT 0000000000001111
.gate SB_LUT4 I0=$abc$44715$auto$simplemap.cc:250:simplemap_eqne$19803_new_inv_ I1=common.pb.spitx_ctrl_reply_data[11] I2=$abc$44715$new_n1570_ I3=common.pb.spirx_ctrl_data[11] O=$abc$44715$new_n1582_
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:56"
.param LUT_INIT 0001101110111011
.gate SB_LUT4 I0=$false I1=$false I2=$abc$44715$new_n1584_ I3=$abc$44715$auto$simplemap.cc:250:simplemap_eqne$30621[1]_new_ O=$abc$44715$techmap$techmap\common.pb.$procmux$12992.$reduce_or$/home/mb/fpga-toolchain/yosys/bin/../share/yosys/techmap.v:441$18836_Y
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:46"
.param LUT_INIT 0000000000001111
.gate SB_LUT4 I0=$abc$44715$auto$simplemap.cc:250:simplemap_eqne$19803_new_inv_ I1=common.pb.spitx_ctrl_reply_data[12] I2=$abc$44715$new_n1570_ I3=common.pb.spirx_ctrl_data[12] O=$abc$44715$new_n1584_
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:56"
.param LUT_INIT 0001101110111011
.gate SB_LUT4 I0=$false I1=$false I2=$abc$44715$new_n1586_ I3=$abc$44715$auto$simplemap.cc:250:simplemap_eqne$30621[1]_new_ O=$abc$44715$techmap$techmap\common.pb.$procmux$12992.$reduce_or$/home/mb/fpga-toolchain/yosys/bin/../share/yosys/techmap.v:441$18837_Y
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:46"
.param LUT_INIT 0000000000001111
.gate SB_LUT4 I0=$abc$44715$auto$simplemap.cc:250:simplemap_eqne$19803_new_inv_ I1=common.pb.spitx_ctrl_reply_data[13] I2=$abc$44715$new_n1570_ I3=common.pb.spirx_ctrl_data[13] O=$abc$44715$new_n1586_
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:56"
.param LUT_INIT 0001101110111011
.gate SB_LUT4 I0=$false I1=$false I2=$abc$44715$new_n1588_ I3=$abc$44715$auto$simplemap.cc:250:simplemap_eqne$30621[1]_new_ O=$abc$44715$techmap$techmap\common.pb.$procmux$12992.$reduce_or$/home/mb/fpga-toolchain/yosys/bin/../share/yosys/techmap.v:441$18838_Y
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:46"
.param LUT_INIT 0000000000001111
.gate SB_LUT4 I0=$abc$44715$auto$simplemap.cc:250:simplemap_eqne$19803_new_inv_ I1=common.pb.spitx_ctrl_reply_data[14] I2=$abc$44715$new_n1570_ I3=common.pb.spirx_ctrl_data[14] O=$abc$44715$new_n1588_
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:56"
.param LUT_INIT 0001101110111011
.gate SB_LUT4 I0=$false I1=$false I2=$abc$44715$new_n1590_ I3=$abc$44715$auto$simplemap.cc:250:simplemap_eqne$30621[1]_new_ O=$abc$44715$techmap$techmap\common.pb.$procmux$12992.$reduce_or$/home/mb/fpga-toolchain/yosys/bin/../share/yosys/techmap.v:441$18839_Y
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:46"
.param LUT_INIT 0000000000001111
.gate SB_LUT4 I0=$abc$44715$auto$simplemap.cc:250:simplemap_eqne$19803_new_inv_ I1=common.pb.spitx_ctrl_reply_data[15] I2=$abc$44715$new_n1570_ I3=common.pb.spirx_ctrl_data[15] O=$abc$44715$new_n1590_
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:56"
.param LUT_INIT 0001101110111011
.gate SB_LUT4 I0=$false I1=$false I2=$abc$44715$new_n1592_ I3=$abc$44715$auto$simplemap.cc:250:simplemap_eqne$30621[1]_new_ O=$abc$44715$techmap$techmap\common.pb.$procmux$12992.$reduce_or$/home/mb/fpga-toolchain/yosys/bin/../share/yosys/techmap.v:441$18840_Y
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:46"
.param LUT_INIT 0000000000001111
.gate SB_LUT4 I0=$abc$44715$auto$simplemap.cc:250:simplemap_eqne$19803_new_inv_ I1=common.pb.spitx_ctrl_reply_data[16] I2=$abc$44715$new_n1570_ I3=common.pb.spirx_ctrl_data[16] O=$abc$44715$new_n1592_
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:56"
.param LUT_INIT 0001101110111011
.gate SB_LUT4 I0=$false I1=$false I2=$abc$44715$new_n1594_ I3=$abc$44715$auto$simplemap.cc:250:simplemap_eqne$30621[1]_new_ O=$abc$44715$techmap$techmap\common.pb.$procmux$12992.$reduce_or$/home/mb/fpga-toolchain/yosys/bin/../share/yosys/techmap.v:441$18841_Y
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:46"
.param LUT_INIT 0000000000001111
.gate SB_LUT4 I0=$abc$44715$auto$simplemap.cc:250:simplemap_eqne$19803_new_inv_ I1=common.pb.spitx_ctrl_reply_data[17] I2=$abc$44715$new_n1570_ I3=common.pb.spirx_ctrl_data[17] O=$abc$44715$new_n1594_
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:56"
.param LUT_INIT 0001101110111011
.gate SB_LUT4 I0=$false I1=$false I2=$abc$44715$new_n1596_ I3=$abc$44715$auto$simplemap.cc:250:simplemap_eqne$30621[1]_new_ O=$abc$44715$techmap$techmap\common.pb.$procmux$12992.$reduce_or$/home/mb/fpga-toolchain/yosys/bin/../share/yosys/techmap.v:441$18842_Y
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:46"
.param LUT_INIT 0000000000001111
.gate SB_LUT4 I0=$abc$44715$auto$simplemap.cc:250:simplemap_eqne$19803_new_inv_ I1=common.pb.spitx_ctrl_reply_data[18] I2=$abc$44715$new_n1570_ I3=common.pb.spirx_ctrl_data[18] O=$abc$44715$new_n1596_
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:56"
.param LUT_INIT 0001101110111011
.gate SB_LUT4 I0=$false I1=$false I2=$abc$44715$new_n1598_ I3=$abc$44715$auto$simplemap.cc:250:simplemap_eqne$30621[1]_new_ O=$abc$44715$techmap$techmap\common.pb.$procmux$12992.$reduce_or$/home/mb/fpga-toolchain/yosys/bin/../share/yosys/techmap.v:441$18843_Y
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:46"
.param LUT_INIT 0000000000001111
.gate SB_LUT4 I0=$abc$44715$auto$simplemap.cc:250:simplemap_eqne$19803_new_inv_ I1=common.pb.spitx_ctrl_reply_data[19] I2=$abc$44715$new_n1570_ I3=common.pb.spirx_ctrl_data[19] O=$abc$44715$new_n1598_
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:56"
.param LUT_INIT 0001101110111011
.gate SB_LUT4 I0=$false I1=$false I2=$abc$44715$new_n1600_ I3=$abc$44715$auto$simplemap.cc:250:simplemap_eqne$30621[1]_new_ O=$abc$44715$techmap$techmap\common.pb.$procmux$12992.$reduce_or$/home/mb/fpga-toolchain/yosys/bin/../share/yosys/techmap.v:441$18844_Y
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:46"
.param LUT_INIT 0000000000001111
.gate SB_LUT4 I0=$abc$44715$auto$simplemap.cc:250:simplemap_eqne$19803_new_inv_ I1=common.pb.spitx_ctrl_reply_data[20] I2=$abc$44715$new_n1570_ I3=common.pb.spirx_ctrl_data[20] O=$abc$44715$new_n1600_
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:56"
.param LUT_INIT 0001101110111011
.gate SB_LUT4 I0=$false I1=$false I2=$abc$44715$new_n1602_ I3=$abc$44715$auto$simplemap.cc:250:simplemap_eqne$30621[1]_new_ O=$abc$44715$techmap$techmap\common.pb.$procmux$12992.$reduce_or$/home/mb/fpga-toolchain/yosys/bin/../share/yosys/techmap.v:441$18845_Y
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:46"
.param LUT_INIT 0000000000001111
.gate SB_LUT4 I0=$abc$44715$auto$simplemap.cc:250:simplemap_eqne$19803_new_inv_ I1=common.pb.spitx_ctrl_reply_data[21] I2=$abc$44715$new_n1570_ I3=common.pb.spirx_ctrl_data[21] O=$abc$44715$new_n1602_
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:56"
.param LUT_INIT 0001101110111011
.gate SB_LUT4 I0=$false I1=$false I2=$abc$44715$new_n1604_ I3=$abc$44715$auto$simplemap.cc:250:simplemap_eqne$30621[1]_new_ O=$abc$44715$techmap$techmap\common.pb.$procmux$12992.$reduce_or$/home/mb/fpga-toolchain/yosys/bin/../share/yosys/techmap.v:441$18846_Y
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:46"
.param LUT_INIT 0000000000001111
.gate SB_LUT4 I0=$abc$44715$auto$simplemap.cc:250:simplemap_eqne$19803_new_inv_ I1=common.pb.spitx_ctrl_reply_data[22] I2=$abc$44715$new_n1570_ I3=common.pb.spirx_ctrl_data[22] O=$abc$44715$new_n1604_
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:56"
.param LUT_INIT 0001101110111011
.gate SB_LUT4 I0=$false I1=$false I2=$abc$44715$new_n1606_ I3=$abc$44715$auto$simplemap.cc:250:simplemap_eqne$30621[1]_new_ O=$abc$44715$techmap$techmap\common.pb.$procmux$12992.$reduce_or$/home/mb/fpga-toolchain/yosys/bin/../share/yosys/techmap.v:441$18847_Y
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:46"
.param LUT_INIT 0000000000001111
.gate SB_LUT4 I0=$abc$44715$auto$simplemap.cc:250:simplemap_eqne$19803_new_inv_ I1=common.pb.spitx_ctrl_reply_data[23] I2=$abc$44715$new_n1570_ I3=common.pb.spirx_ctrl_data[23] O=$abc$44715$new_n1606_
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:56"
.param LUT_INIT 0001101110111011
.gate SB_LUT4 I0=$abc$44715$auto$simplemap.cc:250:simplemap_eqne$19803_new_inv_ I1=$abc$44715$auto$simplemap.cc:250:simplemap_eqne$30621[1]_new_ I2=$abc$44715$new_n1608_ I3=common.pb.spitx_ctrl_reply_data[4] O=$abc$44715$techmap$techmap\common.pb.$procmux$13013.$reduce_or$/home/mb/fpga-toolchain/yosys/bin/../share/yosys/techmap.v:441$18553_Y
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:56"
.param LUT_INIT 0001001100000010
.gate SB_LUT4 I0=$abc$44715$auto$simplemap.cc:250:simplemap_eqne$32324[1]_new_ I1=$abc$44715$techmap\common.pb.$0$func$\rx_buf_overflow_get$profibus_phy_mod.v:275$5346$\rx_buf_overflow_get[0:0]$6272_new_inv_ I2=common.pb.spirx_ctrl_data[4] I3=$abc$44715$new_n1570_ O=$abc$44715$new_n1608_
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:56"
.param LUT_INIT 0000110111011101
.gate SB_LUT4 I0=$false I1=$false I2=common.pb.rx_buf_overflow[0] I3=common.pb.rx_buf_overflow[1] O=$abc$44715$techmap\common.pb.$0$func$\rx_buf_overflow_get$profibus_phy_mod.v:275$5346$\rx_buf_overflow_get[0:0]$6272_new_inv_
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:46"
.param LUT_INIT 1111000000001111
.gate SB_LUT4 I0=$abc$44715$auto$simplemap.cc:250:simplemap_eqne$19803_new_inv_ I1=$abc$44715$auto$simplemap.cc:250:simplemap_eqne$30621[1]_new_ I2=$abc$44715$new_n1611_ I3=common.pb.spitx_ctrl_reply_data[3] O=$abc$44715$techmap$techmap\common.pb.$procmux$13034.$reduce_or$/home/mb/fpga-toolchain/yosys/bin/../share/yosys/techmap.v:441$18553_Y
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:56"
.param LUT_INIT 0001001100000010
.gate SB_LUT4 I0=$abc$44715$auto$simplemap.cc:250:simplemap_eqne$32324[1]_new_ I1=$abc$44715$techmap\common.pb.$0$func$\tx_buf_overflow_get$profibus_phy_mod.v:274$5345$\tx_buf_overflow_get[0:0]$6268_new_inv_ I2=common.pb.spirx_ctrl_data[3] I3=$abc$44715$new_n1570_ O=$abc$44715$new_n1611_
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:56"
.param LUT_INIT 0000110111011101
.gate SB_LUT4 I0=$false I1=$false I2=common.pb.tx_buf_overflow[0] I3=common.pb.tx_buf_overflow[1] O=$abc$44715$techmap\common.pb.$0$func$\tx_buf_overflow_get$profibus_phy_mod.v:274$5345$\tx_buf_overflow_get[0:0]$6268_new_inv_
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:46"
.param LUT_INIT 1111000000001111
.gate SB_LUT4 I0=$abc$44715$auto$simplemap.cc:250:simplemap_eqne$19803_new_inv_ I1=$abc$44715$auto$simplemap.cc:250:simplemap_eqne$30621[1]_new_ I2=$abc$44715$new_n1614_ I3=common.pb.spitx_ctrl_reply_data[2] O=$abc$44715$techmap$techmap\common.pb.$procmux$13070.$reduce_or$/home/mb/fpga-toolchain/yosys/bin/../share/yosys/techmap.v:441$18553_Y
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:56"
.param LUT_INIT 0001001100000010
.gate SB_LUT4 I0=common.pb.softreset_status I1=$abc$44715$auto$simplemap.cc:250:simplemap_eqne$32324[1]_new_ I2=$abc$44715$new_n1570_ I3=common.pb.spirx_ctrl_data[2] O=$abc$44715$new_n1614_
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:56"
.param LUT_INIT 0000011101110111
.gate SB_LUT4 I0=$abc$44715$auto$simplemap.cc:250:simplemap_eqne$19803_new_inv_ I1=$abc$44715$auto$simplemap.cc:250:simplemap_eqne$30621[1]_new_ I2=$abc$44715$new_n1616_ I3=common.pb.spitx_ctrl_reply_data[1] O=$abc$44715$techmap$techmap\common.pb.$procmux$13106.$reduce_or$/home/mb/fpga-toolchain/yosys/bin/../share/yosys/techmap.v:441$18553_Y
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:56"
.param LUT_INIT 0001001100000010
.gate SB_LUT4 I0=$abc$44715$auto$simplemap.cc:250:simplemap_eqne$32324[1]_new_ I1=common.pb.n_hardreset_status I2=$abc$44715$new_n1570_ I3=common.pb.spirx_ctrl_data[1] O=$abc$44715$new_n1616_
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:56"
.param LUT_INIT 0000110111011101
.gate SB_LUT4 I0=$abc$44715$auto$simplemap.cc:250:simplemap_eqne$19803_new_inv_ I1=$abc$44715$auto$simplemap.cc:250:simplemap_eqne$30621[1]_new_ I2=$abc$44715$new_n1618_ I3=common.pb.spitx_ctrl_reply_data[0] O=$abc$44715$techmap$techmap\common.pb.$procmux$13142.$reduce_or$/home/mb/fpga-toolchain/yosys/bin/../share/yosys/techmap.v:441$18553_Y
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:56"
.param LUT_INIT 0001001100000010
.gate SB_LUT4 I0=$abc$44715$auto$simplemap.cc:250:simplemap_eqne$32324[1]_new_ I1=common.pb.n_poweronreset_status I2=$abc$44715$new_n1570_ I3=common.pb.spirx_ctrl_data[0] O=$abc$44715$new_n1618_
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:56"
.param LUT_INIT 0000110111011101
.gate SB_LUT4 I0=$abc$44715$auto$simplemap.cc:250:simplemap_eqne$19803_new_inv_ I1=$abc$44715$auto$simplemap.cc:250:simplemap_eqne$30621[1]_new_ I2=$abc$44715$new_n1620_ I3=common.pb.spitx_ctrl_reply_data[5] O=$abc$44715$techmap$techmap\common.pb.$procmux$13163.$reduce_or$/home/mb/fpga-toolchain/yosys/bin/../share/yosys/techmap.v:441$18553_Y
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:56"
.param LUT_INIT 0001001100000010
.gate SB_LUT4 I0=$abc$44715$auto$simplemap.cc:250:simplemap_eqne$32324[1]_new_ I1=$abc$44715$techmap\common.pb.$0$func$\spirx_ctrl_crcerr_get$profibus_phy_mod.v:275$5347$\spirx_ctrl_crcerr_get[0:0]$6276_new_inv_ I2=common.pb.spirx_ctrl_data[5] I3=$abc$44715$new_n1570_ O=$abc$44715$new_n1620_
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:56"
.param LUT_INIT 0000110111011101
.gate SB_LUT4 I0=$false I1=$false I2=common.pb.spirx_ctrl_crcerr[0] I3=common.pb.spirx_ctrl_crcerr[1] O=$abc$44715$techmap\common.pb.$0$func$\spirx_ctrl_crcerr_get$profibus_phy_mod.v:275$5347$\spirx_ctrl_crcerr_get[0:0]$6276_new_inv_
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:46"
.param LUT_INIT 1111000000001111
.gate SB_LUT4 I0=$abc$44715$auto$simplemap.cc:250:simplemap_eqne$19803_new_inv_ I1=$abc$44715$auto$simplemap.cc:250:simplemap_eqne$30621[1]_new_ I2=$abc$44715$auto$simplemap.cc:127:simplemap_reduce$24713_new_inv_ I3=common.pb.spitx_ctrl_reply[0] O=$abc$44715$techmap$techmap\common.pb.$procmux$14211.$reduce_or$/home/mb/fpga-toolchain/yosys/bin/../share/yosys/techmap.v:441$18295_Y
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:56"
.param LUT_INIT 0001001100000010
.gate SB_LUT4 I0=$false I1=$false I2=$abc$44715$new_n1570_ I3=$abc$44715$auto$simplemap.cc:250:simplemap_eqne$32324[1]_new_ O=$abc$44715$auto$simplemap.cc:127:simplemap_reduce$24713_new_inv_
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:46"
.param LUT_INIT 0000000000001111
.gate SB_LUT4 I0=common.pb.spitx_ctrl_reply[1] I1=$abc$44715$auto$simplemap.cc:250:simplemap_eqne$19803_new_inv_ I2=$abc$44715$new_n1567_ I3=$abc$44715$auto$simplemap.cc:250:simplemap_eqne$32324[1]_new_ O=$abc$44715$techmap$techmap\common.pb.$procmux$14211.$reduce_or$/home/mb/fpga-toolchain/yosys/bin/../share/yosys/techmap.v:441$18296_Y
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:56"
.param LUT_INIT 0010111000001110
.gate SB_LUT4 I0=$abc$44715$auto$simplemap.cc:250:simplemap_eqne$19803_new_inv_ I1=$abc$44715$auto$simplemap.cc:250:simplemap_eqne$30621[1]_new_ I2=$abc$44715$auto$simplemap.cc:127:simplemap_reduce$24713_new_inv_ I3=common.pb.spitx_ctrl_reply[2] O=$abc$44715$techmap$techmap\common.pb.$procmux$14211.$reduce_or$/home/mb/fpga-toolchain/yosys/bin/../share/yosys/techmap.v:441$18297_Y
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:56"
.param LUT_INIT 0001001100000010
.gate SB_LUT4 I0=$false I1=common.pb.spitx_ctrl_reply[3] I2=$abc$44715$auto$simplemap.cc:250:simplemap_eqne$19803_new_inv_ I3=$abc$44715$auto$simplemap.cc:250:simplemap_eqne$30621[1]_new_ O=$abc$44715$techmap$techmap\common.pb.$procmux$14211.$reduce_or$/home/mb/fpga-toolchain/yosys/bin/../share/yosys/techmap.v:441$18298_Y
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:51"
.param LUT_INIT 0000000000001100
.gate SB_LUT4 I0=$false I1=common.pb.spitx_ctrl_reply[4] I2=$abc$44715$auto$simplemap.cc:250:simplemap_eqne$19803_new_inv_ I3=$abc$44715$auto$simplemap.cc:250:simplemap_eqne$30621[1]_new_ O=$abc$44715$techmap$techmap\common.pb.$procmux$14211.$reduce_or$/home/mb/fpga-toolchain/yosys/bin/../share/yosys/techmap.v:441$18299_Y
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:51"
.param LUT_INIT 0000000000001100
.gate SB_LUT4 I0=$false I1=common.pb.spitx_ctrl_reply[5] I2=$abc$44715$auto$simplemap.cc:250:simplemap_eqne$19803_new_inv_ I3=$abc$44715$auto$simplemap.cc:250:simplemap_eqne$30621[1]_new_ O=$abc$44715$techmap$techmap\common.pb.$procmux$14211.$reduce_or$/home/mb/fpga-toolchain/yosys/bin/../share/yosys/techmap.v:441$18300_Y
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:51"
.param LUT_INIT 0000000000001100
.gate SB_LUT4 I0=$false I1=common.pb.spitx_ctrl_reply[6] I2=$abc$44715$auto$simplemap.cc:250:simplemap_eqne$19803_new_inv_ I3=$abc$44715$auto$simplemap.cc:250:simplemap_eqne$30621[1]_new_ O=$abc$44715$techmap$techmap\common.pb.$procmux$14211.$reduce_or$/home/mb/fpga-toolchain/yosys/bin/../share/yosys/techmap.v:441$18301_Y
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:51"
.param LUT_INIT 0000000000001100
.gate SB_LUT4 I0=$false I1=common.pb.spitx_ctrl_reply[7] I2=$abc$44715$auto$simplemap.cc:250:simplemap_eqne$19803_new_inv_ I3=$abc$44715$auto$simplemap.cc:250:simplemap_eqne$30621[1]_new_ O=$abc$44715$techmap$techmap\common.pb.$procmux$14211.$reduce_or$/home/mb/fpga-toolchain/yosys/bin/../share/yosys/techmap.v:441$18302_Y
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:51"
.param LUT_INIT 0000000000001100
.gate SB_LUT4 I0=$abc$44715$techmap$techmap\common.pb.$procmux$14301.$and$/home/mb/fpga-toolchain/yosys/bin/../share/yosys/techmap.v:434$17895_Y[0]_new_ I1=$abc$44715$auto$simplemap.cc:168:logic_reduce$18573_new_inv_ I2=common.pb.spirx_crc[0] I3=$abc$44715$new_n1640_ O=$abc$44715$techmap$techmap\common.pb.$procmux$14301.$reduce_or$/home/mb/fpga-toolchain/yosys/bin/../share/yosys/techmap.v:441$17897_Y
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:56"
.param LUT_INIT 1110111011101010
.gate SB_LUT4 I0=common.pb.spi.rx_irq_r I1=$abc$44715$auto$opt_reduce.cc:132:opt_mux$15900_new_inv_ I2=$abc$44715$techmap\common.pb.$xor$crc8_func.v:25$5547_Y_new_inv_ I3=common.pb.spirx_crc[0] O=$abc$44715$techmap$techmap\common.pb.$procmux$14301.$and$/home/mb/fpga-toolchain/yosys/bin/../share/yosys/techmap.v:434$17895_Y[0]_new_
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:56"
.param LUT_INIT 0001001100000010
.gate SB_LUT4 I0=$false I1=$false I2=$abc$44715$techmap$techmap\common.pb.$procmux$14444.$and$/home/mb/fpga-toolchain/yosys/bin/../share/yosys/techmap.v:434$18189_Y[2]_new_ I3=$abc$44715$auto$simplemap.cc:309:simplemap_lut$17319_new_ O=$abc$44715$auto$opt_reduce.cc:132:opt_mux$15900_new_inv_
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:46"
.param LUT_INIT 0000000000001111
.gate SB_LUT4 I0=$false I1=$false I2=$abc$44715$auto$simplemap.cc:309:simplemap_lut$17316[0]_new_ I3=common.pb.spirx_state[2] O=$abc$44715$auto$simplemap.cc:309:simplemap_lut$17319_new_
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:46"
.param LUT_INIT 0000000011110000
.gate SB_LUT4 I0=$false I1=$false I2=common.pb.spirx_state[1] I3=common.pb.spirx_state[0] O=$abc$44715$auto$simplemap.cc:309:simplemap_lut$17316[0]_new_
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:46"
.param LUT_INIT 1111000000000000
.gate SB_LUT4 I0=$false I1=common.pb.spirx_state[2] I2=common.pb.spirx_state[1] I3=common.pb.spirx_state[0] O=$abc$44715$techmap$techmap\common.pb.$procmux$14444.$and$/home/mb/fpga-toolchain/yosys/bin/../share/yosys/techmap.v:434$18189_Y[2]_new_
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:51"
.param LUT_INIT 0000000000001100
.gate SB_LUT4 I0=common.pb.spirx_crc[0] I1=common.pb.spi.rx_data_r[0] I2=$abc$44715$auto$simplemap.cc:250:simplemap_eqne$19820[6]_new_inv_ I3=$abc$44715$auto$simplemap.cc:250:simplemap_eqne$19820[7]_new_inv_ O=$abc$44715$techmap\common.pb.$xor$crc8_func.v:25$5547_Y_new_inv_
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:56"
.param LUT_INIT 1001011001101001
.gate SB_LUT4 I0=$false I1=$false I2=common.pb.spirx_crc[7] I3=common.pb.spi.rx_data_r[7] O=$abc$44715$auto$simplemap.cc:250:simplemap_eqne$19820[7]_new_inv_
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:46"
.param LUT_INIT 1111000000001111
.gate SB_LUT4 I0=$false I1=$false I2=common.pb.spirx_crc[6] I3=common.pb.spi.rx_data_r[6] O=$abc$44715$auto$simplemap.cc:250:simplemap_eqne$19820[6]_new_inv_
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:46"
.param LUT_INIT 1111000000001111
.gate SB_LUT4 I0=$false I1=$abc$44715$new_n1643_ I2=$abc$44715$new_n1642_ I3=$abc$44715$new_n1641_ O=$abc$44715$new_n1640_
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:51"
.param LUT_INIT 1100000000000000
.gate SB_LUT4 I0=$false I1=$false I2=common.pb.spi.rx_data_r[1] I3=common.pb.spi.rx_irq_r O=$abc$44715$new_n1641_
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:46"
.param LUT_INIT 1111000000000000
.gate SB_LUT4 I0=common.pb.spi.rx_data_r[5] I1=common.pb.spi.rx_data_r[3] I2=common.pb.spi.rx_data_r[4] I3=common.pb.spi.rx_data_r[2] O=$abc$44715$new_n1642_
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:56"
.param LUT_INIT 0000000000001000
.gate SB_LUT4 I0=$false I1=common.pb.spi.rx_data_r[7] I2=common.pb.spi.rx_data_r[6] I3=common.pb.spi.rx_data_r[0] O=$abc$44715$new_n1643_
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:51"
.param LUT_INIT 0000000000001100
.gate SB_LUT4 I0=$false I1=common.pb.spirx_state[2] I2=common.pb.spirx_state[1] I3=common.pb.spirx_state[0] O=$abc$44715$auto$simplemap.cc:168:logic_reduce$18573_new_inv_
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:51"
.param LUT_INIT 0000000000000011
.gate SB_LUT4 I0=$abc$44715$techmap$techmap\common.pb.$procmux$14301.$and$/home/mb/fpga-toolchain/yosys/bin/../share/yosys/techmap.v:434$17895_Y[1]_new_ I1=$abc$44715$auto$simplemap.cc:168:logic_reduce$18573_new_inv_ I2=common.pb.spirx_crc[1] I3=$abc$44715$new_n1640_ O=$abc$44715$techmap$techmap\common.pb.$procmux$14301.$reduce_or$/home/mb/fpga-toolchain/yosys/bin/../share/yosys/techmap.v:441$17898_Y
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:56"
.param LUT_INIT 1110111011101010
.gate SB_LUT4 I0=$abc$44715$techmap$techmap\common.pb.$procmux$14301.$and$/home/mb/fpga-toolchain/yosys/bin/../share/yosys/techmap.v:434$17895_Y[2]_new_ I1=$abc$44715$auto$simplemap.cc:168:logic_reduce$18573_new_inv_ I2=common.pb.spirx_crc[2] I3=$abc$44715$new_n1640_ O=$abc$44715$techmap$techmap\common.pb.$procmux$14301.$reduce_or$/home/mb/fpga-toolchain/yosys/bin/../share/yosys/techmap.v:441$17899_Y
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:56"
.param LUT_INIT 1110111011101010
.gate SB_LUT4 I0=common.pb.spi.rx_irq_r I1=$abc$44715$auto$opt_reduce.cc:132:opt_mux$15900_new_inv_ I2=$abc$44715$techmap\common.pb.$xor$crc8_func.v:27$5559_Y_new_inv_ I3=common.pb.spirx_crc[2] O=$abc$44715$techmap$techmap\common.pb.$procmux$14301.$and$/home/mb/fpga-toolchain/yosys/bin/../share/yosys/techmap.v:434$17895_Y[2]_new_
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:56"
.param LUT_INIT 0001001100000010
.gate SB_LUT4 I0=common.pb.spirx_crc[0] I1=common.pb.spi.rx_data_r[0] I2=$abc$44715$techmap\common.pb.$xor$crc8_func.v:27$5555_Y_new_inv_ I3=$abc$44715$auto$simplemap.cc:250:simplemap_eqne$19820[6]_new_inv_ O=$abc$44715$techmap\common.pb.$xor$crc8_func.v:27$5559_Y_new_inv_
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:56"
.param LUT_INIT 1001011001101001
.gate SB_LUT4 I0=common.pb.spirx_crc[2] I1=common.pb.spirx_crc[1] I2=common.pb.spi.rx_data_r[1] I3=common.pb.spi.rx_data_r[2] O=$abc$44715$techmap\common.pb.$xor$crc8_func.v:27$5555_Y_new_inv_
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:56"
.param LUT_INIT 1001011001101001
.gate SB_LUT4 I0=$abc$44715$techmap$techmap\common.pb.$procmux$14301.$and$/home/mb/fpga-toolchain/yosys/bin/../share/yosys/techmap.v:434$17895_Y[3]_new_ I1=$abc$44715$auto$simplemap.cc:168:logic_reduce$18573_new_inv_ I2=common.pb.spirx_crc[3] I3=$abc$44715$new_n1640_ O=$abc$44715$techmap$techmap\common.pb.$procmux$14301.$reduce_or$/home/mb/fpga-toolchain/yosys/bin/../share/yosys/techmap.v:441$17900_Y
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:56"
.param LUT_INIT 1110111011101010
.gate SB_LUT4 I0=common.pb.spi.rx_irq_r I1=$abc$44715$auto$opt_reduce.cc:132:opt_mux$15900_new_inv_ I2=$abc$44715$techmap\common.pb.$xor$crc8_func.v:28$5566_Y_new_inv_ I3=common.pb.spirx_crc[3] O=$abc$44715$techmap$techmap\common.pb.$procmux$14301.$and$/home/mb/fpga-toolchain/yosys/bin/../share/yosys/techmap.v:434$17895_Y[3]_new_
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:56"
.param LUT_INIT 0001001100000010
.gate SB_LUT4 I0=common.pb.spirx_crc[3] I1=common.pb.spi.rx_data_r[3] I2=$abc$44715$techmap\common.pb.$xor$crc8_func.v:27$5555_Y_new_inv_ I3=$abc$44715$auto$simplemap.cc:250:simplemap_eqne$19820[7]_new_inv_ O=$abc$44715$techmap\common.pb.$xor$crc8_func.v:28$5566_Y_new_inv_
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:56"
.param LUT_INIT 1001011001101001
.gate SB_LUT4 I0=$abc$44715$techmap$techmap\common.pb.$procmux$14301.$and$/home/mb/fpga-toolchain/yosys/bin/../share/yosys/techmap.v:434$17895_Y[4]_new_ I1=$abc$44715$auto$simplemap.cc:168:logic_reduce$18573_new_inv_ I2=common.pb.spirx_crc[4] I3=$abc$44715$new_n1640_ O=$abc$44715$techmap$techmap\common.pb.$procmux$14301.$reduce_or$/home/mb/fpga-toolchain/yosys/bin/../share/yosys/techmap.v:441$17901_Y
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:56"
.param LUT_INIT 1110111011101010
.gate SB_LUT4 I0=common.pb.spi.rx_irq_r I1=$abc$44715$auto$opt_reduce.cc:132:opt_mux$15900_new_inv_ I2=$abc$44715$techmap\common.pb.$xor$crc8_func.v:29$5571_Y_new_inv_ I3=common.pb.spirx_crc[4] O=$abc$44715$techmap$techmap\common.pb.$procmux$14301.$and$/home/mb/fpga-toolchain/yosys/bin/../share/yosys/techmap.v:434$17895_Y[4]_new_
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:56"
.param LUT_INIT 0001001100000010
.gate SB_LUT4 I0=$false I1=common.pb.spirx_crc[2] I2=common.pb.spi.rx_data_r[2] I3=$abc$44715$techmap\common.pb.$xor$crc8_func.v:29$5569_Y_new_ O=$abc$44715$techmap\common.pb.$xor$crc8_func.v:29$5571_Y_new_inv_
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:51"
.param LUT_INIT 0011110011000011
.gate SB_LUT4 I0=common.pb.spirx_crc[4] I1=common.pb.spirx_crc[3] I2=common.pb.spi.rx_data_r[3] I3=common.pb.spi.rx_data_r[4] O=$abc$44715$techmap\common.pb.$xor$crc8_func.v:29$5569_Y_new_
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:56"
.param LUT_INIT 0110100110010110
.gate SB_LUT4 I0=$false I1=$abc$44715$techmap$techmap\common.pb.$procmux$14301.$and$/home/mb/fpga-toolchain/yosys/bin/../share/yosys/techmap.v:434$17896_Y[5]_new_ I2=$abc$44715$techmap\common.pb.$procmux$14299_Y[5]_new_inv_ I3=$abc$44715$auto$opt_reduce.cc:132:opt_mux$15900_new_inv_ O=$abc$44715$techmap$techmap\common.pb.$procmux$14301.$reduce_or$/home/mb/fpga-toolchain/yosys/bin/../share/yosys/techmap.v:441$17902_Y
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:51"
.param LUT_INIT 1100110011001111
.gate SB_LUT4 I0=$false I1=$abc$44715$auto$simplemap.cc:168:logic_reduce$18573_new_inv_ I2=$abc$44715$new_n1640_ I3=common.pb.spirx_crc[5] O=$abc$44715$techmap$techmap\common.pb.$procmux$14301.$and$/home/mb/fpga-toolchain/yosys/bin/../share/yosys/techmap.v:434$17896_Y[5]_new_
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:51"
.param LUT_INIT 1100110011000000
.gate SB_LUT4 I0=common.pb.spirx_crc[5] I1=common.pb.spi.rx_data_r[5] I2=$abc$44715$techmap\common.pb.$xor$crc8_func.v:29$5569_Y_new_ I3=common.pb.spi.rx_irq_r O=$abc$44715$techmap\common.pb.$procmux$14299_Y[5]_new_inv_
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:56"
.param LUT_INIT 0110100101010101
.gate SB_LUT4 I0=$abc$44715$techmap$techmap\common.pb.$procmux$14301.$and$/home/mb/fpga-toolchain/yosys/bin/../share/yosys/techmap.v:434$17895_Y[6]_new_ I1=$abc$44715$auto$simplemap.cc:168:logic_reduce$18573_new_inv_ I2=common.pb.spirx_crc[6] I3=$abc$44715$new_n1640_ O=$abc$44715$techmap$techmap\common.pb.$procmux$14301.$reduce_or$/home/mb/fpga-toolchain/yosys/bin/../share/yosys/techmap.v:441$17903_Y
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:56"
.param LUT_INIT 1110111011101010
.gate SB_LUT4 I0=common.pb.spi.rx_irq_r I1=$abc$44715$auto$opt_reduce.cc:132:opt_mux$15900_new_inv_ I2=$abc$44715$techmap\common.pb.$xor$crc8_func.v:31$5581_Y_new_inv_ I3=common.pb.spirx_crc[6] O=$abc$44715$techmap$techmap\common.pb.$procmux$14301.$and$/home/mb/fpga-toolchain/yosys/bin/../share/yosys/techmap.v:434$17895_Y[6]_new_
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:56"
.param LUT_INIT 0001001100000010
.gate SB_LUT4 I0=$false I1=common.pb.spirx_crc[5] I2=common.pb.spi.rx_data_r[5] I3=$abc$44715$new_n1666_ O=$abc$44715$techmap\common.pb.$xor$crc8_func.v:31$5581_Y_new_inv_
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:51"
.param LUT_INIT 0011110011000011
.gate SB_LUT4 I0=$false I1=common.pb.spirx_crc[4] I2=common.pb.spi.rx_data_r[4] I3=$abc$44715$auto$simplemap.cc:250:simplemap_eqne$19820[6]_new_inv_ O=$abc$44715$new_n1666_
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:51"
.param LUT_INIT 0011110011000011
.gate SB_LUT4 I0=$abc$44715$techmap$techmap\common.pb.$procmux$14301.$and$/home/mb/fpga-toolchain/yosys/bin/../share/yosys/techmap.v:434$17895_Y[7]_new_ I1=$abc$44715$auto$simplemap.cc:168:logic_reduce$18573_new_inv_ I2=common.pb.spirx_crc[7] I3=$abc$44715$new_n1640_ O=$abc$44715$techmap$techmap\common.pb.$procmux$14301.$reduce_or$/home/mb/fpga-toolchain/yosys/bin/../share/yosys/techmap.v:441$17904_Y
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:56"
.param LUT_INIT 1110111011101010
.gate SB_LUT4 I0=common.pb.spi.rx_irq_r I1=$abc$44715$auto$opt_reduce.cc:132:opt_mux$15900_new_inv_ I2=$abc$44715$techmap\common.pb.$xor$crc8_func.v:32$5586_Y_new_inv_ I3=common.pb.spirx_crc[7] O=$abc$44715$techmap$techmap\common.pb.$procmux$14301.$and$/home/mb/fpga-toolchain/yosys/bin/../share/yosys/techmap.v:434$17895_Y[7]_new_
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:56"
.param LUT_INIT 0001001100000010
.gate SB_LUT4 I0=common.pb.spirx_crc[5] I1=common.pb.spi.rx_data_r[5] I2=$abc$44715$auto$simplemap.cc:250:simplemap_eqne$19820[6]_new_inv_ I3=$abc$44715$auto$simplemap.cc:250:simplemap_eqne$19820[7]_new_inv_ O=$abc$44715$techmap\common.pb.$xor$crc8_func.v:32$5586_Y_new_inv_
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:56"
.param LUT_INIT 1001011001101001
.gate SB_LUT4 I0=common.pb.spirx_bytecount[0] I1=$abc$44715$new_n1671_ I2=$false I3=$abc$44715$new_n1680_ O=$abc$44715$techmap$techmap\common.pb.$procmux$14359.$reduce_or$/home/mb/fpga-toolchain/yosys/bin/../share/yosys/techmap.v:441$18295_Y
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:56"
.param LUT_INIT 0010001001110111
.gate SB_LUT4 I0=$abc$44715$new_n1677_ I1=$abc$44715$new_n1672_ I2=$abc$44715$auto$simplemap.cc:127:simplemap_reduce$35185[1]_new_inv_ I3=$abc$44715$auto$simplemap.cc:250:simplemap_eqne$35177[4]_new_inv_ O=$abc$44715$new_n1671_
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:56"
.param LUT_INIT 0001000000010001
.gate SB_LUT4 I0=$false I1=$false I2=$abc$44715$auto$simplemap.cc:309:simplemap_lut$20537_new_ I3=$abc$44715$new_n1673_ O=$abc$44715$new_n1672_
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:46"
.param LUT_INIT 0000000011110000
.gate SB_LUT4 I0=$false I1=common.pb.spi.rx_irq_r I2=$abc$44715$techmap\common.pb.$xor$parity_func.v:39$5527_Y_new_ I3=$abc$44715$new_n1674_ O=$abc$44715$new_n1673_
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:51"
.param LUT_INIT 0000110011000000
.gate SB_LUT4 I0=common.pb.spi.rx_data_r[7] I1=common.pb.spi.rx_data_r[5] I2=common.pb.spi.rx_data_r[6] I3=common.pb.spi.rx_data_r[4] O=$abc$44715$new_n1674_
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:56"
.param LUT_INIT 1001011001101001
.gate SB_LUT4 I0=common.pb.spi.rx_data_r[3] I1=common.pb.spi.rx_data_r[1] I2=common.pb.spi.rx_data_r[2] I3=common.pb.spi.rx_data_r[0] O=$abc$44715$techmap\common.pb.$xor$parity_func.v:39$5527_Y_new_
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:56"
.param LUT_INIT 1001011001101001
.gate SB_LUT4 I0=$false I1=common.pb.spirx_state[0] I2=common.pb.spirx_state[2] I3=common.pb.spirx_state[1] O=$abc$44715$auto$simplemap.cc:309:simplemap_lut$20537_new_
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:51"
.param LUT_INIT 0000000000001100
.gate SB_LUT4 I0=$false I1=$false I2=$abc$44715$techmap$techmap\common.pb.$procmux$14444.$and$/home/mb/fpga-toolchain/yosys/bin/../share/yosys/techmap.v:434$18189_Y[2]_new_ I3=common.pb.spi.rx_irq_r O=$abc$44715$new_n1677_
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:46"
.param LUT_INIT 0000000011110000
.gate SB_LUT4 I0=$false I1=$false I2=common.pb.spi.rx_irq_r I3=common.pb.tx_buf_wr O=$abc$44715$auto$simplemap.cc:127:simplemap_reduce$35185[1]_new_inv_
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:46"
.param LUT_INIT 0000000011110000
.gate SB_LUT4 I0=$false I1=common.pb.spirx_state[1] I2=common.pb.spirx_state[2] I3=common.pb.spirx_state[0] O=$abc$44715$auto$simplemap.cc:250:simplemap_eqne$35177[4]_new_inv_
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:51"
.param LUT_INIT 0000000000001100
.gate SB_LUT4 I0=$false I1=$abc$44715$new_n1681_ I2=$abc$44715$auto$simplemap.cc:127:simplemap_reduce$35185[1]_new_inv_ I3=$abc$44715$auto$simplemap.cc:250:simplemap_eqne$35177[4]_new_inv_ O=$abc$44715$new_n1680_
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:51"
.param LUT_INIT 0000001100110011
.gate SB_LUT4 I0=$false I1=$false I2=common.pb.spi.rx_irq_r I3=$abc$44715$techmap$techmap\common.pb.$procmux$14444.$and$/home/mb/fpga-toolchain/yosys/bin/../share/yosys/techmap.v:434$18189_Y[2]_new_ O=$abc$44715$new_n1681_
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:46"
.param LUT_INIT 1111000000000000
.gate SB_LUT4 I0=$false I1=$abc$44715$new_n1683_ I2=$abc$44715$new_n1686_ I3=common.pb.spirx_bytecount[1] O=$abc$44715$techmap$techmap\common.pb.$procmux$14359.$reduce_or$/home/mb/fpga-toolchain/yosys/bin/../share/yosys/techmap.v:441$18296_Y
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:51"
.param LUT_INIT 0011001100110000
.gate SB_LUT4 I0=$abc$44715$new_n1684_ I1=$abc$44715$new_n1672_ I2=$abc$44715$auto$simplemap.cc:250:simplemap_eqne$35177[4]_new_inv_ I3=common.pb.tx_buf_wr O=$abc$44715$new_n1683_
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:56"
.param LUT_INIT 0000000100010001
.gate SB_LUT4 I0=$abc$44715$auto$simplemap.cc:250:simplemap_eqne$35177[4]_new_inv_ I1=$abc$44715$techmap$techmap\common.pb.$procmux$14444.$and$/home/mb/fpga-toolchain/yosys/bin/../share/yosys/techmap.v:434$18189_Y[2]_new_ I2=common.pb.spirx_bytecount[1] I3=$abc$44715$new_n1685_ O=$abc$44715$new_n1684_
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:56"
.param LUT_INIT 0000111011101110
.gate SB_LUT4 I0=$false I1=$false I2=common.pb.spirx_bytecount[0] I3=common.pb.spi.rx_irq_r O=$abc$44715$new_n1685_
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:46"
.param LUT_INIT 1111000000000000
.gate SB_LUT4 I0=$abc$44715$new_n1685_ I1=$abc$44715$techmap$techmap\common.pb.$procmux$14444.$and$/home/mb/fpga-toolchain/yosys/bin/../share/yosys/techmap.v:434$18189_Y[2]_new_ I2=$abc$44715$auto$simplemap.cc:250:simplemap_eqne$35177[4]_new_inv_ I3=common.pb.tx_buf_wr O=$abc$44715$new_n1686_
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:56"
.param LUT_INIT 1000100010101000
.gate SB_LUT4 I0=common.pb.spirx_bytecount[2] I1=$abc$44715$new_n1671_ I2=$abc$44715$auto$wreduce.cc:455:run$15907[2] I3=$abc$44715$new_n1680_ O=$abc$44715$techmap$techmap\common.pb.$procmux$14359.$reduce_or$/home/mb/fpga-toolchain/yosys/bin/../share/yosys/techmap.v:441$18297_Y
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:56"
.param LUT_INIT 0010001011110010
.gate SB_LUT4 I0=common.pb.spirx_bytecount[3] I1=$abc$44715$new_n1671_ I2=$abc$44715$auto$wreduce.cc:455:run$15907[3] I3=$abc$44715$new_n1680_ O=$abc$44715$techmap$techmap\common.pb.$procmux$14359.$reduce_or$/home/mb/fpga-toolchain/yosys/bin/../share/yosys/techmap.v:441$18298_Y
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:56"
.param LUT_INIT 0010001011110010
.gate SB_LUT4 I0=common.pb.spirx_bytecount[4] I1=$abc$44715$new_n1671_ I2=$abc$44715$auto$wreduce.cc:455:run$15907[4] I3=$abc$44715$new_n1680_ O=$abc$44715$techmap$techmap\common.pb.$procmux$14359.$reduce_or$/home/mb/fpga-toolchain/yosys/bin/../share/yosys/techmap.v:441$18299_Y
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:56"
.param LUT_INIT 0010001011110010
.gate SB_LUT4 I0=common.pb.spirx_bytecount[5] I1=$abc$44715$new_n1671_ I2=$abc$44715$auto$wreduce.cc:455:run$15907[5] I3=$abc$44715$new_n1680_ O=$abc$44715$techmap$techmap\common.pb.$procmux$14359.$reduce_or$/home/mb/fpga-toolchain/yosys/bin/../share/yosys/techmap.v:441$18300_Y
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:56"
.param LUT_INIT 0010001011110010
.gate SB_LUT4 I0=common.pb.spirx_bytecount[6] I1=$abc$44715$new_n1671_ I2=$abc$44715$auto$wreduce.cc:455:run$15907[6] I3=$abc$44715$new_n1680_ O=$abc$44715$techmap$techmap\common.pb.$procmux$14359.$reduce_or$/home/mb/fpga-toolchain/yosys/bin/../share/yosys/techmap.v:441$18301_Y
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:56"
.param LUT_INIT 0010001011110010
.gate SB_LUT4 I0=$abc$44715$new_n1695_ I1=common.pb.spirx_len_valid I2=$abc$44715$new_n1694_ I3=common.pb.spirx_lencalc.length_valid O=$abc$44715$techmap$techmap\common.pb.$procmux$14395.$reduce_or$/home/mb/fpga-toolchain/yosys/bin/../share/yosys/techmap.v:441$17952_Y
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:56"
.param LUT_INIT 1110101011001000
.gate SB_LUT4 I0=$false I1=$false I2=$abc$44715$auto$simplemap.cc:168:logic_reduce$18573_new_inv_ I3=$abc$44715$new_n1640_ O=$abc$44715$new_n1694_
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:46"
.param LUT_INIT 0000000011110000
.gate SB_LUT4 I0=$false I1=$abc$44715$auto$simplemap.cc:250:simplemap_eqne$35177[4]_new_inv_ I2=common.pb.spirx_len_valid I3=common.pb.spirx_lencalc.error O=$abc$44715$new_n1695_
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:51"
.param LUT_INIT 1100000011001100
.gate SB_LUT4 I0=common.pb.spirx_len[0] I1=$abc$44715$new_n1697_ I2=common.pb.spirx_lencalc.length[0] I3=$abc$44715$new_n1699_ O=$abc$44715$techmap$techmap\common.pb.$procmux$14418.$reduce_or$/home/mb/fpga-toolchain/yosys/bin/../share/yosys/techmap.v:441$17897_Y
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:56"
.param LUT_INIT 1111001000100010
.gate SB_LUT4 I0=$false I1=$false I2=$abc$44715$new_n1698_ I3=$abc$44715$new_n1694_ O=$abc$44715$new_n1697_
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:46"
.param LUT_INIT 0000000000001111
.gate SB_LUT4 I0=$abc$44715$auto$simplemap.cc:250:simplemap_eqne$35177[4]_new_inv_ I1=common.pb.spirx_lencalc.length_valid I2=common.pb.spirx_lencalc.error I3=common.pb.spirx_len_valid O=$abc$44715$new_n1698_
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:56"
.param LUT_INIT 1010101010100010
.gate SB_LUT4 I0=common.pb.spirx_lencalc.length_valid I1=$abc$44715$auto$simplemap.cc:250:simplemap_eqne$35177[4]_new_inv_ I2=common.pb.spirx_lencalc.error I3=common.pb.spirx_len_valid O=$abc$44715$new_n1699_
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:56"
.param LUT_INIT 0000000000001000
.gate SB_LUT4 I0=common.pb.spirx_len[1] I1=$abc$44715$new_n1697_ I2=common.pb.spirx_lencalc.length[1] I3=$abc$44715$new_n1699_ O=$abc$44715$techmap$techmap\common.pb.$procmux$14418.$reduce_or$/home/mb/fpga-toolchain/yosys/bin/../share/yosys/techmap.v:441$17898_Y
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:56"
.param LUT_INIT 1111001000100010
.gate SB_LUT4 I0=common.pb.spirx_len[2] I1=$abc$44715$new_n1697_ I2=common.pb.spirx_lencalc.length[2] I3=$abc$44715$new_n1699_ O=$abc$44715$techmap$techmap\common.pb.$procmux$14418.$reduce_or$/home/mb/fpga-toolchain/yosys/bin/../share/yosys/techmap.v:441$17899_Y
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:56"
.param LUT_INIT 1111001000100010
.gate SB_LUT4 I0=common.pb.spirx_len[3] I1=$abc$44715$new_n1697_ I2=common.pb.spirx_lencalc.length[3] I3=$abc$44715$new_n1699_ O=$abc$44715$techmap$techmap\common.pb.$procmux$14418.$reduce_or$/home/mb/fpga-toolchain/yosys/bin/../share/yosys/techmap.v:441$17900_Y
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:56"
.param LUT_INIT 1111001000100010
.gate SB_LUT4 I0=common.pb.spirx_len[4] I1=$abc$44715$new_n1697_ I2=common.pb.spirx_lencalc.length[4] I3=$abc$44715$new_n1699_ O=$abc$44715$techmap$techmap\common.pb.$procmux$14418.$reduce_or$/home/mb/fpga-toolchain/yosys/bin/../share/yosys/techmap.v:441$17901_Y
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:56"
.param LUT_INIT 1111001000100010
.gate SB_LUT4 I0=common.pb.spirx_len[5] I1=$abc$44715$new_n1697_ I2=common.pb.spirx_lencalc.length[5] I3=$abc$44715$new_n1699_ O=$abc$44715$techmap$techmap\common.pb.$procmux$14418.$reduce_or$/home/mb/fpga-toolchain/yosys/bin/../share/yosys/techmap.v:441$17902_Y
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:56"
.param LUT_INIT 1111001000100010
.gate SB_LUT4 I0=common.pb.spirx_len[6] I1=$abc$44715$new_n1697_ I2=common.pb.spirx_lencalc.length[6] I3=$abc$44715$new_n1699_ O=$abc$44715$techmap$techmap\common.pb.$procmux$14418.$reduce_or$/home/mb/fpga-toolchain/yosys/bin/../share/yosys/techmap.v:441$17903_Y
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:56"
.param LUT_INIT 1111001000100010
.gate SB_LUT4 I0=common.pb.spirx_len[7] I1=$abc$44715$new_n1697_ I2=common.pb.spirx_lencalc.length[7] I3=$abc$44715$new_n1699_ O=$abc$44715$techmap$techmap\common.pb.$procmux$14418.$reduce_or$/home/mb/fpga-toolchain/yosys/bin/../share/yosys/techmap.v:441$17904_Y
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:56"
.param LUT_INIT 1111001000100010
.gate SB_LUT4 I0=$false I1=$abc$44715$auto$dff2dffe.cc:158:make_patterns_logic$26894_new_inv_ I2=$abc$44715$auto$simplemap.cc:168:logic_reduce$16646_new_inv_ I3=$abc$44715$new_n1732_ O=$abc$44715$auto$dff2dffe.cc:175:make_patterns_logic$26906
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:51"
.param LUT_INIT 0000001100110011
.gate SB_LUT4 I0=$false I1=$false I2=common.pb.n_reset I3=$abc$44715$new_n1709_ O=$abc$44715$auto$dff2dffe.cc:158:make_patterns_logic$26894_new_inv_
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:46"
.param LUT_INIT 1111000000000000
.gate SB_LUT4 I0=$false I1=$false I2=common.led_blink.led I3=$abc$44715$auto$simplemap.cc:168:logic_reduce$16686_new_inv_ O=$abc$44715$new_n1709_
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:46"
.param LUT_INIT 0000000011110000
.gate SB_LUT4 I0=$abc$44715$auto$simplemap.cc:168:logic_reduce$16669[2]_new_inv_ I1=$abc$44715$auto$simplemap.cc:168:logic_reduce$16669[3]_new_inv_ I2=$abc$44715$auto$simplemap.cc:168:logic_reduce$16678[0]_new_inv_ I3=$abc$44715$auto$simplemap.cc:168:logic_reduce$16683[1]_new_inv_ O=$abc$44715$auto$simplemap.cc:168:logic_reduce$16686_new_inv_
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:56"
.param LUT_INIT 1000000000000000
.gate SB_LUT4 I0=$abc$44715$auto$simplemap.cc:168:logic_reduce$16669[6]_new_inv_ I1=$abc$44715$auto$simplemap.cc:168:logic_reduce$16669[7]_new_inv_ I2=$abc$44715$auto$simplemap.cc:168:logic_reduce$16669[4]_new_inv_ I3=$abc$44715$auto$simplemap.cc:168:logic_reduce$16669[5]_new_inv_ O=$abc$44715$auto$simplemap.cc:168:logic_reduce$16683[1]_new_inv_
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:56"
.param LUT_INIT 1000000000000000
.gate SB_LUT4 I0=common.led_blink.led_on_count[23] I1=common.led_blink.led_on_count[22] I2=common.led_blink.led_on_count[21] I3=common.led_blink.led_on_count[20] O=$abc$44715$auto$simplemap.cc:168:logic_reduce$16669[5]_new_inv_
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:56"
.param LUT_INIT 0000000000000001
.gate SB_LUT4 I0=common.led_blink.led_on_count[19] I1=common.led_blink.led_on_count[18] I2=common.led_blink.led_on_count[17] I3=common.led_blink.led_on_count[16] O=$abc$44715$auto$simplemap.cc:168:logic_reduce$16669[4]_new_inv_
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:56"
.param LUT_INIT 0000000000000001
.gate SB_LUT4 I0=common.led_blink.led_on_count[31] I1=common.led_blink.led_on_count[30] I2=common.led_blink.led_on_count[29] I3=common.led_blink.led_on_count[28] O=$abc$44715$auto$simplemap.cc:168:logic_reduce$16669[7]_new_inv_
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:56"
.param LUT_INIT 0000000000000001
.gate SB_LUT4 I0=common.led_blink.led_on_count[27] I1=common.led_blink.led_on_count[26] I2=common.led_blink.led_on_count[25] I3=common.led_blink.led_on_count[24] O=$abc$44715$auto$simplemap.cc:168:logic_reduce$16669[6]_new_inv_
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:56"
.param LUT_INIT 0000000000000001
.gate SB_LUT4 I0=$false I1=$false I2=$abc$44715$auto$simplemap.cc:168:logic_reduce$16669[0]_new_inv_ I3=$abc$44715$auto$simplemap.cc:168:logic_reduce$16669[1]_new_inv_ O=$abc$44715$auto$simplemap.cc:168:logic_reduce$16678[0]_new_inv_
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:46"
.param LUT_INIT 1111000000000000
.gate SB_LUT4 I0=common.led_blink.led_on_count[7] I1=common.led_blink.led_on_count[6] I2=common.led_blink.led_on_count[5] I3=common.led_blink.led_on_count[4] O=$abc$44715$auto$simplemap.cc:168:logic_reduce$16669[1]_new_inv_
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:56"
.param LUT_INIT 0000000000000001
.gate SB_LUT4 I0=common.led_blink.led_on_count[3] I1=common.led_blink.led_on_count[2] I2=common.led_blink.led_on_count[1] I3=common.led_blink.led_on_count[0] O=$abc$44715$auto$simplemap.cc:168:logic_reduce$16669[0]_new_inv_
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:56"
.param LUT_INIT 0000000000000001
.gate SB_LUT4 I0=common.led_blink.led_on_count[15] I1=common.led_blink.led_on_count[14] I2=common.led_blink.led_on_count[13] I3=common.led_blink.led_on_count[12] O=$abc$44715$auto$simplemap.cc:168:logic_reduce$16669[3]_new_inv_
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:56"
.param LUT_INIT 0000000000000001
.gate SB_LUT4 I0=common.led_blink.led_on_count[11] I1=common.led_blink.led_on_count[10] I2=common.led_blink.led_on_count[9] I3=common.led_blink.led_on_count[8] O=$abc$44715$auto$simplemap.cc:168:logic_reduce$16669[2]_new_inv_
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:56"
.param LUT_INIT 0000000000000001
.gate SB_LUT4 I0=$false I1=$false I2=$abc$44715$auto$simplemap.cc:168:logic_reduce$16643[0]_new_inv_ I3=$abc$44715$auto$simplemap.cc:168:logic_reduce$16643[1]_new_inv_ O=$abc$44715$auto$simplemap.cc:168:logic_reduce$16646_new_inv_
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:46"
.param LUT_INIT 1111000000000000
.gate SB_LUT4 I0=$abc$44715$auto$simplemap.cc:168:logic_reduce$16629[6]_new_inv_ I1=$abc$44715$auto$simplemap.cc:168:logic_reduce$16629[7]_new_inv_ I2=$abc$44715$auto$simplemap.cc:168:logic_reduce$16629[4]_new_inv_ I3=$abc$44715$auto$simplemap.cc:168:logic_reduce$16629[5]_new_inv_ O=$abc$44715$auto$simplemap.cc:168:logic_reduce$16643[1]_new_inv_
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:56"
.param LUT_INIT 1000000000000000
.gate SB_LUT4 I0=common.led_blink.led_off_count[23] I1=common.led_blink.led_off_count[22] I2=common.led_blink.led_off_count[21] I3=common.led_blink.led_off_count[20] O=$abc$44715$auto$simplemap.cc:168:logic_reduce$16629[5]_new_inv_
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:56"
.param LUT_INIT 0000000000000001
.gate SB_LUT4 I0=common.led_blink.led_off_count[19] I1=common.led_blink.led_off_count[18] I2=common.led_blink.led_off_count[17] I3=common.led_blink.led_off_count[16] O=$abc$44715$auto$simplemap.cc:168:logic_reduce$16629[4]_new_inv_
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:56"
.param LUT_INIT 0000000000000001
.gate SB_LUT4 I0=common.led_blink.led_off_count[31] I1=common.led_blink.led_off_count[30] I2=common.led_blink.led_off_count[29] I3=common.led_blink.led_off_count[28] O=$abc$44715$auto$simplemap.cc:168:logic_reduce$16629[7]_new_inv_
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:56"
.param LUT_INIT 0000000000000001
.gate SB_LUT4 I0=common.led_blink.led_off_count[27] I1=common.led_blink.led_off_count[26] I2=common.led_blink.led_off_count[25] I3=common.led_blink.led_off_count[24] O=$abc$44715$auto$simplemap.cc:168:logic_reduce$16629[6]_new_inv_
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:56"
.param LUT_INIT 0000000000000001
.gate SB_LUT4 I0=$abc$44715$auto$simplemap.cc:168:logic_reduce$16629[2]_new_inv_ I1=$abc$44715$auto$simplemap.cc:168:logic_reduce$16629[3]_new_inv_ I2=$abc$44715$auto$simplemap.cc:168:logic_reduce$16629[0]_new_inv_ I3=$abc$44715$auto$simplemap.cc:168:logic_reduce$16629[1]_new_inv_ O=$abc$44715$auto$simplemap.cc:168:logic_reduce$16643[0]_new_inv_
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:56"
.param LUT_INIT 1000000000000000
.gate SB_LUT4 I0=common.led_blink.led_off_count[7] I1=common.led_blink.led_off_count[6] I2=common.led_blink.led_off_count[5] I3=common.led_blink.led_off_count[4] O=$abc$44715$auto$simplemap.cc:168:logic_reduce$16629[1]_new_inv_
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:56"
.param LUT_INIT 0000000000000001
.gate SB_LUT4 I0=common.led_blink.led_off_count[3] I1=common.led_blink.led_off_count[2] I2=common.led_blink.led_off_count[1] I3=common.led_blink.led_off_count[0] O=$abc$44715$auto$simplemap.cc:168:logic_reduce$16629[0]_new_inv_
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:56"
.param LUT_INIT 0000000000000001
.gate SB_LUT4 I0=common.led_blink.led_off_count[15] I1=common.led_blink.led_off_count[14] I2=common.led_blink.led_off_count[13] I3=common.led_blink.led_off_count[12] O=$abc$44715$auto$simplemap.cc:168:logic_reduce$16629[3]_new_inv_
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:56"
.param LUT_INIT 0000000000000001
.gate SB_LUT4 I0=common.led_blink.led_off_count[11] I1=common.led_blink.led_off_count[10] I2=common.led_blink.led_off_count[9] I3=common.led_blink.led_off_count[8] O=$abc$44715$auto$simplemap.cc:168:logic_reduce$16629[2]_new_inv_
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:56"
.param LUT_INIT 0000000000000001
.gate SB_LUT4 I0=$false I1=$false I2=common.pb.n_reset I3=common.led_blink.led O=$abc$44715$new_n1732_
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:46"
.param LUT_INIT 0000000011110000
.gate SB_LUT4 I0=$abc$44715$auto$dff2dffe.cc:158:make_patterns_logic$26894_new_inv_ I1=$abc$44715$new_n1732_ I2=common.led_blink.led_off_count[0] I3=$abc$44715$auto$simplemap.cc:168:logic_reduce$16646_new_inv_ O=$abc$44715$auto$dff2dffe.cc:175:make_patterns_logic$26948
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:56"
.param LUT_INIT 0001000100010101
.gate SB_LUT4 I0=common.pb.n_reset I1=$abc$44715$new_n1709_ I2=common.led_blink.led_on_count[0] I3=$abc$44715$new_n1735_ O=$abc$44715$auto$dff2dffe.cc:175:make_patterns_logic$27890
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:56"
.param LUT_INIT 0111111101011101
.gate SB_LUT4 I0=$abc$44715$auto$simplemap.cc:168:logic_reduce$16646_new_inv_ I1=common.led_blink.led I2=common.pb.uart.tx_mod.tx_active I3=common.pb.uart.rx_mod.rx_active O=$abc$44715$new_n1735_
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:56"
.param LUT_INIT 0010001000100000
.gate SB_LUT4 I0=$false I1=$false I2=common.pb.n_reset I3=$abc$44715$techmap\common.led_blink.$procmux$9288_Y O=$abc$44715$auto$dff2dffe.cc:175:make_patterns_logic$27832
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:46"
.param LUT_INIT 1111111100001111
.gate SB_LUT4 I0=$false I1=$false I2=$abc$44715$new_n1735_ I3=$abc$44715$new_n1709_ O=$abc$44715$techmap\common.led_blink.$procmux$9288_Y
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:46"
.param LUT_INIT 1111111111110000
.gate SB_LUT4 I0=common.pb.uart.rx_mod.rx_irq I1=$abc$44715$auto$simplemap.cc:250:simplemap_eqne$29225[1]_new_ I2=$abc$44715$auto$dff2dffe.cc:158:make_patterns_logic$29217 I3=PIN_17 O=$abc$44715$auto$dff2dffe.cc:175:make_patterns_logic$29258
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:56"
.param LUT_INIT 0000000010000000
.gate SB_LUT4 I0=$false I1=$abc$44715$auto$simplemap.cc:127:simplemap_reduce$20018[2]_new_inv_ I2=$abc$44715$new_n1744_ I3=$abc$44715$new_n1740_ O=$abc$44715$auto$simplemap.cc:250:simplemap_eqne$29225[1]_new_
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:51"
.param LUT_INIT 1100000000000000
.gate SB_LUT4 I0=$abc$44715$auto$simplemap.cc:250:simplemap_eqne$20007[2]_new_inv_ I1=$abc$44715$auto$simplemap.cc:127:simplemap_reduce$20018[3]_new_inv_ I2=common.pb.rx_buf_rd_addr[1] I3=common.pb.rx_buf_wr_addr_next[1] O=$abc$44715$new_n1740_
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:56"
.param LUT_INIT 1000000000001000
.gate SB_LUT4 I0=$false I1=$false I2=common.pb.rx_buf_wr_addr[0] I3=common.pb.rx_buf_wr_addr[1] O=common.pb.rx_buf_wr_addr_next[1]
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:46"
.param LUT_INIT 0000111111110000
.gate SB_LUT4 I0=$false I1=$false I2=common.pb.rx_buf_rd_addr[2] I3=common.pb.rx_buf_wr_addr_next[2] O=$abc$44715$auto$simplemap.cc:250:simplemap_eqne$20007[2]_new_inv_
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:46"
.param LUT_INIT 1111000000001111
.gate SB_LUT4 I0=common.pb.rx_buf_rd_addr[7] I1=common.pb.rx_buf_wr_addr_next[7] I2=common.pb.rx_buf_rd_addr[6] I3=common.pb.rx_buf_wr_addr_next[6] O=$abc$44715$auto$simplemap.cc:127:simplemap_reduce$20018[3]_new_inv_
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:56"
.param LUT_INIT 1001000000001001
.gate SB_LUT4 I0=common.pb.rx_buf_rd_addr[3] I1=common.pb.rx_buf_wr_addr_next[3] I2=common.pb.rx_buf_wr_addr_next[0] I3=common.pb.rx_buf_rd_addr[0] O=$abc$44715$new_n1744_
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:56"
.param LUT_INIT 1001000000001001
.gate SB_LUT4 I0=common.pb.rx_buf_rd_addr[5] I1=common.pb.rx_buf_wr_addr_next[5] I2=common.pb.rx_buf_rd_addr[4] I3=common.pb.rx_buf_wr_addr_next[4] O=$abc$44715$auto$simplemap.cc:127:simplemap_reduce$20018[2]_new_inv_
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:56"
.param LUT_INIT 1001000000001001
.gate SB_LUT4 I0=$false I1=$false I2=common.pb.uart.rx_mod.rx_parity_ok I3=common.pb.uart.rx_mod.rx_frame_error O=PIN_17
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:46"
.param LUT_INIT 1111111100001111
.gate SB_LUT4 I0=$false I1=common.pb.uart.rx_mod.rx_irq I2=$abc$44715$auto$dff2dffe.cc:158:make_patterns_logic$29217 I3=$abc$44715$new_n1748_ O=$abc$44715$auto$dff2dffe.cc:175:make_patterns_logic$29291
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:51"
.param LUT_INIT 1111111100111111
.gate SB_LUT4 I0=$false I1=$false I2=PIN_17 I3=$abc$44715$auto$simplemap.cc:250:simplemap_eqne$29225[1]_new_ O=$abc$44715$new_n1748_
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:46"
.param LUT_INIT 0000000000001111
.gate SB_LUT4 I0=$false I1=common.pb.uart.rx_mod.rx_irq I2=$abc$44715$auto$dff2dffe.cc:158:make_patterns_logic$29217 I3=$abc$44715$new_n1748_ O=$abc$44715$auto$dff2dffe.cc:175:make_patterns_logic$29336
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:51"
.param LUT_INIT 1100000000000000
.gate SB_LUT4 I0=$false I1=$abc$44715$auto$dff2dffe.cc:158:make_patterns_logic$29217 I2=common.pb.rx_buf_wr I3=common.pb.uart.rx_mod.rx_irq O=$abc$44715$auto$dff2dffe.cc:175:make_patterns_logic$29748
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:51"
.param LUT_INIT 0011001111110011
.gate SB_LUT4 I0=$false I1=$false I2=$abc$44715$auto$dff2dffe.cc:158:make_patterns_logic$29217 I3=$abc$44715$techmap\common.pb.$procmux$14662_Y O=$abc$44715$auto$dff2dffe.cc:175:make_patterns_logic$29962
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:46"
.param LUT_INIT 1111111100001111
.gate SB_LUT4 I0=$false I1=$abc$44715$auto$dff2dffe.cc:158:make_patterns_logic$29217 I2=common.pb.tx_buf_rd_addr[0] I3=$abc$44715$techmap\common.pb.$procmux$14662_Y O=$abc$44715$auto$dff2dffe.cc:175:make_patterns_logic$30348
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:51"
.param LUT_INIT 1111001100110011
.gate SB_LUT4 I0=$false I1=$abc$44715$auto$simplemap.cc:250:simplemap_eqne$30609[2]_new_inv_ I2=$abc$44715$auto$dff2dffe.cc:158:make_patterns_logic$29217 I3=$abc$44715$auto$simplemap.cc:250:simplemap_eqne$30621[1]_new_ O=$abc$44715$auto$dff2dffe.cc:175:make_patterns_logic$30676
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:51"
.param LUT_INIT 0000000011000000
.gate SB_LUT4 I0=$false I1=common.pb.spirx_state[2] I2=common.pb.spirx_state[1] I3=common.pb.spirx_state[0] O=$abc$44715$auto$simplemap.cc:250:simplemap_eqne$30609[2]_new_inv_
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:51"
.param LUT_INIT 0000000011000000
.gate SB_LUT4 I0=$false I1=$false I2=$abc$44715$auto$simplemap.cc:250:simplemap_eqne$19803_new_inv_ I3=$abc$44715$auto$dff2dffe.cc:175:make_patterns_logic$30676 O=$abc$44715$auto$dff2dffe.cc:175:make_patterns_logic$30642
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:46"
.param LUT_INIT 1111000000000000
.gate SB_LUT4 I0=$false I1=$abc$44715$auto$simplemap.cc:250:simplemap_eqne$32268[3]_new_inv_ I2=$abc$44715$auto$dff2dffe.cc:158:make_patterns_logic$29217 I3=$abc$44715$new_n1765_ O=$abc$44715$auto$dff2dffe.cc:175:make_patterns_logic$32301
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:51"
.param LUT_INIT 1100000000000000
.gate SB_LUT4 I0=$false I1=$false I2=common.pb.spi.rx_irq_r I3=$abc$44715$techmap\common.pb.$eq$profibus_phy_mod.v:721$5638_Y_new_ O=$abc$44715$new_n1765_
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:46"
.param LUT_INIT 0000000011110000
.gate SB_LUT4 I0=$abc$44715$new_n1770_ I1=$abc$44715$auto$simplemap.cc:127:simplemap_reduce$19832[3]_new_inv_ I2=$abc$44715$new_n1768_ I3=$abc$44715$auto$simplemap.cc:127:simplemap_reduce$19832[0]_new_inv_ O=$abc$44715$techmap\common.pb.$eq$profibus_phy_mod.v:721$5638_Y_new_
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:56"
.param LUT_INIT 1000000000000000
.gate SB_LUT4 I0=common.pb.spirx_crc[1] I1=common.pb.spi.rx_data_r[1] I2=common.pb.spirx_crc[0] I3=common.pb.spi.rx_data_r[0] O=$abc$44715$auto$simplemap.cc:127:simplemap_reduce$19832[0]_new_inv_
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:56"
.param LUT_INIT 1001000000001001
.gate SB_LUT4 I0=common.pb.spi.rx_data_r[3] I1=common.pb.spirx_crc[3] I2=common.pb.spirx_crc[4] I3=common.pb.spi.rx_data_r[4] O=$abc$44715$new_n1768_
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:56"
.param LUT_INIT 1001000000001001
.gate SB_LUT4 I0=common.pb.spirx_crc[7] I1=common.pb.spi.rx_data_r[7] I2=common.pb.spirx_crc[6] I3=common.pb.spi.rx_data_r[6] O=$abc$44715$auto$simplemap.cc:127:simplemap_reduce$19832[3]_new_inv_
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:56"
.param LUT_INIT 1001000000001001
.gate SB_LUT4 I0=common.pb.spirx_crc[5] I1=common.pb.spi.rx_data_r[5] I2=common.pb.spirx_crc[2] I3=common.pb.spi.rx_data_r[2] O=$abc$44715$new_n1770_
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:56"
.param LUT_INIT 1001000000001001
.gate SB_LUT4 I0=$false I1=common.pb.spirx_state[2] I2=common.pb.spirx_state[0] I3=common.pb.spirx_state[1] O=$abc$44715$auto$simplemap.cc:250:simplemap_eqne$32268[3]_new_inv_
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:51"
.param LUT_INIT 0000000011000000
.gate SB_LUT4 I0=$abc$44715$auto$dff2dffe.cc:158:make_patterns_logic$29217 I1=common.pb.spirx_state[1] I2=common.pb.spirx_state[0] I3=common.pb.spirx_state[2] O=$abc$44715$auto$dff2dffe.cc:175:make_patterns_logic$32364
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:56"
.param LUT_INIT 0000001010000010
.gate SB_LUT4 I0=$abc$44715$auto$dff2dffe.cc:158:make_patterns_logic$29217 I1=common.pb.spirx_state[2] I2=common.pb.spirx_state[1] I3=common.pb.spirx_state[0] O=$abc$44715$auto$dff2dffe.cc:175:make_patterns_logic$32516
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:56"
.param LUT_INIT 0000001000101000
.gate SB_LUT4 I0=$false I1=$false I2=$abc$44715$auto$dff2dffe.cc:158:make_patterns_logic$29217 I3=$abc$44715$auto$opt_reduce.cc:132:opt_mux$15904_new_inv_ O=$abc$44715$auto$dff2dffe.cc:175:make_patterns_logic$32104
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:46"
.param LUT_INIT 0000000011110000
.gate SB_LUT4 I0=$false I1=$false I2=$abc$44715$auto$simplemap.cc:250:simplemap_eqne$35177[4]_new_inv_ I3=$abc$44715$auto$simplemap.cc:168:logic_reduce$18573_new_inv_ O=$abc$44715$auto$opt_reduce.cc:132:opt_mux$15904_new_inv_
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:46"
.param LUT_INIT 0000000000001111
.gate SB_LUT4 I0=$abc$44715$auto$simplemap.cc:250:simplemap_eqne$19803_new_inv_ I1=$abc$44715$auto$simplemap.cc:127:simplemap_reduce$18865[0]_new_inv_ I2=$abc$44715$new_n1777_ I3=$abc$44715$auto$dff2dffe.cc:158:make_patterns_logic$29217 O=$abc$44715$auto$dff2dffe.cc:175:make_patterns_logic$32865
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:56"
.param LUT_INIT 1000000000000000
.gate SB_LUT4 I0=$false I1=$false I2=$abc$44715$auto$simplemap.cc:250:simplemap_eqne$30609[2]_new_inv_ I3=$abc$44715$auto$simplemap.cc:127:simplemap_reduce$17870[1]_new_inv_ O=$abc$44715$new_n1777_
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:46"
.param LUT_INIT 1111000000000000
.gate SB_LUT4 I0=$false I1=common.pb.spirx_ctrl[0] I2=common.pb.spirx_ctrl[1] I3=$abc$44715$auto$simplemap.cc:127:simplemap_reduce$18772[1]_new_inv_ O=$abc$44715$auto$simplemap.cc:127:simplemap_reduce$18865[0]_new_inv_
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:51"
.param LUT_INIT 1100000000000000
.gate SB_LUT4 I0=$abc$44715$auto$simplemap.cc:250:simplemap_eqne$35177[4]_new_inv_ I1=$abc$44715$auto$simplemap.cc:127:simplemap_reduce$35185[1]_new_inv_ I2=$abc$44715$auto$dff2dffe.cc:158:make_patterns_logic$29217 I3=$abc$44715$auto$simplemap.cc:250:simplemap_eqne$35177[1]_new_ O=$abc$44715$auto$dff2dffe.cc:175:make_patterns_logic$35227
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:56"
.param LUT_INIT 1000000000000000
.gate SB_LUT4 I0=$false I1=$abc$44715$new_n1785_ I2=$abc$44715$new_n1784_ I3=$abc$44715$new_n1781_ O=$abc$44715$auto$simplemap.cc:250:simplemap_eqne$35177[1]_new_
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:51"
.param LUT_INIT 1100000000000000
.gate SB_LUT4 I0=$abc$44715$new_n1783_ I1=$abc$44715$auto$simplemap.cc:250:simplemap_eqne$19927[1]_new_inv_ I2=common.pb.tx_buf_rd_addr[6] I3=common.pb.tx_buf_wr_addr_next[6] O=$abc$44715$new_n1781_
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:56"
.param LUT_INIT 1000000000001000
.gate SB_LUT4 I0=$false I1=common.pb.tx_buf_rd_addr[1] I2=common.pb.tx_buf_wr_addr[1] I3=common.pb.tx_buf_wr_addr[0] O=$abc$44715$auto$simplemap.cc:250:simplemap_eqne$19927[1]_new_inv_
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:51"
.param LUT_INIT 0011110011000011
.gate SB_LUT4 I0=common.pb.tx_buf_rd_addr[5] I1=common.pb.tx_buf_wr_addr_next[5] I2=common.pb.tx_buf_rd_addr[3] I3=common.pb.tx_buf_wr_addr_next[3] O=$abc$44715$new_n1783_
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:56"
.param LUT_INIT 1001000000001001
.gate SB_LUT4 I0=common.pb.tx_buf_rd_addr[2] I1=common.pb.tx_buf_wr_addr_next[2] I2=common.pb.tx_buf_wr_addr_next[0] I3=common.pb.tx_buf_rd_addr[0] O=$abc$44715$new_n1784_
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:56"
.param LUT_INIT 1001000000001001
.gate SB_LUT4 I0=common.pb.tx_buf_rd_addr[7] I1=common.pb.tx_buf_wr_addr_next[7] I2=common.pb.tx_buf_rd_addr[4] I3=common.pb.tx_buf_wr_addr_next[4] O=$abc$44715$new_n1785_
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:56"
.param LUT_INIT 1001000000001001
.gate SB_LUT4 I0=$false I1=$abc$44715$auto$dff2dffe.cc:158:make_patterns_logic$29217 I2=$abc$44715$auto$simplemap.cc:127:simplemap_reduce$17870[0]_new_inv_ I3=$abc$44715$new_n1777_ O=$abc$44715$auto$dff2dffe.cc:175:make_patterns_logic$35298
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:51"
.param LUT_INIT 1111001100110011
.gate SB_LUT4 I0=$false I1=common.pb.spirx_ctrl[0] I2=common.pb.spirx_ctrl[1] I3=$abc$44715$auto$simplemap.cc:127:simplemap_reduce$17865[1]_new_inv_ O=$abc$44715$auto$simplemap.cc:127:simplemap_reduce$17870[0]_new_inv_
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:51"
.param LUT_INIT 1100000000000000
.gate SB_LUT4 I0=$abc$44715$auto$dff2dffe.cc:158:make_patterns_logic$29217 I1=$abc$44715$new_n1777_ I2=$abc$44715$auto$simplemap.cc:127:simplemap_reduce$18777[0]_new_inv_ I3=$abc$44715$auto$simplemap.cc:250:simplemap_eqne$19803_new_inv_ O=$abc$44715$auto$dff2dffe.cc:175:make_patterns_logic$32343
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:56"
.param LUT_INIT 1101010101010101
.gate SB_LUT4 I0=$false I1=$false I2=$abc$44715$auto$dff2dffe.cc:158:make_patterns_logic$29217 I3=$abc$44715$new_n1790_ O=$abc$44715$auto$dff2dffe.cc:175:make_patterns_logic$35460
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:46"
.param LUT_INIT 1111111100001111
.gate SB_LUT4 I0=$abc$44715$auto$simplemap.cc:168:logic_reduce$19575 I1=common.pb.spi.rx_irq_r I2=$abc$44715$auto$simplemap.cc:250:simplemap_eqne$35427[1]_new_ I3=$abc$44715$auto$simplemap.cc:250:simplemap_eqne$37070[3]_new_inv_ O=$abc$44715$new_n1790_
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:56"
.param LUT_INIT 1000000000000000
.gate SB_LUT4 I0=$false I1=$false I2=$abc$44715$auto$simplemap.cc:127:simplemap_reduce$19217[1]_new_inv_ I3=common.pb.spitx_bytecount[3] O=$abc$44715$auto$simplemap.cc:250:simplemap_eqne$37118[1]_new_
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:46"
.param LUT_INIT 0000000011110000
.gate SB_LUT4 I0=$false I1=$abc$44715$auto$simplemap.cc:250:simplemap_eqne$37118[1]_new_ I2=$abc$44715$auto$simplemap.cc:127:simplemap_reduce$19284[0]_new_inv_ I3=common.pb.spitx_bytecount[2] O=$abc$44715$auto$simplemap.cc:250:simplemap_eqne$37070[3]_new_inv_
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:51"
.param LUT_INIT 0000110011001100
.gate SB_LUT4 I0=$false I1=$false I2=common.pb.spitx_data_running I3=$abc$44715$auto$simplemap.cc:250:simplemap_eqne$19803_new_inv_ O=$abc$44715$auto$simplemap.cc:250:simplemap_eqne$35427[1]_new_
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:46"
.param LUT_INIT 0000000000001111
.gate SB_LUT4 I0=$abc$44715$auto$dff2dffe.cc:158:make_patterns_logic$29217 I1=$abc$44715$auto$simplemap.cc:127:simplemap_reduce$35862[2]_new_inv_ I2=$abc$44715$auto$simplemap.cc:250:simplemap_eqne$35427[1]_new_ I3=common.pb.spi.rx_irq_r O=$abc$44715$auto$dff2dffe.cc:175:make_patterns_logic$35804
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:56"
.param LUT_INIT 0111011101010111
.gate SB_LUT4 I0=common.pb.spitx_data_running I1=$abc$44715$auto$simplemap.cc:250:simplemap_eqne$19803_new_inv_ I2=common.pb.spitx_ctrl_running I3=$abc$44715$techmap\common.pb.$eq$profibus_phy_mod.v:990$6250_Y_new_ O=$abc$44715$auto$simplemap.cc:127:simplemap_reduce$35862[2]_new_inv_
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:56"
.param LUT_INIT 1010101010101110
.gate SB_LUT4 I0=$abc$44715$auto$simplemap.cc:127:simplemap_reduce$19527[0]_new_inv_ I1=$abc$44715$new_n1800_ I2=$abc$44715$new_n1799_ I3=$abc$44715$new_n1798_ O=$abc$44715$techmap\common.pb.$eq$profibus_phy_mod.v:990$6250_Y_new_
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:56"
.param LUT_INIT 1000000000000000
.gate SB_LUT4 I0=common.pb.rx_buf_wr_addr[6] I1=common.pb.rx_buf_rd_addr[6] I2=common.pb.rx_buf_wr_addr[2] I3=common.pb.rx_buf_rd_addr[2] O=$abc$44715$new_n1798_
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:56"
.param LUT_INIT 1001000000001001
.gate SB_LUT4 I0=common.pb.rx_buf_wr_addr[7] I1=common.pb.rx_buf_rd_addr[7] I2=common.pb.rx_buf_wr_addr[5] I3=common.pb.rx_buf_rd_addr[5] O=$abc$44715$new_n1799_
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:56"
.param LUT_INIT 1001000000001001
.gate SB_LUT4 I0=common.pb.rx_buf_wr_addr[4] I1=common.pb.rx_buf_rd_addr[4] I2=common.pb.rx_buf_wr_addr[3] I3=common.pb.rx_buf_rd_addr[3] O=$abc$44715$new_n1800_
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:56"
.param LUT_INIT 1001000000001001
.gate SB_LUT4 I0=common.pb.rx_buf_rd_addr[1] I1=common.pb.rx_buf_wr_addr[1] I2=common.pb.rx_buf_wr_addr[0] I3=common.pb.rx_buf_rd_addr[0] O=$abc$44715$auto$simplemap.cc:127:simplemap_reduce$19527[0]_new_inv_
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:56"
.param LUT_INIT 1001000000001001
.gate SB_LUT4 I0=$abc$44715$auto$dff2dffe.cc:158:make_patterns_logic$29217 I1=$abc$44715$auto$simplemap.cc:250:simplemap_eqne$35427[1]_new_ I2=$abc$44715$auto$simplemap.cc:127:simplemap_reduce$35862[2]_new_inv_ I3=common.pb.spi.rx_irq_r O=$abc$44715$auto$dff2dffe.cc:175:make_patterns_logic$35776
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:56"
.param LUT_INIT 0111011101010111
.gate SB_LUT4 I0=$false I1=$false I2=$abc$44715$new_n1812_ I3=$abc$44715$auto$dff2dffe.cc:175:make_patterns_logic$37697 O=$abc$44715$auto$dff2dffe.cc:175:make_patterns_logic$35906
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:46"
.param LUT_INIT 0000000000001111
.gate SB_LUT4 I0=$false I1=$false I2=$abc$44715$new_n1807_ I3=$abc$44715$auto$simplemap.cc:250:simplemap_eqne$35937[3]_new_ O=$abc$44715$auto$dff2dffe.cc:175:make_patterns_logic$37697
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:46"
.param LUT_INIT 1111000000000000
.gate SB_LUT4 I0=$false I1=$false I2=$abc$44715$new_n1806_ I3=$abc$44715$techmap\common.pb.$eq$profibus_phy_mod.v:990$6250_Y_new_ O=$abc$44715$auto$simplemap.cc:250:simplemap_eqne$35937[3]_new_
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:46"
.param LUT_INIT 0000000011110000
.gate SB_LUT4 I0=common.pb.spitx_tail I1=common.pb.rx_buf_rd_data[8] I2=$abc$44715$auto$alumacc.cc:491:replace_alu$16067[7] I3=$abc$44715$auto$rtlil.cc:1835:ReduceAnd$16071_new_ O=$abc$44715$new_n1806_
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:56"
.param LUT_INIT 0001000101010001
.gate SB_LUT4 I0=common.pb.spi.rx_irq_r I1=$abc$44715$new_n1811_ I2=$abc$44715$auto$simplemap.cc:250:simplemap_eqne$35852[3]_new_ I3=$abc$44715$auto$simplemap.cc:127:simplemap_reduce$35862[2]_new_inv_ O=$abc$44715$new_n1807_
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:56"
.param LUT_INIT 1000000000000000
.gate SB_LUT4 I0=$false I1=$abc$44715$auto$rtlil.cc:1836:ReduceOr$16064_new_inv_ I2=$abc$44715$new_n1490_ I3=$abc$44715$auto$alumacc.cc:491:replace_alu$16076[7] O=$abc$44715$auto$simplemap.cc:250:simplemap_eqne$35852[3]_new_
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:51"
.param LUT_INIT 0011000000110011
.gate SB_LUT4 I0=$abc$44715$auto$alumacc.cc:491:replace_alu$16054[7] I1=$abc$44715$auto$simplemap.cc:127:simplemap_reduce$17358[2]_new_ I2=$abc$44715$auto$simplemap.cc:127:simplemap_reduce$19236[0]_new_inv_ I3=$abc$44715$auto$simplemap.cc:127:simplemap_reduce$19217[1]_new_inv_ O=$abc$44715$auto$rtlil.cc:1836:ReduceOr$16064_new_inv_
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:56"
.param LUT_INIT 0001010101010101
.gate SB_LUT4 I0=$false I1=$false I2=common.pb.spitx_bytecount[3] I3=common.pb.spitx_bytecount[2] O=$abc$44715$auto$simplemap.cc:127:simplemap_reduce$17358[2]_new_
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:46"
.param LUT_INIT 0000000011110000
.gate SB_LUT4 I0=$false I1=$false I2=$abc$44715$auto$dff2dffe.cc:158:make_patterns_logic$29217 I3=$abc$44715$auto$simplemap.cc:127:simplemap_reduce$35840[0]_new_ O=$abc$44715$new_n1811_
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:46"
.param LUT_INIT 0000000011110000
.gate SB_LUT4 I0=$abc$44715$auto$dff2dffe.cc:158:make_patterns_logic$29217 I1=$abc$44715$auto$simplemap.cc:127:simplemap_reduce$35862[2]_new_inv_ I2=$abc$44715$new_n1814_ I3=$abc$44715$techmap\common.pb.$procmux$12826_Y_new_inv_ O=$abc$44715$new_n1812_
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:56"
.param LUT_INIT 1010101000101010
.gate SB_LUT4 I0=$abc$44715$auto$simplemap.cc:127:simplemap_reduce$35840[0]_new_ I1=$abc$44715$auto$rtlil.cc:1836:ReduceOr$16064_new_inv_ I2=$abc$44715$auto$alumacc.cc:491:replace_alu$16076[7] I3=$abc$44715$new_n1490_ O=$abc$44715$techmap\common.pb.$procmux$12826_Y_new_inv_
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:56"
.param LUT_INIT 0100010001010100
.gate SB_LUT4 I0=$false I1=common.pb.spi.rx_irq_r I2=$abc$44715$auto$simplemap.cc:127:simplemap_reduce$35840[0]_new_ I3=common.pb.spitx_bytecount[0] O=$abc$44715$new_n1814_
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:51"
.param LUT_INIT 0000110011001100
.gate SB_LUT4 I0=$false I1=$abc$44715$auto$dff2dffe.cc:175:make_patterns_logic$36014 I2=$abc$44715$new_n1807_ I3=common.pb.spitx_len[0] O=$abc$44715$auto$dff2dffe.cc:175:make_patterns_logic$36148
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:51"
.param LUT_INIT 1100110000001100
.gate SB_LUT4 I0=$false I1=$abc$44715$new_n1812_ I2=$abc$44715$auto$simplemap.cc:250:simplemap_eqne$35937[3]_new_ I3=$abc$44715$new_n1807_ O=$abc$44715$auto$dff2dffe.cc:175:make_patterns_logic$36014
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:51"
.param LUT_INIT 0011000000110011
.gate SB_LUT4 I0=$false I1=$abc$44715$auto$simplemap.cc:127:simplemap_reduce$32288_new_inv_ I2=$abc$44715$auto$simplemap.cc:250:simplemap_eqne$35427[1]_new_ I3=$abc$44715$auto$simplemap.cc:127:simplemap_reduce$35862[2]_new_inv_ O=$abc$44715$auto$dff2dffe.cc:175:make_patterns_logic$36833
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:51"
.param LUT_INIT 0011001100111111
.gate SB_LUT4 I0=$false I1=$false I2=$abc$44715$auto$dff2dffe.cc:158:make_patterns_logic$29217 I3=common.pb.spi.rx_irq_r O=$abc$44715$auto$simplemap.cc:127:simplemap_reduce$32288_new_inv_
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:46"
.param LUT_INIT 0000000011110000
.gate SB_LUT4 I0=$abc$44715$auto$dff2dffe.cc:158:make_patterns_logic$29217 I1=common.pb.spi.rx_irq_r I2=$abc$44715$auto$simplemap.cc:250:simplemap_eqne$35427[1]_new_ I3=$abc$44715$auto$simplemap.cc:250:simplemap_eqne$37070[3]_new_inv_ O=$abc$44715$auto$dff2dffe.cc:175:make_patterns_logic$37082
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:56"
.param LUT_INIT 0101010111010101
.gate SB_LUT4 I0=$abc$44715$auto$dff2dffe.cc:158:make_patterns_logic$29217 I1=common.pb.spi.rx_irq_r I2=$abc$44715$auto$simplemap.cc:250:simplemap_eqne$35427[1]_new_ I3=$abc$44715$auto$simplemap.cc:250:simplemap_eqne$37118[1]_new_ O=$abc$44715$auto$dff2dffe.cc:175:make_patterns_logic$37142
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:56"
.param LUT_INIT 1101110101011101
.gate SB_LUT4 I0=$false I1=$abc$44715$new_n1811_ I2=common.pb.rx_buf_rd_addr[0] I3=$abc$44715$auto$dff2dffe.cc:175:make_patterns_logic$36014 O=$abc$44715$auto$dff2dffe.cc:175:make_patterns_logic$37856
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:51"
.param LUT_INIT 1100000000000000
.gate SB_LUT4 I0=$false I1=$abc$44715$new_n1806_ I2=$abc$44715$auto$simplemap.cc:250:simplemap_eqne$35852[3]_new_ I3=$abc$44715$techmap\common.pb.$eq$profibus_phy_mod.v:990$6250_Y_new_ O=$abc$44715$new_n1823_
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:51"
.param LUT_INIT 0000000011000000
.gate SB_LUT4 I0=$false I1=$false I2=$abc$44715$auto$simplemap.cc:127:simplemap_reduce$35840[0]_new_ I3=common.pb.spitx_bytecount[0] O=$abc$44715$auto$simplemap.cc:168:logic_reduce$19575
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:46"
.param LUT_INIT 1111111100001111
.gate SB_LUT4 I0=$false I1=$abc$44715$auto$dff2dffe.cc:158:make_patterns_logic$29217 I2=common.pb.timer_idle_active I3=$abc$44715$techmap\common.pb.$procmux$9294_Y O=$abc$44715$auto$dff2dffe.cc:175:make_patterns_logic$38689
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:51"
.param LUT_INIT 0011001111110011
.gate SB_LUT4 I0=common.pb.uart.tx_mod.tx_irq I1=common.pb.uart.rx_mod.rx_active I2=common.pb.uart.tx_mod.tx_active I3=common.pb.uart.rx_mod.rx_irq O=$abc$44715$techmap\common.pb.$procmux$9294_Y
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:56"
.param LUT_INIT 0000000000000001
.gate SB_LUT4 I0=$false I1=$abc$44715$auto$alumacc.cc:491:replace_alu$16049[23] I2=$abc$44715$techmap\common.pb.$procmux$9294_Y I3=$abc$44715$auto$dff2dffe.cc:158:make_patterns_logic$29217 O=$abc$44715$auto$dff2dffe.cc:158:make_patterns_logic$39268
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:51"
.param LUT_INIT 0011111111111111
.gate SB_LUT4 I0=$false I1=$abc$44715$auto$dff2dffe.cc:158:make_patterns_logic$39268 I2=$abc$44715$auto$ice40_ffinit.cc:140:execute$44090 I3=$abc$44715$techmap\common.pb.$procmux$9294_Y O=$abc$44715$auto$dff2dffe.cc:175:make_patterns_logic$39306
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:51"
.param LUT_INIT 0000110011001100
.gate SB_LUT4 I0=common.pb.spi.ss_s I1=$abc$44715$auto$rtlil.cc:1836:ReduceOr$16042 I2=common.pb.spi.sync_sck.shiftreg[2] I3=common.pb.spi.sync_sck.out O=$abc$44715$auto$dff2dffe.cc:158:make_patterns_logic$39574
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:56"
.param LUT_INIT 1110111111101110
.gate SB_LUT4 I0=$false I1=$false I2=$abc$44715$new_n1832_ I3=$abc$44715$auto$rtlil.cc:1836:ReduceOr$16042 O=$abc$44715$auto$dff2dffe.cc:175:make_patterns_logic$39612
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:46"
.param LUT_INIT 1111111100001111
.gate SB_LUT4 I0=common.pb.spi.ss_s I1=common.pb.spi.sync_sck.out I2=common.pb.spi.bit_count[0] I3=common.pb.spi.sync_sck.shiftreg[2] O=$abc$44715$new_n1832_
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:56"
.param LUT_INIT 0101010100010101
.gate SB_LUT4 I0=common.pb.spi.ss_s I1=common.pb.spi.sync_sck.out I2=common.pb.spi.sync_sck.shiftreg[2] I3=$abc$44715$auto$rtlil.cc:1836:ReduceOr$16042 O=$abc$44715$auto$dff2dffe.cc:158:make_patterns_logic$39760
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:56"
.param LUT_INIT 1010101010101110
.gate SB_LUT4 I0=$false I1=$false I2=$abc$44715$auto$rtlil.cc:1836:ReduceOr$16042 I3=common.pb.spi.ss_s O=$abc$44715$auto$dff2dffe.cc:175:make_patterns_logic$39847
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:46"
.param LUT_INIT 0000000011110000
.gate SB_LUT4 I0=common.pb.spi.ss_s I1=$abc$44715$auto$simplemap.cc:168:logic_reduce$20473_new_inv_ I2=common.pb.spi.sync_sck.shiftreg[2] I3=common.pb.spi.sync_sck.out O=$abc$44715$auto$dff2dffe.cc:158:make_patterns_logic$39664
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:56"
.param LUT_INIT 1110111011111110
.gate SB_LUT4 I0=$false I1=$false I2=$abc$44715$new_n1440_ I3=common.pb.spi.bit_count[3] O=$abc$44715$auto$simplemap.cc:168:logic_reduce$20473_new_inv_
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:46"
.param LUT_INIT 0000000011110000
.gate SB_LUT4 I0=common.pb.n_reset I1=$abc$44715$new_n1838_ I2=common.pb.uart_tx_trigger I3=common.pb.uart.tx_trigger_req O=$abc$44715$auto$dff2dffe.cc:175:make_patterns_logic$40020
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:56"
.param LUT_INIT 1101110111111101
.gate SB_LUT4 I0=common.pb.uart.tx_trigger_req I1=common.pb.uart.arb_mod.rx I2=common.pb.uart.rx_mod.rx_active I3=$abc$44715$auto$rtlil.cc:1969:NotGate$44281 O=$abc$44715$new_n1838_
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:56"
.param LUT_INIT 0000000000001000
.gate SB_LUT4 I0=$abc$44715$auto$dff2dffe.cc:175:make_patterns_logic$40852 I1=$abc$44715$techmap\common.pb.uart.tx_mod.$procmux$15460_Y I2=common.pb.uart.tx_trigger_req I3=$abc$44715$auto$rtlil.cc:1969:NotGate$44285 O=$abc$44715$auto$dff2dffe.cc:175:make_patterns_logic$40319
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:56"
.param LUT_INIT 1010101010100010
.gate SB_LUT4 I0=$abc$44715$auto$simplemap.cc:127:simplemap_reduce$40854[0]_new_inv_ I1=$abc$44715$auto$rtlil.cc:1969:NotGate$44285 I2=$abc$44715$new_n1430_ I3=$abc$44715$auto$simplemap.cc:250:simplemap_eqne$40309[1]_new_inv_ O=$abc$44715$auto$dff2dffe.cc:175:make_patterns_logic$40852
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:56"
.param LUT_INIT 0100010001010100
.gate SB_LUT4 I0=$abc$44715$techmap\common.pb.uart.tx_mod.$procmux$15532_Y I1=$abc$44715$auto$rtlil.cc:1969:NotGate$44285 I2=common.pb.uart.tx_mod.symclk.setup I3=common.pb.uart.tx_mod.symclk.symend O=$abc$44715$auto$simplemap.cc:127:simplemap_reduce$40854[0]_new_inv_
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:56"
.param LUT_INIT 0010000000100010
.gate SB_LUT4 I0=common.pb.uart.tx_mod.sym_count[3] I1=common.pb.uart.tx_mod.sym_count[0] I2=common.pb.uart.tx_mod.sym_count[1] I3=common.pb.uart.tx_mod.sym_count[2] O=$abc$44715$techmap\common.pb.uart.tx_mod.$procmux$15532_Y
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:56"
.param LUT_INIT 0000000010000000
.gate SB_LUT4 I0=$false I1=$false I2=$abc$44715$auto$simplemap.cc:127:simplemap_reduce$40245[0]_new_ I3=common.pb.uart.tx_mod.sym_count[0] O=$abc$44715$techmap\common.pb.uart.tx_mod.$procmux$15460_Y
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:46"
.param LUT_INIT 0000000011110000
.gate SB_LUT4 I0=$false I1=common.pb.uart.tx_trigger_req I2=$abc$44715$techmap\common.pb.uart.tx_mod.$procmux$15460_Y I3=$abc$44715$auto$rtlil.cc:1969:NotGate$44285 O=$abc$44715$auto$dff2dffe.cc:175:make_patterns_logic$40465
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:51"
.param LUT_INIT 0000000011000000
.gate SB_LUT4 I0=common.pb.uart.tx_mod.symclk.setup I1=$abc$44715$auto$rtlil.cc:1969:NotGate$44285 I2=$abc$44715$new_n1430_ I3=$abc$44715$techmap\common.pb.uart.tx_mod.$procmux$15532_Y O=$abc$44715$auto$dff2dffe.cc:175:make_patterns_logic$40759
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:56"
.param LUT_INIT 1110111011111110
.gate SB_LUT4 I0=$abc$44715$auto$simplemap.cc:127:simplemap_reduce$40854[0]_new_inv_ I1=$abc$44715$techmap\common.pb.uart.tx_mod.$procmux$15460_Y I2=common.pb.uart.tx_trigger_req I3=$abc$44715$auto$rtlil.cc:1969:NotGate$44285 O=$abc$44715$auto$dff2dffe.cc:175:make_patterns_logic$40917
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:56"
.param LUT_INIT 0101010101010001
.gate SB_LUT4 I0=$abc$44715$auto$rtlil.cc:1969:NotGate$44281 I1=$abc$44715$new_n1849_ I2=$abc$44715$techmap\common.pb.uart.rx_mod.$procmux$15345_Y I3=common.pb.uart.rx_mod.symclk.sample O=$abc$44715$auto$dff2dffe.cc:175:make_patterns_logic$41173
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:56"
.param LUT_INIT 1110111010101110
.gate SB_LUT4 I0=common.pb.uart.rx_mod.sym_count[3] I1=common.pb.uart.rx_mod.sym_count[0] I2=common.pb.uart.rx_mod.sym_count[1] I3=common.pb.uart.rx_mod.sym_count[2] O=$abc$44715$techmap\common.pb.uart.rx_mod.$procmux$15345_Y
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:56"
.param LUT_INIT 0000000010000000
.gate SB_LUT4 I0=common.pb.uart.rx_mod.sym_count[3] I1=common.pb.uart.rx_mod.sym_count[0] I2=common.pb.uart.rx_mod.sym_count[1] I3=common.pb.uart.rx_mod.sym_count[2] O=$abc$44715$new_n1849_
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:56"
.param LUT_INIT 1010101010000001
.gate SB_LUT4 I0=$abc$44715$auto$rtlil.cc:1969:NotGate$44281 I1=$abc$44715$new_n1851_ I2=$abc$44715$techmap\common.pb.uart.rx_mod.$procmux$15345_Y I3=common.pb.uart.rx_mod.symclk.sample O=$abc$44715$auto$dff2dffe.cc:175:make_patterns_logic$42153
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:56"
.param LUT_INIT 1011101110101011
.gate SB_LUT4 I0=$false I1=$abc$44715$auto$rtlil.cc:1969:NotGate$44581 I2=common.pb.uart.arb_mod.rx I3=common.pb.uart.rx_mod.rx_edge.prev_signal O=$abc$44715$new_n1851_
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:51"
.param LUT_INIT 1100000011001100
.gate SB_LUT4 I0=$false I1=$abc$44715$auto$dff2dffe.cc:175:make_patterns_logic$41173 I2=$abc$44715$new_n1851_ I3=$abc$44715$auto$rtlil.cc:1969:NotGate$44281 O=$abc$44715$auto$dff2dffe.cc:175:make_patterns_logic$41256
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:51"
.param LUT_INIT 1100110000001100
.gate SB_LUT4 I0=common.pb.uart.rx_mod.sym_count[0] I1=common.pb.uart.rx_mod.symclk.sample I2=$abc$44715$auto$simplemap.cc:127:simplemap_reduce$41156[0]_new_ I3=$abc$44715$auto$rtlil.cc:1969:NotGate$44281 O=$abc$44715$auto$dff2dffe.cc:175:make_patterns_logic$41306
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:56"
.param LUT_INIT 0000000010000000
.gate SB_LUT4 I0=$false I1=common.pb.uart.rx_mod.symclk.sample I2=$abc$44715$techmap\common.pb.uart.rx_mod.$procmux$15284_Y[1]_new_ I3=$abc$44715$auto$rtlil.cc:1969:NotGate$44281 O=$abc$44715$auto$dff2dffe.cc:175:make_patterns_logic$41390
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:51"
.param LUT_INIT 0000000011000000
.gate SB_LUT4 I0=common.pb.uart.rx_mod.sym_count[3] I1=common.pb.uart.rx_mod.sym_count[1] I2=common.pb.uart.rx_mod.sym_count[2] I3=common.pb.uart.rx_mod.sym_count[0] O=$abc$44715$techmap\common.pb.uart.rx_mod.$procmux$15284_Y[1]_new_
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:56"
.param LUT_INIT 0000000000001000
.gate SB_LUT4 I0=$abc$44715$new_n2670_ I1=$abc$44715$new_n1860_ I2=$abc$44715$new_n1862_ I3=$abc$44715$auto$simplemap.cc:127:simplemap_reduce$21307[1]_new_inv_ O=$abc$44715$auto$dff2dffe.cc:175:make_patterns_logic$41480
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:56"
.param LUT_INIT 1010001000100010
.gate SB_LUT4 I0=common.pb.uart.rx_mod.symclk.sample I1=common.pb.uart.rx_mod.sym_count[3] I2=$abc$44715$new_n1437_ I3=$abc$44715$auto$rtlil.cc:1969:NotGate$44281 O=$abc$44715$new_n1860_
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:56"
.param LUT_INIT 0000000010000010
.gate SB_LUT4 I0=$false I1=common.pb.uart.rx_mod.sym_count[2] I2=common.pb.uart.rx_mod.sym_count[1] I3=$abc$44715$auto$simplemap.cc:250:simplemap_eqne$21196[3] O=$abc$44715$auto$simplemap.cc:127:simplemap_reduce$21307[1]_new_inv_
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:51"
.param LUT_INIT 0000000000111100
.gate SB_LUT4 I0=$abc$44715$auto$alumacc.cc:474:replace_alu$16160.C[31] I1=common.pb.uart.rx_mod.sym_count[1] I2=$abc$44715$auto$simplemap.cc:250:simplemap_eqne$21196[4] I3=common.pb.uart.rx_mod.sym_count[0] O=$abc$44715$new_n1862_
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:56"
.param LUT_INIT 0000000000001000
.gate SB_LUT4 I0=$abc$44715$new_n2670_ I1=$abc$44715$new_n1860_ I2=$abc$44715$new_n1864_ I3=$abc$44715$auto$simplemap.cc:127:simplemap_reduce$21307[1]_new_inv_ O=$abc$44715$auto$dff2dffe.cc:175:make_patterns_logic$41570
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:56"
.param LUT_INIT 1010001000100010
.gate SB_LUT4 I0=$abc$44715$auto$alumacc.cc:474:replace_alu$16160.C[31] I1=common.pb.uart.rx_mod.sym_count[1] I2=common.pb.uart.rx_mod.sym_count[0] I3=$abc$44715$auto$simplemap.cc:250:simplemap_eqne$21196[4] O=$abc$44715$new_n1864_
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:56"
.param LUT_INIT 0000000010000000
.gate SB_LUT4 I0=$abc$44715$new_n2670_ I1=$abc$44715$new_n1860_ I2=$abc$44715$new_n1866_ I3=$abc$44715$auto$simplemap.cc:127:simplemap_reduce$21307[1]_new_inv_ O=$abc$44715$auto$dff2dffe.cc:175:make_patterns_logic$41660
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:56"
.param LUT_INIT 1010001000100010
.gate SB_LUT4 I0=$abc$44715$auto$alumacc.cc:474:replace_alu$16160.C[31] I1=common.pb.uart.rx_mod.sym_count[1] I2=$abc$44715$auto$simplemap.cc:250:simplemap_eqne$21196[4] I3=common.pb.uart.rx_mod.sym_count[0] O=$abc$44715$new_n1866_
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:56"
.param LUT_INIT 0000000000000010
.gate SB_LUT4 I0=$abc$44715$new_n2670_ I1=$abc$44715$new_n1860_ I2=$abc$44715$new_n1868_ I3=$abc$44715$auto$simplemap.cc:127:simplemap_reduce$21307[1]_new_inv_ O=$abc$44715$auto$dff2dffe.cc:175:make_patterns_logic$41750
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:56"
.param LUT_INIT 1010001000100010
.gate SB_LUT4 I0=$abc$44715$auto$alumacc.cc:474:replace_alu$16160.C[31] I1=common.pb.uart.rx_mod.sym_count[0] I2=common.pb.uart.rx_mod.sym_count[1] I3=$abc$44715$auto$simplemap.cc:250:simplemap_eqne$21196[4] O=$abc$44715$new_n1868_
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:56"
.param LUT_INIT 0000000000001000
.gate SB_LUT4 I0=$abc$44715$new_n2670_ I1=$abc$44715$new_n1860_ I2=$abc$44715$auto$simplemap.cc:127:simplemap_reduce$21232[1]_new_inv_ I3=$abc$44715$new_n1862_ O=$abc$44715$auto$dff2dffe.cc:175:make_patterns_logic$41840
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:56"
.param LUT_INIT 1010001000100010
.gate SB_LUT4 I0=$false I1=common.pb.uart.rx_mod.sym_count[2] I2=common.pb.uart.rx_mod.sym_count[1] I3=$abc$44715$auto$simplemap.cc:250:simplemap_eqne$21196[3] O=$abc$44715$auto$simplemap.cc:127:simplemap_reduce$21232[1]_new_inv_
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:51"
.param LUT_INIT 0000000011000011
.gate SB_LUT4 I0=$abc$44715$new_n2670_ I1=$abc$44715$new_n1860_ I2=$abc$44715$auto$simplemap.cc:127:simplemap_reduce$21232[1]_new_inv_ I3=$abc$44715$new_n1864_ O=$abc$44715$auto$dff2dffe.cc:175:make_patterns_logic$41930
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:56"
.param LUT_INIT 1010001000100010
.gate SB_LUT4 I0=$abc$44715$new_n2670_ I1=$abc$44715$new_n1860_ I2=$abc$44715$auto$simplemap.cc:127:simplemap_reduce$21232[1]_new_inv_ I3=$abc$44715$new_n1866_ O=$abc$44715$auto$dff2dffe.cc:175:make_patterns_logic$42020
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:56"
.param LUT_INIT 1010001000100010
.gate SB_LUT4 I0=$abc$44715$new_n2670_ I1=$abc$44715$new_n1860_ I2=$abc$44715$auto$simplemap.cc:127:simplemap_reduce$21232[1]_new_inv_ I3=$abc$44715$new_n1868_ O=$abc$44715$auto$dff2dffe.cc:175:make_patterns_logic$42110
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:56"
.param LUT_INIT 1010001000100010
.gate SB_LUT4 I0=$false I1=$abc$44715$new_n1875_ I2=$abc$44715$auto$dff2dffe.cc:175:make_patterns_logic$41173 I3=$abc$44715$auto$rtlil.cc:1969:NotGate$44581 O=$abc$44715$auto$dff2dffe.cc:175:make_patterns_logic$42366
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:51"
.param LUT_INIT 0000000011000000
.gate SB_LUT4 I0=$false I1=$false I2=$abc$44715$auto$rtlil.cc:1969:NotGate$44281 I3=common.pb.uart.rx_mod.sym_count[2] O=$abc$44715$new_n1875_
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:46"
.param LUT_INIT 0000000000001111
.gate SB_LUT4 I0=$false I1=common.pb.uart.rx_mod.rx_buf[4] I2=common.pb.uart.rx_mod.rx_buf[6] I3=$abc$44715$new_n1877_ O=$abc$44715$techmap\common.pb.uart.rx_mod.$0\rx_parity_ok[0:0]
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:51"
.param LUT_INIT 0011110011000011
.gate SB_LUT4 I0=common.pb.uart.rx_mod.rx_parity_buf I1=common.pb.uart.rx_mod.rx_buf[0] I2=common.pb.uart.rx_mod.rx_buf[5] I3=$abc$44715$new_n1878_ O=$abc$44715$new_n1877_
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:56"
.param LUT_INIT 1001011001101001
.gate SB_LUT4 I0=common.pb.uart.rx_mod.rx_buf[1] I1=common.pb.uart.rx_mod.rx_buf[2] I2=common.pb.uart.rx_mod.rx_buf[3] I3=common.pb.uart.rx_mod.rx_buf[7] O=$abc$44715$new_n1878_
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:56"
.param LUT_INIT 1001011001101001
.gate SB_LUT4 I0=$false I1=$abc$44715$auto$simplemap.cc:168:logic_reduce$22042[2]_new_inv_ I2=$abc$44715$auto$simplemap.cc:168:logic_reduce$22042[3]_new_inv_ I3=$abc$44715$new_n1880_ O=$abc$44715$techmap\common.pb.uart.tx_mod.symclk.$eq$uart_mod.v:73$17_Y
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:51"
.param LUT_INIT 1100000000000000
.gate SB_LUT4 I0=$abc$44715$auto$simplemap.cc:168:logic_reduce$22042[4]_new_inv_ I1=$abc$44715$auto$simplemap.cc:168:logic_reduce$22042[5]_new_inv_ I2=$abc$44715$auto$simplemap.cc:168:logic_reduce$22042[0]_new_inv_ I3=$abc$44715$auto$simplemap.cc:168:logic_reduce$22042[1]_new_inv_ O=$abc$44715$new_n1880_
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:56"
.param LUT_INIT 1000000000000000
.gate SB_LUT4 I0=common.pb.uart.tx_mod.symclk.count[7] I1=common.pb.uart.tx_mod.symclk.count[6] I2=common.pb.uart.tx_mod.symclk.count[5] I3=common.pb.uart.tx_mod.symclk.count[4] O=$abc$44715$auto$simplemap.cc:168:logic_reduce$22042[1]_new_inv_
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:56"
.param LUT_INIT 0000000000000001
.gate SB_LUT4 I0=common.pb.uart.tx_mod.symclk.count[3] I1=common.pb.uart.tx_mod.symclk.count[2] I2=common.pb.uart.tx_mod.symclk.count[1] I3=common.pb.uart.tx_mod.symclk.count[0] O=$abc$44715$auto$simplemap.cc:168:logic_reduce$22042[0]_new_inv_
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:56"
.param LUT_INIT 0000000000000001
.gate SB_LUT4 I0=common.pb.uart.tx_mod.symclk.count[23] I1=common.pb.uart.tx_mod.symclk.count[22] I2=common.pb.uart.tx_mod.symclk.count[21] I3=common.pb.uart.tx_mod.symclk.count[20] O=$abc$44715$auto$simplemap.cc:168:logic_reduce$22042[5]_new_inv_
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:56"
.param LUT_INIT 0000000000000001
.gate SB_LUT4 I0=common.pb.uart.tx_mod.symclk.count[19] I1=common.pb.uart.tx_mod.symclk.count[18] I2=common.pb.uart.tx_mod.symclk.count[17] I3=common.pb.uart.tx_mod.symclk.count[16] O=$abc$44715$auto$simplemap.cc:168:logic_reduce$22042[4]_new_inv_
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:56"
.param LUT_INIT 0000000000000001
.gate SB_LUT4 I0=common.pb.uart.tx_mod.symclk.count[15] I1=common.pb.uart.tx_mod.symclk.count[14] I2=common.pb.uart.tx_mod.symclk.count[13] I3=common.pb.uart.tx_mod.symclk.count[12] O=$abc$44715$auto$simplemap.cc:168:logic_reduce$22042[3]_new_inv_
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:56"
.param LUT_INIT 0000000000000001
.gate SB_LUT4 I0=common.pb.uart.tx_mod.symclk.count[11] I1=common.pb.uart.tx_mod.symclk.count[10] I2=common.pb.uart.tx_mod.symclk.count[9] I3=common.pb.uart.tx_mod.symclk.count[8] O=$abc$44715$auto$simplemap.cc:168:logic_reduce$22042[2]_new_inv_
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:56"
.param LUT_INIT 0000000000000001
.gate SB_LUT4 I0=$false I1=$false I2=common.led_blink.led_on_count[0] I3=common.led_blink.led O=$abc$44715$techmap\common.led_blink.$procmux$9274_Y[0]
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:46"
.param LUT_INIT 0000111100000000
.gate SB_LUT4 I0=$false I1=$false I2=common.led_blink.led I3=common.led_blink.led_on_count[1] O=$abc$44715$techmap\common.led_blink.$procmux$9274_Y[1]
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:46"
.param LUT_INIT 0000000011110000
.gate SB_LUT4 I0=$false I1=$false I2=common.led_blink.led_off_count[0] I3=common.led_blink.led O=$abc$44715$techmap\common.led_blink.$procmux$9260_Y[0]
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:46"
.param LUT_INIT 0000000000001111
.gate SB_LUT4 I0=$false I1=$false I2=common.led_blink.led_off_count[1] I3=common.led_blink.led O=$abc$44715$techmap\common.led_blink.$procmux$9260_Y[1]
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:46"
.param LUT_INIT 1111111100001111
.gate SB_LUT4 I0=$false I1=$false I2=common.pb.spitx_bytecount[0] I3=$abc$44715$new_n1952_ O=$abc$44715$techmap\common.pb.$procmux$12940_Y[0]
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:46"
.param LUT_INIT 0000000000001111
.gate SB_LUT4 I0=$false I1=$abc$44715$techmap\common.pb.$procmux$12855_Y I2=$abc$44715$auto$simplemap.cc:127:simplemap_reduce$35862[2]_new_inv_ I3=$abc$44715$techmap\common.pb.$procmux$12826_Y_new_inv_ O=$abc$44715$new_n1952_
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:51"
.param LUT_INIT 0011001100000011
.gate SB_LUT4 I0=$false I1=$false I2=$abc$44715$auto$simplemap.cc:250:simplemap_eqne$35427[1]_new_ I3=$abc$44715$auto$simplemap.cc:250:simplemap_eqne$37070[3]_new_inv_ O=$abc$44715$techmap\common.pb.$procmux$12855_Y
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:46"
.param LUT_INIT 1111000000000000
.gate SB_LUT4 I0=$false I1=common.pb.spitx_bytecount[1] I2=common.pb.spitx_bytecount[0] I3=$abc$44715$new_n1952_ O=$abc$44715$techmap\common.pb.$procmux$12940_Y[1]
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:51"
.param LUT_INIT 0000000000111100
.gate SB_LUT4 I0=$false I1=$false I2=common.pb.spitx_len[0] I3=$abc$44715$auto$simplemap.cc:168:logic_reduce$19575 O=$abc$44715$techmap\common.pb.$procmux$12896_Y[0]
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:46"
.param LUT_INIT 0000111100000000
.gate SB_LUT4 I0=$false I1=$false I2=$abc$44715$auto$simplemap.cc:168:logic_reduce$19575 I3=common.pb.spitx_len[1] O=$abc$44715$techmap\common.pb.$procmux$12896_Y[1]
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:46"
.param LUT_INIT 0000000011110000
.gate SB_LUT4 I0=$abc$44715$techmap\common.pb.$procmux$12826_Y_new_inv_ I1=common.pb.spitx_data_running I2=common.pb.spitx_ctrl_running I3=$abc$44715$techmap\common.pb.$eq$profibus_phy_mod.v:990$6250_Y_new_ O=$abc$44715$techmap\common.pb.$procmux$12830_Y
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:56"
.param LUT_INIT 0100010001000101
.gate SB_LUT4 I0=$abc$44715$new_n1972_ I1=$abc$44715$auto$simplemap.cc:127:simplemap_reduce$35862[2]_new_inv_ I2=$abc$44715$auto$simplemap.cc:127:simplemap_reduce$35840[0]_new_ I3=$abc$44715$techmap\common.pb.$procmux$9771_Y_new_inv_ O=$abc$44715$techmap\common.pb.$2\spi_tx_data[7:0][1]
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:56"
.param LUT_INIT 1010101010101110
.gate SB_LUT4 I0=$abc$44715$auto$simplemap.cc:250:simplemap_eqne$35852[3]_new_ I1=common.pb.spitx_len[1] I2=common.pb.rx_buf_rd_data[1] I3=$abc$44715$auto$simplemap.cc:250:simplemap_eqne$35937[3]_new_ O=$abc$44715$techmap\common.pb.$procmux$9771_Y_new_inv_
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:56"
.param LUT_INIT 0001101110111011
.gate SB_LUT4 I0=$false I1=$abc$44715$auto$simplemap.cc:250:simplemap_eqne$35427[1]_new_ I2=$abc$44715$new_n1973_ I3=$abc$44715$new_n1977_ O=$abc$44715$new_n1972_
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:51"
.param LUT_INIT 0000110011001100
.gate SB_LUT4 I0=$abc$44715$new_n1976_ I1=$abc$44715$techmap$techmap\common.pb.$procmux$11552.$and$/home/mb/fpga-toolchain/yosys/bin/../share/yosys/techmap.v:434$19164_Y_new_ I2=$abc$44715$new_n1474_ I3=common.pb.spitx_ctrl_reply_data[9] O=$abc$44715$new_n1973_
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:56"
.param LUT_INIT 0000000100010001
.gate SB_LUT4 I0=$false I1=$false I2=common.pb.spitx_crc[1] I3=$abc$44715$techmap\common.pb.$procmux$10683_CMP_new_ O=$abc$44715$techmap$techmap\common.pb.$procmux$11552.$and$/home/mb/fpga-toolchain/yosys/bin/../share/yosys/techmap.v:434$19164_Y_new_
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:46"
.param LUT_INIT 1111000000000000
.gate SB_LUT4 I0=common.pb.spitx_bytecount[2] I1=$abc$44715$auto$simplemap.cc:127:simplemap_reduce$19217[1]_new_inv_ I2=$abc$44715$auto$simplemap.cc:127:simplemap_reduce$19284[0]_new_inv_ I3=common.pb.spitx_bytecount[3] O=$abc$44715$techmap\common.pb.$procmux$10683_CMP_new_
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:56"
.param LUT_INIT 0000000010000000
.gate SB_LUT4 I0=$false I1=$false I2=common.pb.spitx_ctrl_reply_data[1] I3=$abc$44715$techmap\common.pb.$procmux$10684_CMP_new_ O=$abc$44715$new_n1976_
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:46"
.param LUT_INIT 1111000000000000
.gate SB_LUT4 I0=$abc$44715$new_n1978_ I1=$abc$44715$new_n1466_ I2=$abc$44715$new_n1490_ I3=common.pb.spitx_ctrl_reply[1] O=$abc$44715$new_n1977_
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:56"
.param LUT_INIT 0000001000100010
.gate SB_LUT4 I0=common.pb.spitx_ctrl_reply_data[25] I1=$abc$44715$auto$rtlil.cc:1835:ReduceAnd$16071_new_ I2=$abc$44715$techmap\common.pb.$procmux$10686_CMP_new_ I3=common.pb.spitx_ctrl_reply_data[17] O=$abc$44715$new_n1978_
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:56"
.param LUT_INIT 0000011101110111
.gate SB_LUT4 I0=$abc$44715$new_n1982_ I1=$abc$44715$auto$simplemap.cc:127:simplemap_reduce$35862[2]_new_inv_ I2=$abc$44715$auto$simplemap.cc:127:simplemap_reduce$23962[3]_new_inv_ I3=$abc$44715$new_n1980_ O=$abc$44715$techmap\common.pb.$2\spi_tx_data[7:0][2]
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:56"
.param LUT_INIT 1110111010101110
.gate SB_LUT4 I0=$abc$44715$new_n1981_ I1=$abc$44715$auto$simplemap.cc:250:simplemap_eqne$35852[3]_new_ I2=common.pb.rx_buf_rd_data[2] I3=$abc$44715$auto$simplemap.cc:250:simplemap_eqne$35937[3]_new_ O=$abc$44715$new_n1980_
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:56"
.param LUT_INIT 1010001000100010
.gate SB_LUT4 I0=$false I1=$abc$44715$new_n1466_ I2=$abc$44715$auto$simplemap.cc:250:simplemap_eqne$35852[3]_new_ I3=common.pb.spitx_len[2] O=$abc$44715$new_n1981_
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:51"
.param LUT_INIT 0011001100110000
.gate SB_LUT4 I0=$false I1=$false I2=$abc$44715$auto$simplemap.cc:250:simplemap_eqne$35427[1]_new_ I3=$abc$44715$techmap$techmap\common.pb.$procmux$11499.$reduce_or$/home/mb/fpga-toolchain/yosys/bin/../share/yosys/techmap.v:441$19172_Y_new_inv_ O=$abc$44715$new_n1982_
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:46"
.param LUT_INIT 0000000011110000
.gate SB_LUT4 I0=$abc$44715$new_n1989_ I1=$abc$44715$new_n1988_ I2=$abc$44715$new_n1987_ I3=$abc$44715$auto$simplemap.cc:127:simplemap_reduce$23962[3]_new_inv_ O=$abc$44715$techmap$techmap\common.pb.$procmux$11499.$reduce_or$/home/mb/fpga-toolchain/yosys/bin/../share/yosys/techmap.v:441$19172_Y_new_inv_
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:56"
.param LUT_INIT 1000000000000000
.gate SB_LUT4 I0=$false I1=$abc$44715$auto$simplemap.cc:127:simplemap_reduce$35840[0]_new_ I2=common.pb.spitx_bytecount[0] I3=$abc$44715$common.pb.new_status_available_new_inv_ O=$abc$44715$auto$simplemap.cc:127:simplemap_reduce$23962[3]_new_inv_
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:51"
.param LUT_INIT 1111001100110011
.gate SB_LUT4 I0=$abc$44715$common.pb.any_reset_status_new_inv_ I1=$abc$44715$techmap\common.pb.$0$func$\spirx_ctrl_crcerr_get$profibus_phy_mod.v:275$5347$\spirx_ctrl_crcerr_get[0:0]$6276_new_inv_ I2=$abc$44715$techmap\common.pb.$0$func$\tx_buf_overflow_get$profibus_phy_mod.v:274$5345$\tx_buf_overflow_get[0:0]$6268_new_inv_ I3=$abc$44715$techmap\common.pb.$0$func$\rx_buf_overflow_get$profibus_phy_mod.v:275$5346$\rx_buf_overflow_get[0:0]$6272_new_inv_ O=$abc$44715$common.pb.new_status_available_new_inv_
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:56"
.param LUT_INIT 1000000000000000
.gate SB_LUT4 I0=$false I1=common.pb.n_poweronreset_status I2=common.pb.n_hardreset_status I3=common.pb.softreset_status O=$abc$44715$common.pb.any_reset_status_new_inv_
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:51"
.param LUT_INIT 0000000011000000
.gate SB_LUT4 I0=common.pb.spitx_ctrl_reply_data[18] I1=$abc$44715$techmap\common.pb.$procmux$10686_CMP_new_ I2=$abc$44715$new_n1490_ I3=common.pb.spitx_ctrl_reply[2] O=$abc$44715$new_n1987_
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:56"
.param LUT_INIT 0000011101110111
.gate SB_LUT4 I0=common.pb.spitx_ctrl_reply_data[10] I1=$abc$44715$new_n1474_ I2=$abc$44715$techmap\common.pb.$procmux$10684_CMP_new_ I3=common.pb.spitx_ctrl_reply_data[2] O=$abc$44715$new_n1988_
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:56"
.param LUT_INIT 0000011101110111
.gate SB_LUT4 I0=common.pb.spitx_ctrl_reply_data[26] I1=$abc$44715$auto$rtlil.cc:1835:ReduceAnd$16071_new_ I2=$abc$44715$techmap\common.pb.$procmux$10683_CMP_new_ I3=common.pb.spitx_crc[2] O=$abc$44715$new_n1989_
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:56"
.param LUT_INIT 0000011101110111
.gate SB_LUT4 I0=$abc$44715$new_n1993_ I1=$abc$44715$new_n1999_ I2=$abc$44715$new_n1994_ I3=$abc$44715$new_n1991_ O=$abc$44715$techmap\common.pb.$2\spi_tx_data[7:0][3]
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:56"
.param LUT_INIT 1110111011101010
.gate SB_LUT4 I0=$abc$44715$new_n1992_ I1=$abc$44715$auto$simplemap.cc:250:simplemap_eqne$35852[3]_new_ I2=common.pb.rx_buf_rd_data[3] I3=$abc$44715$auto$simplemap.cc:250:simplemap_eqne$35937[3]_new_ O=$abc$44715$new_n1991_
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:56"
.param LUT_INIT 1010001000100010
.gate SB_LUT4 I0=$false I1=$abc$44715$new_n1466_ I2=$abc$44715$auto$simplemap.cc:250:simplemap_eqne$35852[3]_new_ I3=common.pb.spitx_len[3] O=$abc$44715$new_n1992_
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:51"
.param LUT_INIT 0011001100110000
.gate SB_LUT4 I0=$abc$44715$auto$simplemap.cc:250:simplemap_eqne$35427[1]_new_ I1=$abc$44715$new_n1995_ I2=$abc$44715$new_n1998_ I3=$abc$44715$new_n1994_ O=$abc$44715$new_n1993_
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:56"
.param LUT_INIT 1010101000101010
.gate SB_LUT4 I0=$false I1=$false I2=$abc$44715$new_n1466_ I3=$abc$44715$common.pb.any_reset_status_new_inv_ O=$abc$44715$new_n1994_
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:46"
.param LUT_INIT 0000000011110000
.gate SB_LUT4 I0=$abc$44715$auto$simplemap.cc:127:simplemap_reduce$23933[0]_new_inv_ I1=$abc$44715$new_n1997_ I2=$abc$44715$auto$rtlil.cc:1835:ReduceAnd$16071_new_ I3=common.pb.spitx_ctrl_reply_data[27] O=$abc$44715$new_n1995_
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:56"
.param LUT_INIT 0000001000100010
.gate SB_LUT4 I0=common.pb.spitx_ctrl_reply_data[3] I1=$abc$44715$techmap\common.pb.$procmux$10684_CMP_new_ I2=common.pb.spitx_crc[3] I3=$abc$44715$techmap\common.pb.$procmux$10683_CMP_new_ O=$abc$44715$auto$simplemap.cc:127:simplemap_reduce$23933[0]_new_inv_
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:56"
.param LUT_INIT 0000011101110111
.gate SB_LUT4 I0=$false I1=$false I2=common.pb.spitx_ctrl_reply[3] I3=$abc$44715$new_n1490_ O=$abc$44715$new_n1997_
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:46"
.param LUT_INIT 1111000000000000
.gate SB_LUT4 I0=common.pb.spitx_ctrl_reply_data[11] I1=$abc$44715$new_n1474_ I2=common.pb.spitx_ctrl_reply_data[19] I3=$abc$44715$techmap\common.pb.$procmux$10686_CMP_new_ O=$abc$44715$new_n1998_
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:56"
.param LUT_INIT 0000011101110111
.gate SB_LUT4 I0=$false I1=$false I2=$abc$44715$auto$simplemap.cc:168:logic_reduce$19575 I3=$abc$44715$auto$simplemap.cc:127:simplemap_reduce$35862[2]_new_inv_ O=$abc$44715$new_n1999_
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:46"
.param LUT_INIT 1111000000000000
.gate SB_LUT4 I0=$abc$44715$auto$simplemap.cc:127:simplemap_reduce$35862[2]_new_inv_ I1=$abc$44715$techmap\common.pb.$4\spi_tx_data[7:0][4]_new_inv_ I2=$abc$44715$auto$simplemap.cc:250:simplemap_eqne$35427[1]_new_ I3=$abc$44715$techmap$techmap\common.pb.$procmux$11399.$reduce_or$/home/mb/fpga-toolchain/yosys/bin/../share/yosys/techmap.v:441$19172_Y_new_inv_ O=$abc$44715$techmap\common.pb.$2\spi_tx_data[7:0][4]
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:56"
.param LUT_INIT 0010001011110010
.gate SB_LUT4 I0=$abc$44715$new_n2002_ I1=common.pb.rx_buf_rd_data[4] I2=$abc$44715$new_n1823_ I3=$abc$44715$auto$simplemap.cc:127:simplemap_reduce$35840[0]_new_ O=$abc$44715$techmap\common.pb.$4\spi_tx_data[7:0][4]_new_inv_
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:56"
.param LUT_INIT 1010101000101010
.gate SB_LUT4 I0=$false I1=$abc$44715$auto$simplemap.cc:168:logic_reduce$19575 I2=$abc$44715$techmap\common.pb.$procmux$12826_Y_new_inv_ I3=common.pb.spitx_len[4] O=$abc$44715$new_n2002_
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:51"
.param LUT_INIT 0000110011001100
.gate SB_LUT4 I0=$abc$44715$new_n2006_ I1=$abc$44715$new_n2004_ I2=$abc$44715$auto$rtlil.cc:1835:ReduceAnd$16071_new_ I3=common.pb.spitx_ctrl_reply_data[28] O=$abc$44715$techmap$techmap\common.pb.$procmux$11399.$reduce_or$/home/mb/fpga-toolchain/yosys/bin/../share/yosys/techmap.v:441$19172_Y_new_inv_
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:56"
.param LUT_INIT 0000100010001000
.gate SB_LUT4 I0=$abc$44715$new_n2005_ I1=$abc$44715$auto$simplemap.cc:168:logic_reduce$19575 I2=$abc$44715$new_n1474_ I3=common.pb.spitx_ctrl_reply_data[12] O=$abc$44715$new_n2004_
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:56"
.param LUT_INIT 0000100010001000
.gate SB_LUT4 I0=common.pb.spitx_ctrl_reply_data[4] I1=$abc$44715$techmap\common.pb.$procmux$10684_CMP_new_ I2=common.pb.spitx_ctrl_reply_data[20] I3=$abc$44715$techmap\common.pb.$procmux$10686_CMP_new_ O=$abc$44715$new_n2005_
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:56"
.param LUT_INIT 0000011101110111
.gate SB_LUT4 I0=common.pb.spitx_ctrl_reply[4] I1=$abc$44715$new_n1490_ I2=common.pb.spitx_crc[4] I3=$abc$44715$techmap\common.pb.$procmux$10683_CMP_new_ O=$abc$44715$new_n2006_
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:56"
.param LUT_INIT 0000011101110111
.gate SB_LUT4 I0=$abc$44715$new_n2009_ I1=$abc$44715$auto$simplemap.cc:127:simplemap_reduce$35862[2]_new_inv_ I2=$abc$44715$auto$simplemap.cc:127:simplemap_reduce$35840[0]_new_ I3=$abc$44715$techmap\common.pb.$procmux$9843_Y_new_inv_ O=$abc$44715$techmap\common.pb.$2\spi_tx_data[7:0][5]
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:56"
.param LUT_INIT 1010101010101110
.gate SB_LUT4 I0=$abc$44715$auto$simplemap.cc:250:simplemap_eqne$35852[3]_new_ I1=common.pb.spitx_len[5] I2=common.pb.rx_buf_rd_data[5] I3=$abc$44715$auto$simplemap.cc:250:simplemap_eqne$35937[3]_new_ O=$abc$44715$techmap\common.pb.$procmux$9843_Y_new_inv_
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:56"
.param LUT_INIT 0001101110111011
.gate SB_LUT4 I0=$abc$44715$auto$simplemap.cc:250:simplemap_eqne$35427[1]_new_ I1=$abc$44715$new_n2012_ I2=$abc$44715$auto$simplemap.cc:127:simplemap_reduce$23876[1]_new_inv_ I3=$abc$44715$new_n2010_ O=$abc$44715$new_n2009_
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:56"
.param LUT_INIT 0010101010101010
.gate SB_LUT4 I0=common.pb.spitx_ctrl_reply_data[5] I1=$abc$44715$techmap\common.pb.$procmux$10684_CMP_new_ I2=$abc$44715$new_n1490_ I3=common.pb.spitx_ctrl_reply[5] O=$abc$44715$new_n2010_
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:56"
.param LUT_INIT 0000011101110111
.gate SB_LUT4 I0=common.pb.spitx_ctrl_reply_data[13] I1=$abc$44715$new_n1474_ I2=common.pb.spitx_ctrl_reply_data[21] I3=$abc$44715$techmap\common.pb.$procmux$10686_CMP_new_ O=$abc$44715$auto$simplemap.cc:127:simplemap_reduce$23876[1]_new_inv_
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:56"
.param LUT_INIT 0000011101110111
.gate SB_LUT4 I0=common.pb.spitx_ctrl_reply_data[29] I1=$abc$44715$auto$rtlil.cc:1835:ReduceAnd$16071_new_ I2=$abc$44715$techmap\common.pb.$procmux$10683_CMP_new_ I3=common.pb.spitx_crc[5] O=$abc$44715$new_n2012_
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:56"
.param LUT_INIT 0000011101110111
.gate SB_LUT4 I0=$abc$44715$new_n2016_ I1=$abc$44715$auto$simplemap.cc:127:simplemap_reduce$35862[2]_new_inv_ I2=$abc$44715$new_n2021_ I3=$abc$44715$new_n2014_ O=$abc$44715$techmap\common.pb.$2\spi_tx_data[7:0][0]
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:56"
.param LUT_INIT 1110111010101110
.gate SB_LUT4 I0=$abc$44715$new_n1466_ I1=$abc$44715$new_n2015_ I2=common.pb.spitx_len[0] I3=$abc$44715$auto$simplemap.cc:250:simplemap_eqne$35852[3]_new_ O=$abc$44715$new_n2014_
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:56"
.param LUT_INIT 0100010001010100
.gate SB_LUT4 I0=common.pb.rx_buf_rd_data[0] I1=$abc$44715$new_n1806_ I2=$abc$44715$auto$simplemap.cc:250:simplemap_eqne$35852[3]_new_ I3=$abc$44715$techmap\common.pb.$eq$profibus_phy_mod.v:990$6250_Y_new_ O=$abc$44715$new_n2015_
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:56"
.param LUT_INIT 0000000010000000
.gate SB_LUT4 I0=$abc$44715$auto$simplemap.cc:250:simplemap_eqne$35427[1]_new_ I1=$abc$44715$new_n2020_ I2=$abc$44715$new_n2018_ I3=$abc$44715$new_n2017_ O=$abc$44715$new_n2016_
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:56"
.param LUT_INIT 0010101010101010
.gate SB_LUT4 I0=$false I1=$abc$44715$auto$simplemap.cc:168:logic_reduce$19575 I2=$abc$44715$new_n1474_ I3=common.pb.spitx_ctrl_reply_data[8] O=$abc$44715$new_n2017_
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:51"
.param LUT_INIT 0000110011001100
.gate SB_LUT4 I0=$false I1=$abc$44715$new_n2019_ I2=$abc$44715$techmap\common.pb.$procmux$10684_CMP_new_ I3=common.pb.spitx_ctrl_reply_data[0] O=$abc$44715$new_n2018_
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:51"
.param LUT_INIT 0000110011001100
.gate SB_LUT4 I0=common.pb.spitx_ctrl_reply[0] I1=$abc$44715$new_n1490_ I2=common.pb.spitx_crc[0] I3=$abc$44715$techmap\common.pb.$procmux$10683_CMP_new_ O=$abc$44715$new_n2019_
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:56"
.param LUT_INIT 0000011101110111
.gate SB_LUT4 I0=common.pb.spitx_ctrl_reply_data[24] I1=$abc$44715$auto$rtlil.cc:1835:ReduceAnd$16071_new_ I2=$abc$44715$techmap\common.pb.$procmux$10686_CMP_new_ I3=common.pb.spitx_ctrl_reply_data[16] O=$abc$44715$new_n2020_
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:56"
.param LUT_INIT 0000011101110111
.gate SB_LUT4 I0=$false I1=$abc$44715$auto$simplemap.cc:127:simplemap_reduce$35840[0]_new_ I2=common.pb.spitx_bytecount[0] I3=common.pb.rx_buf_rd_data[8] O=$abc$44715$new_n2021_
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:51"
.param LUT_INIT 0011001111110011
.gate SB_LUT4 I0=$abc$44715$new_n2024_ I1=$abc$44715$auto$simplemap.cc:127:simplemap_reduce$35862[2]_new_inv_ I2=$abc$44715$new_n2029_ I3=$abc$44715$new_n2023_ O=$abc$44715$techmap\common.pb.$2\spi_tx_data[7:0][6]
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:56"
.param LUT_INIT 1110111010101110
.gate SB_LUT4 I0=$false I1=common.pb.rx_buf_rd_data[6] I2=$abc$44715$new_n1823_ I3=$abc$44715$auto$simplemap.cc:127:simplemap_reduce$35840[0]_new_ O=$abc$44715$new_n2023_
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:51"
.param LUT_INIT 0000000011000000
.gate SB_LUT4 I0=$abc$44715$auto$simplemap.cc:250:simplemap_eqne$35427[1]_new_ I1=$abc$44715$new_n2028_ I2=$abc$44715$new_n2026_ I3=$abc$44715$new_n2025_ O=$abc$44715$new_n2024_
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:56"
.param LUT_INIT 0010101010101010
.gate SB_LUT4 I0=$false I1=$abc$44715$auto$simplemap.cc:168:logic_reduce$19575 I2=$abc$44715$new_n1474_ I3=common.pb.spitx_ctrl_reply_data[14] O=$abc$44715$new_n2025_
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:51"
.param LUT_INIT 0000110011001100
.gate SB_LUT4 I0=$false I1=$abc$44715$new_n2027_ I2=$abc$44715$new_n1490_ I3=common.pb.spitx_ctrl_reply[6] O=$abc$44715$new_n2026_
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:51"
.param LUT_INIT 0000110011001100
.gate SB_LUT4 I0=common.pb.spitx_ctrl_reply_data[6] I1=$abc$44715$techmap\common.pb.$procmux$10684_CMP_new_ I2=common.pb.spitx_ctrl_reply_data[22] I3=$abc$44715$techmap\common.pb.$procmux$10686_CMP_new_ O=$abc$44715$new_n2027_
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:56"
.param LUT_INIT 0000011101110111
.gate SB_LUT4 I0=common.pb.spitx_ctrl_reply_data[30] I1=$abc$44715$auto$rtlil.cc:1835:ReduceAnd$16071_new_ I2=$abc$44715$techmap\common.pb.$procmux$10683_CMP_new_ I3=common.pb.spitx_crc[6] O=$abc$44715$new_n2028_
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:56"
.param LUT_INIT 0000011101110111
.gate SB_LUT4 I0=$false I1=$abc$44715$auto$simplemap.cc:168:logic_reduce$19575 I2=$abc$44715$techmap\common.pb.$procmux$12826_Y_new_inv_ I3=common.pb.spitx_len[6] O=$abc$44715$new_n2029_
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:51"
.param LUT_INIT 0000110011001100
.gate SB_LUT4 I0=$abc$44715$auto$simplemap.cc:250:simplemap_eqne$35427[1]_new_ I1=$abc$44715$new_n2036_ I2=$abc$44715$new_n2035_ I3=$abc$44715$new_n2032_ O=$abc$44715$new_n2031_
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:56"
.param LUT_INIT 0010101010101010
.gate SB_LUT4 I0=$false I1=$abc$44715$new_n2034_ I2=$abc$44715$new_n1466_ I3=$abc$44715$techmap\common.pb.$xor$parity_func.v:39$5915_Y_new_ O=$abc$44715$new_n2032_
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:51"
.param LUT_INIT 0000110011001100
.gate SB_LUT4 I0=$false I1=$false I2=$abc$44715$common.pb.any_reset_status_new_inv_ I3=$abc$44715$common.pb.new_status_available_new_inv_ O=$abc$44715$techmap\common.pb.$xor$parity_func.v:39$5915_Y_new_
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:46"
.param LUT_INIT 0000000011110000
.gate SB_LUT4 I0=common.pb.spitx_ctrl_reply_data[15] I1=$abc$44715$new_n1474_ I2=$abc$44715$techmap\common.pb.$procmux$10684_CMP_new_ I3=common.pb.spitx_ctrl_reply_data[7] O=$abc$44715$new_n2034_
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:56"
.param LUT_INIT 0000011101110111
.gate SB_LUT4 I0=common.pb.spitx_ctrl_reply_data[31] I1=$abc$44715$auto$rtlil.cc:1835:ReduceAnd$16071_new_ I2=$abc$44715$techmap\common.pb.$procmux$10686_CMP_new_ I3=common.pb.spitx_ctrl_reply_data[23] O=$abc$44715$new_n2035_
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:56"
.param LUT_INIT 0000011101110111
.gate SB_LUT4 I0=common.pb.spitx_ctrl_reply[7] I1=$abc$44715$new_n1490_ I2=common.pb.spitx_crc[7] I3=$abc$44715$techmap\common.pb.$procmux$10683_CMP_new_ O=$abc$44715$new_n2036_
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:56"
.param LUT_INIT 0000011101110111
.gate SB_LUT4 I0=$false I1=$false I2=common.pb.timer_idle[0] I3=$abc$44715$techmap\common.pb.$procmux$9294_Y O=$abc$44715$techmap\common.pb.$procmux$9310_Y[0]
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:46"
.param LUT_INIT 0000111100000000
.gate SB_LUT4 I0=$false I1=$false I2=$abc$44715$techmap\common.pb.$procmux$9294_Y I3=common.pb.timer_idle[1] O=$abc$44715$techmap\common.pb.$procmux$9310_Y[1]
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:46"
.param LUT_INIT 0000000011110000
.gate SB_LUT4 I0=$false I1=$abc$44715$auto$simplemap.cc:168:logic_reduce$20473_new_inv_ I2=common.pb.spi_tx_data[7] I3=common.pb.spi.tx_shiftreg[7] O=$abc$44715$techmap\common.pb.spi.$procmux$14951_Y
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:51"
.param LUT_INIT 1111001111000000
.gate SB_LUT4 I0=$false I1=$abc$44715$auto$simplemap.cc:168:logic_reduce$20473_new_inv_ I2=common.pb.spi_tx_data[0] I3=common.pb.spi.tx_shiftreg[0] O=$abc$44715$techmap\common.pb.spi.$procmux$14931_Y[1]
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:51"
.param LUT_INIT 1111001111000000
.gate SB_LUT4 I0=$false I1=$abc$44715$auto$simplemap.cc:168:logic_reduce$20473_new_inv_ I2=common.pb.spi_tx_data[1] I3=common.pb.spi.tx_shiftreg[1] O=$abc$44715$techmap\common.pb.spi.$procmux$14931_Y[2]
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:51"
.param LUT_INIT 1111001111000000
.gate SB_LUT4 I0=$false I1=$abc$44715$auto$simplemap.cc:168:logic_reduce$20473_new_inv_ I2=common.pb.spi_tx_data[2] I3=common.pb.spi.tx_shiftreg[2] O=$abc$44715$techmap\common.pb.spi.$procmux$14931_Y[3]
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:51"
.param LUT_INIT 1111001111000000
.gate SB_LUT4 I0=$false I1=$abc$44715$auto$simplemap.cc:168:logic_reduce$20473_new_inv_ I2=common.pb.spi_tx_data[3] I3=common.pb.spi.tx_shiftreg[3] O=$abc$44715$techmap\common.pb.spi.$procmux$14931_Y[4]
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:51"
.param LUT_INIT 1111001111000000
.gate SB_LUT4 I0=$false I1=$abc$44715$auto$simplemap.cc:168:logic_reduce$20473_new_inv_ I2=common.pb.spi_tx_data[4] I3=common.pb.spi.tx_shiftreg[4] O=$abc$44715$techmap\common.pb.spi.$procmux$14931_Y[5]
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:51"
.param LUT_INIT 1111001111000000
.gate SB_LUT4 I0=$false I1=$abc$44715$auto$simplemap.cc:168:logic_reduce$20473_new_inv_ I2=common.pb.spi_tx_data[5] I3=common.pb.spi.tx_shiftreg[5] O=$abc$44715$techmap\common.pb.spi.$procmux$14931_Y[6]
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:51"
.param LUT_INIT 1111001111000000
.gate SB_LUT4 I0=$false I1=$abc$44715$auto$simplemap.cc:168:logic_reduce$20473_new_inv_ I2=common.pb.spi_tx_data[6] I3=common.pb.spi.tx_shiftreg[6] O=$abc$44715$techmap\common.pb.spi.$procmux$14931_Y[7]
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:51"
.param LUT_INIT 1111001111000000
.gate SB_LUT4 I0=$false I1=$false I2=common.pb.spi.bit_count[0] I3=$abc$44715$auto$rtlil.cc:1836:ReduceOr$16042 O=$abc$44715$techmap\common.pb.spi.$procmux$14923_Y[0]
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:46"
.param LUT_INIT 0000000000001111
.gate SB_LUT4 I0=$false I1=$false I2=common.pb.spi.bit_count[1] I3=$abc$44715$auto$rtlil.cc:1836:ReduceOr$16042 O=$abc$44715$techmap\common.pb.spi.$procmux$14923_Y[1]
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:46"
.param LUT_INIT 0000000000001111
.gate SB_LUT4 I0=$false I1=$abc$44715$new_n1838_ I2=common.pb.uart_tx_trigger I3=common.pb.uart.tx_trigger_req O=$abc$44715$techmap\common.pb.uart.$procmux$14906_Y
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:51"
.param LUT_INIT 0011001100110000
.gate SB_LUT4 I0=$false I1=$false I2=common.pb.uart_tx_data[0] I3=common.pb.uart.tx_trigger_req O=$abc$44715$techmap\common.pb.uart.$procmux$14896_Y[0]
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:46"
.param LUT_INIT 0000000011110000
.gate SB_LUT4 I0=$false I1=$false I2=common.pb.uart_tx_data[1] I3=common.pb.uart.tx_trigger_req O=$abc$44715$techmap\common.pb.uart.$procmux$14896_Y[1]
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:46"
.param LUT_INIT 0000000011110000
.gate SB_LUT4 I0=$false I1=$false I2=common.pb.uart_tx_data[2] I3=common.pb.uart.tx_trigger_req O=$abc$44715$techmap\common.pb.uart.$procmux$14896_Y[2]
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:46"
.param LUT_INIT 0000000011110000
.gate SB_LUT4 I0=$false I1=$false I2=common.pb.uart_tx_data[3] I3=common.pb.uart.tx_trigger_req O=$abc$44715$techmap\common.pb.uart.$procmux$14896_Y[3]
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:46"
.param LUT_INIT 0000000011110000
.gate SB_LUT4 I0=$false I1=$false I2=common.pb.uart_tx_data[4] I3=common.pb.uart.tx_trigger_req O=$abc$44715$techmap\common.pb.uart.$procmux$14896_Y[4]
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:46"
.param LUT_INIT 0000000011110000
.gate SB_LUT4 I0=$false I1=$false I2=common.pb.uart_tx_data[5] I3=common.pb.uart.tx_trigger_req O=$abc$44715$techmap\common.pb.uart.$procmux$14896_Y[5]
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:46"
.param LUT_INIT 0000000011110000
.gate SB_LUT4 I0=$false I1=$false I2=common.pb.uart_tx_data[6] I3=common.pb.uart.tx_trigger_req O=$abc$44715$techmap\common.pb.uart.$procmux$14896_Y[6]
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:46"
.param LUT_INIT 0000000011110000
.gate SB_LUT4 I0=$false I1=$false I2=common.pb.uart_tx_data[7] I3=common.pb.uart.tx_trigger_req O=$abc$44715$techmap\common.pb.uart.$procmux$14896_Y[7]
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:46"
.param LUT_INIT 0000000011110000
.gate SB_LUT4 I0=$false I1=$abc$44715$new_n2095_ I2=common.pb.uart.tx_mod.sym_count[0] I3=$abc$44715$new_n2090_ O=$abc$44715$techmap\common.pb.uart.tx_mod.$procmux$15610_Y[0]
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:56"
.param LUT_INIT 0000001111110011
.gate SB_LUT4 I0=$false I1=common.pb.uart.tx_mod.symclk.symend I2=common.pb.uart.tx_mod.symclk.setup I3=$abc$44715$new_n1430_ O=$abc$44715$new_n2089_
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:51"
.param LUT_INIT 0000000000001100
.gate SB_LUT4 I0=common.pb.uart.tx_mod.symclk.symend I1=$abc$44715$new_n1430_ I2=$abc$44715$auto$simplemap.cc:250:simplemap_eqne$40309[1]_new_inv_ I3=common.pb.uart.tx_mod.symclk.setup O=$abc$44715$new_n2090_
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:56"
.param LUT_INIT 1000110010101110
.gate SB_LUT4 I0=$abc$44715$new_n2092_ I1=$abc$44715$auto$simplemap.cc:309:simplemap_lut$17004[0]_new_ I2=$abc$44715$auto$simplemap.cc:250:simplemap_eqne$40309[1]_new_inv_ I3=common.pb.uart.tx_mod.symclk.symend O=$abc$44715$techmap\common.pb.uart.tx_mod.$procmux$15610_Y[1]
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:56"
.param LUT_INIT 1111111011101110
.gate SB_LUT4 I0=$false I1=$abc$44715$techmap\common.pb.uart.tx_mod.$logic_or$uart_mod.v:353$9121_Y_new_ I2=common.pb.uart.tx_mod.sym_count[1] I3=$abc$44715$new_n2093_ O=$abc$44715$new_n2092_
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:51"
.param LUT_INIT 0000110011000000
.gate SB_LUT4 I0=$false I1=common.pb.uart.tx_mod.sym_count[0] I2=common.pb.uart.tx_mod.symclk.symend I3=common.pb.uart.tx_mod.symclk.setup O=$abc$44715$new_n2093_
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:51"
.param LUT_INIT 0000000011000000
.gate SB_LUT4 I0=$abc$44715$auto$wreduce.cc:455:run$15914[2] I1=$abc$44715$new_n2095_ I2=common.pb.uart.tx_mod.sym_count[2] I3=$abc$44715$new_n2090_ O=$abc$44715$techmap\common.pb.uart.tx_mod.$procmux$15610_Y[2]
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:56"
.param LUT_INIT 0010001011110010
.gate SB_LUT4 I0=$abc$44715$new_n2089_ I1=$abc$44715$auto$simplemap.cc:127:simplemap_reduce$40245[0]_new_ I2=common.pb.uart.tx_mod.sym_count[0] I3=common.pb.uart.tx_mod.symclk.symend O=$abc$44715$new_n2095_
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:56"
.param LUT_INIT 0001000101010001
.gate SB_LUT4 I0=$false I1=$abc$44715$new_n2099_ I2=common.pb.uart.rx_mod.sym_count[0] I3=$abc$44715$new_n2098_ O=$abc$44715$techmap\common.pb.uart.rx_mod.$procmux$15305_Y[0]
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:51"
.param LUT_INIT 1100110011001111
.gate SB_LUT4 I0=$abc$44715$auto$rtlil.cc:1969:NotGate$44581 I1=common.pb.uart.rx_mod.symclk.symend I2=common.pb.uart.rx_mod.symclk.sample I3=$abc$44715$new_n1849_ O=$abc$44715$new_n2098_
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:56"
.param LUT_INIT 0101010101010001
.gate SB_LUT4 I0=common.pb.uart.rx_mod.sym_count[0] I1=$abc$44715$new_n1849_ I2=common.pb.uart.rx_mod.symclk.sample I3=common.pb.uart.rx_mod.symclk.symend O=$abc$44715$new_n2099_
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:56"
.param LUT_INIT 0010000000100010
.gate SB_LUT4 I0=$false I1=$false I2=$abc$44715$techmap\common.pb.uart.rx_mod.$procmux$15282_Y[1]_new_ I3=$abc$44715$new_n1849_ O=$abc$44715$techmap\common.pb.uart.rx_mod.$procmux$15305_Y[1]
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:46"
.param LUT_INIT 0000000011110000
.gate SB_LUT4 I0=common.pb.uart.rx_mod.sym_count[1] I1=common.pb.uart.rx_mod.symclk.symend I2=common.pb.uart.rx_mod.sym_count[0] I3=common.pb.uart.rx_mod.symclk.sample O=$abc$44715$techmap\common.pb.uart.rx_mod.$procmux$15282_Y[1]_new_
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:56"
.param LUT_INIT 1010101001101010
.gate SB_LUT4 I0=$false I1=$abc$44715$new_n2103_ I2=$abc$44715$auto$wreduce.cc:455:run$15911[2] I3=$abc$44715$new_n2098_ O=$abc$44715$techmap\common.pb.uart.rx_mod.$procmux$15305_Y[2]
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:51"
.param LUT_INIT 1100110011111100
.gate SB_LUT4 I0=common.pb.uart.rx_mod.sym_count[2] I1=$abc$44715$new_n1849_ I2=common.pb.uart.rx_mod.symclk.sample I3=common.pb.uart.rx_mod.symclk.symend O=$abc$44715$new_n2103_
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:56"
.param LUT_INIT 0010000000100010
.gate SB_LUT4 I0=common.pb.uart.rx_mod.sym_count[3] I1=$abc$44715$new_n1849_ I2=common.pb.uart.rx_mod.symclk.sample I3=common.pb.uart.rx_mod.symclk.symend O=$abc$44715$new_n2105_
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:56"
.param LUT_INIT 0010000000100010
.gate SB_LUT4 I0=common.pb.uart.tx_mod.symclk.count[0] I1=$abc$44715$techmap\common.pb.uart.tx_mod.symclk.$eq$uart_mod.v:73$17_Y I2=$abc$44715$new_n2749_ I3=$abc$44715$auto$rtlil.cc:1836:ReduceOr$15993_new_inv_ O=$abc$44715$techmap\common.pb.uart.tx_mod.symclk.$procmux$15655_Y[0]
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:56"
.param LUT_INIT 0101010101010100
.gate SB_LUT4 I0=$abc$44715$new_n2115_ I1=$abc$44715$new_n2114_ I2=$abc$44715$new_n2113_ I3=$abc$44715$new_n2110_ O=$abc$44715$new_n2109_
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:56"
.param LUT_INIT 1000000000000000
.gate SB_LUT4 I0=$abc$44715$new_n2112_ I1=$abc$44715$new_n2111_ I2=$abc$44715$auto$alumacc.cc:474:replace_alu$15981.B_buf[17] I3=common.pb.uart.tx_mod.symclk.count[17] O=$abc$44715$new_n2110_
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:56"
.param LUT_INIT 1000000000001000
.gate SB_LUT4 I0=$abc$44715$auto$alumacc.cc:474:replace_alu$15981.B_buf[18] I1=common.pb.uart.tx_mod.symclk.count[18] I2=common.pb.uart.tx_mod.symclk.count[23] I3=$abc$44715$auto$alumacc.cc:474:replace_alu$15981.B_buf[23] O=$abc$44715$new_n2111_
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:56"
.param LUT_INIT 1101110100001101
.gate SB_LUT4 I0=$abc$44715$auto$alumacc.cc:474:replace_alu$15981.B_buf[3] I1=common.pb.uart.tx_mod.symclk.count[3] I2=$abc$44715$auto$alumacc.cc:474:replace_alu$15981.B_buf[0] I3=common.pb.uart.tx_mod.symclk.count[0] O=$abc$44715$new_n2112_
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:56"
.param LUT_INIT 1001100100001001
.gate SB_LUT4 I0=$abc$44715$auto$alumacc.cc:474:replace_alu$15981.B_buf[9] I1=common.pb.uart.tx_mod.symclk.count[9] I2=$abc$44715$auto$alumacc.cc:474:replace_alu$15981.B_buf[2] I3=common.pb.uart.tx_mod.symclk.count[2] O=$abc$44715$new_n2113_
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:56"
.param LUT_INIT 1001000000001001
.gate SB_LUT4 I0=common.pb.uart.tx_mod.symclk.count[8] I1=$abc$44715$auto$alumacc.cc:474:replace_alu$15981.B_buf[8] I2=$abc$44715$auto$alumacc.cc:474:replace_alu$15981.B_buf[23] I3=common.pb.uart.tx_mod.symclk.count[23] O=$abc$44715$new_n2114_
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:56"
.param LUT_INIT 1101110100001101
.gate SB_LUT4 I0=$abc$44715$auto$alumacc.cc:474:replace_alu$15981.BB[31] I1=$abc$44715$auto$alumacc.cc:474:replace_alu$15981.B_buf[24] I2=common.pb.uart.tx_mod.symclk.count[14] I3=$abc$44715$auto$alumacc.cc:474:replace_alu$15981.B_buf[14] O=$abc$44715$new_n2115_
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:56"
.param LUT_INIT 0010001000000010
.gate SB_LUT4 I0=$abc$44715$auto$alumacc.cc:474:replace_alu$15981.B_buf[12] I1=common.pb.uart.tx_mod.symclk.count[12] I2=$abc$44715$auto$alumacc.cc:474:replace_alu$15981.B_buf[4] I3=common.pb.uart.tx_mod.symclk.count[4] O=$abc$44715$new_n2120_
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:56"
.param LUT_INIT 1001000000001001
.gate SB_LUT4 I0=common.pb.uart.tx_mod.symclk.count[20] I1=$abc$44715$auto$alumacc.cc:474:replace_alu$15981.B_buf[20] I2=$abc$44715$auto$alumacc.cc:474:replace_alu$15981.B_buf[19] I3=common.pb.uart.tx_mod.symclk.count[19] O=$abc$44715$new_n2121_
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:56"
.param LUT_INIT 1001000000001001
.gate SB_LUT4 I0=common.pb.uart.tx_mod.symclk.count[1] I1=common.pb.uart_clks_per_sym[1] I2=common.pb.uart_clks_per_sym[0] I3=$abc$44715$auto$alumacc.cc:491:replace_alu$16009[23] O=$abc$44715$auto$alumacc.cc:490:replace_alu$15982[1]_new_
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:56"
.param LUT_INIT 1010101010010110
.gate SB_LUT4 I0=$abc$44715$new_n2136_ I1=$abc$44715$auto$alumacc.cc:490:replace_alu$15982[11]_new_ I2=$abc$44715$auto$alumacc.cc:474:replace_alu$15981.B_buf[13] I3=common.pb.uart.tx_mod.symclk.count[13] O=$abc$44715$new_n2134_
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:56"
.param LUT_INIT 1000000000001000
.gate SB_LUT4 I0=$false I1=$false I2=$abc$44715$auto$alumacc.cc:474:replace_alu$15981.B_buf[11] I3=common.pb.uart.tx_mod.symclk.count[11] O=$abc$44715$auto$alumacc.cc:490:replace_alu$15982[11]_new_
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:46"
.param LUT_INIT 1111000000001111
.gate SB_LUT4 I0=$abc$44715$auto$alumacc.cc:474:replace_alu$15981.B_buf[21] I1=common.pb.uart.tx_mod.symclk.count[21] I2=$abc$44715$auto$alumacc.cc:474:replace_alu$15981.B_buf[10] I3=common.pb.uart.tx_mod.symclk.count[10] O=$abc$44715$new_n2136_
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:56"
.param LUT_INIT 1001000000001001
.gate SB_LUT4 I0=$false I1=$false I2=$abc$44715$auto$alumacc.cc:474:replace_alu$15981.B_buf[16] I3=common.pb.uart.tx_mod.symclk.count[16] O=$abc$44715$auto$alumacc.cc:490:replace_alu$15982[16]_new_inv_
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:46"
.param LUT_INIT 0000111111110000
.gate SB_LUT4 I0=common.pb.uart.tx_mod.symclk.count[1] I1=common.pb.uart_clks_per_sym[2] I2=common.pb.uart_clks_per_sym[1] I3=$abc$44715$auto$alumacc.cc:491:replace_alu$16009[23] O=$abc$44715$auto$simplemap.cc:250:simplemap_eqne$21955[1]_new_
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:56"
.param LUT_INIT 1010101001101001
.gate SB_LUT4 I0=$abc$44715$auto$simplemap.cc:127:simplemap_reduce$21991[9]_new_inv_ I1=$abc$44715$new_n2149_ I2=$abc$44715$new_n2146_ I3=$abc$44715$new_n2142_ O=$abc$44715$new_n2141_
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:56"
.param LUT_INIT 1000000000000000
.gate SB_LUT4 I0=$abc$44715$new_n2145_ I1=$abc$44715$new_n2143_ I2=common.pb.uart.tx_mod.symclk.count[10] I3=$abc$44715$techmap\common.pb.uart.rx_mod.symclk.$sub$uart_mod.v:78$19_Y[10] O=$abc$44715$new_n2142_
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:56"
.param LUT_INIT 1000100000001000
.gate SB_LUT4 I0=$false I1=$abc$44715$new_n2144_ I2=$abc$44715$techmap\common.pb.uart.rx_mod.symclk.$sub$uart_mod.v:78$19_Y[21] I3=common.pb.uart.tx_mod.symclk.count[21] O=$abc$44715$new_n2143_
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:51"
.param LUT_INIT 1100000000001100
.gate SB_LUT4 I0=common.pb.uart.tx_mod.symclk.count[2] I1=$abc$44715$techmap\common.pb.uart.rx_mod.symclk.$sub$uart_mod.v:78$19_Y[2] I2=$abc$44715$techmap\common.pb.uart.rx_mod.symclk.$sub$uart_mod.v:78$19_Y[4] I3=common.pb.uart.tx_mod.symclk.count[4] O=$abc$44715$new_n2144_
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:56"
.param LUT_INIT 1101110100001101
.gate SB_LUT4 I0=common.pb.uart.tx_mod.symclk.count[8] I1=$abc$44715$techmap\common.pb.uart.rx_mod.symclk.$sub$uart_mod.v:78$19_Y[8] I2=$abc$44715$techmap\common.pb.uart.rx_mod.symclk.$sub$uart_mod.v:78$19_Y[12] I3=common.pb.uart.tx_mod.symclk.count[12] O=$abc$44715$new_n2145_
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:56"
.param LUT_INIT 1101110100001101
.gate SB_LUT4 I0=$abc$44715$new_n2148_ I1=$abc$44715$new_n2147_ I2=$abc$44715$techmap\common.pb.uart.rx_mod.symclk.$sub$uart_mod.v:78$19_Y[15] I3=common.pb.uart.tx_mod.symclk.count[15] O=$abc$44715$new_n2146_
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:56"
.param LUT_INIT 1000000000001000
.gate SB_LUT4 I0=$abc$44715$techmap\common.pb.uart.rx_mod.symclk.$sub$uart_mod.v:78$19_Y[2] I1=common.pb.uart.tx_mod.symclk.count[2] I2=$abc$44715$techmap\common.pb.uart.rx_mod.symclk.$sub$uart_mod.v:78$19_Y[14] I3=common.pb.uart.tx_mod.symclk.count[14] O=$abc$44715$new_n2147_
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:56"
.param LUT_INIT 1101110100001101
.gate SB_LUT4 I0=$abc$44715$techmap\common.pb.uart.rx_mod.symclk.$sub$uart_mod.v:78$19_Y[9] I1=common.pb.uart.tx_mod.symclk.count[9] I2=$abc$44715$techmap\common.pb.uart.rx_mod.symclk.$sub$uart_mod.v:78$19_Y[3] I3=common.pb.uart.tx_mod.symclk.count[3] O=$abc$44715$new_n2148_
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:56"
.param LUT_INIT 1001000000001001
.gate SB_LUT4 I0=$abc$44715$techmap\common.pb.uart.rx_mod.symclk.$sub$uart_mod.v:78$19_Y[13] I1=common.pb.uart.tx_mod.symclk.count[13] I2=$abc$44715$techmap\common.pb.uart.rx_mod.symclk.$sub$uart_mod.v:78$19_Y[0] I3=common.pb.uart.tx_mod.symclk.count[0] O=$abc$44715$new_n2149_
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:56"
.param LUT_INIT 1001000000001001
.gate SB_LUT4 I0=$abc$44715$techmap\common.pb.uart.rx_mod.symclk.$sub$uart_mod.v:78$19_Y[19] I1=common.pb.uart.tx_mod.symclk.count[19] I2=$abc$44715$techmap\common.pb.uart.rx_mod.symclk.$sub$uart_mod.v:78$19_Y[18] I3=common.pb.uart.tx_mod.symclk.count[18] O=$abc$44715$auto$simplemap.cc:127:simplemap_reduce$21991[9]_new_inv_
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:56"
.param LUT_INIT 1001000000001001
.gate SB_LUT4 I0=$false I1=$false I2=common.pb.uart.tx_mod.symclk.count[12] I3=$abc$44715$techmap\common.pb.uart.rx_mod.symclk.$sub$uart_mod.v:78$19_Y[12] O=$abc$44715$new_n2159_
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:46"
.param LUT_INIT 0000000011110000
.gate SB_LUT4 I0=$false I1=$abc$44715$new_n2165_ I2=common.pb.uart.tx_mod.symclk.count[14] I3=$abc$44715$techmap\common.pb.uart.rx_mod.symclk.$sub$uart_mod.v:78$19_Y[14] O=$abc$44715$new_n2164_
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:51"
.param LUT_INIT 1100110000001100
.gate SB_LUT4 I0=common.pb.uart.tx_mod.symclk.count[4] I1=$abc$44715$techmap\common.pb.uart.rx_mod.symclk.$sub$uart_mod.v:78$19_Y[4] I2=$abc$44715$techmap\common.pb.uart.rx_mod.symclk.$sub$uart_mod.v:78$19_Y[8] I3=common.pb.uart.tx_mod.symclk.count[8] O=$abc$44715$new_n2165_
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:56"
.param LUT_INIT 1101110100001101
.gate SB_LUT4 I0=common.pb.uart.tx_mod.symclk.count[1] I1=common.pb.uart.tx_mod.symclk.count[0] I2=$abc$44715$new_n2749_ I3=$abc$44715$auto$rtlil.cc:1836:ReduceOr$15993_new_inv_ O=$abc$44715$techmap\common.pb.uart.tx_mod.symclk.$procmux$15655_Y[1]
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:56"
.param LUT_INIT 0110011001100000
.gate SB_LUT4 I0=$abc$44715$auto$wreduce.cc:455:run$15915[2] I1=$abc$44715$techmap\common.pb.uart.tx_mod.symclk.$eq$uart_mod.v:73$17_Y I2=$abc$44715$new_n2749_ I3=$abc$44715$auto$rtlil.cc:1836:ReduceOr$15993_new_inv_ O=$abc$44715$techmap\common.pb.uart.tx_mod.symclk.$procmux$15655_Y[2]
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:56"
.param LUT_INIT 1010101010101000
.gate SB_LUT4 I0=$abc$44715$auto$wreduce.cc:455:run$15915[3] I1=$abc$44715$techmap\common.pb.uart.tx_mod.symclk.$eq$uart_mod.v:73$17_Y I2=$abc$44715$new_n2749_ I3=$abc$44715$auto$rtlil.cc:1836:ReduceOr$15993_new_inv_ O=$abc$44715$techmap\common.pb.uart.tx_mod.symclk.$procmux$15655_Y[3]
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:56"
.param LUT_INIT 1010101010101000
.gate SB_LUT4 I0=$abc$44715$auto$wreduce.cc:455:run$15915[4] I1=$abc$44715$techmap\common.pb.uart.tx_mod.symclk.$eq$uart_mod.v:73$17_Y I2=$abc$44715$new_n2749_ I3=$abc$44715$auto$rtlil.cc:1836:ReduceOr$15993_new_inv_ O=$abc$44715$techmap\common.pb.uart.tx_mod.symclk.$procmux$15655_Y[4]
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:56"
.param LUT_INIT 1010101010101000
.gate SB_LUT4 I0=$abc$44715$auto$wreduce.cc:455:run$15915[5] I1=$abc$44715$techmap\common.pb.uart.tx_mod.symclk.$eq$uart_mod.v:73$17_Y I2=$abc$44715$new_n2749_ I3=$abc$44715$auto$rtlil.cc:1836:ReduceOr$15993_new_inv_ O=$abc$44715$techmap\common.pb.uart.tx_mod.symclk.$procmux$15655_Y[5]
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:56"
.param LUT_INIT 1010101010101000
.gate SB_LUT4 I0=$abc$44715$auto$wreduce.cc:455:run$15915[6] I1=$abc$44715$techmap\common.pb.uart.tx_mod.symclk.$eq$uart_mod.v:73$17_Y I2=$abc$44715$new_n2749_ I3=$abc$44715$auto$rtlil.cc:1836:ReduceOr$15993_new_inv_ O=$abc$44715$techmap\common.pb.uart.tx_mod.symclk.$procmux$15655_Y[6]
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:56"
.param LUT_INIT 1010101010101000
.gate SB_LUT4 I0=$abc$44715$auto$wreduce.cc:455:run$15915[7] I1=$abc$44715$techmap\common.pb.uart.tx_mod.symclk.$eq$uart_mod.v:73$17_Y I2=$abc$44715$new_n2749_ I3=$abc$44715$auto$rtlil.cc:1836:ReduceOr$15993_new_inv_ O=$abc$44715$techmap\common.pb.uart.tx_mod.symclk.$procmux$15655_Y[7]
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:56"
.param LUT_INIT 1010101010101000
.gate SB_LUT4 I0=$abc$44715$auto$wreduce.cc:455:run$15915[8] I1=$abc$44715$techmap\common.pb.uart.tx_mod.symclk.$eq$uart_mod.v:73$17_Y I2=$abc$44715$new_n2749_ I3=$abc$44715$auto$rtlil.cc:1836:ReduceOr$15993_new_inv_ O=$abc$44715$techmap\common.pb.uart.tx_mod.symclk.$procmux$15655_Y[8]
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:56"
.param LUT_INIT 1010101010101000
.gate SB_LUT4 I0=$abc$44715$auto$wreduce.cc:455:run$15915[9] I1=$abc$44715$techmap\common.pb.uart.tx_mod.symclk.$eq$uart_mod.v:73$17_Y I2=$abc$44715$new_n2749_ I3=$abc$44715$auto$rtlil.cc:1836:ReduceOr$15993_new_inv_ O=$abc$44715$techmap\common.pb.uart.tx_mod.symclk.$procmux$15655_Y[9]
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:56"
.param LUT_INIT 1010101010101000
.gate SB_LUT4 I0=$abc$44715$auto$wreduce.cc:455:run$15915[10] I1=$abc$44715$techmap\common.pb.uart.tx_mod.symclk.$eq$uart_mod.v:73$17_Y I2=$abc$44715$new_n2749_ I3=$abc$44715$auto$rtlil.cc:1836:ReduceOr$15993_new_inv_ O=$abc$44715$techmap\common.pb.uart.tx_mod.symclk.$procmux$15655_Y[10]
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:56"
.param LUT_INIT 1010101010101000
.gate SB_LUT4 I0=$abc$44715$auto$wreduce.cc:455:run$15915[11] I1=$abc$44715$techmap\common.pb.uart.tx_mod.symclk.$eq$uart_mod.v:73$17_Y I2=$abc$44715$new_n2749_ I3=$abc$44715$auto$rtlil.cc:1836:ReduceOr$15993_new_inv_ O=$abc$44715$techmap\common.pb.uart.tx_mod.symclk.$procmux$15655_Y[11]
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:56"
.param LUT_INIT 1010101010101000
.gate SB_LUT4 I0=$abc$44715$auto$wreduce.cc:455:run$15915[12] I1=$abc$44715$techmap\common.pb.uart.tx_mod.symclk.$eq$uart_mod.v:73$17_Y I2=$abc$44715$new_n2749_ I3=$abc$44715$auto$rtlil.cc:1836:ReduceOr$15993_new_inv_ O=$abc$44715$techmap\common.pb.uart.tx_mod.symclk.$procmux$15655_Y[12]
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:56"
.param LUT_INIT 1010101010101000
.gate SB_LUT4 I0=$abc$44715$auto$wreduce.cc:455:run$15915[13] I1=$abc$44715$techmap\common.pb.uart.tx_mod.symclk.$eq$uart_mod.v:73$17_Y I2=$abc$44715$new_n2749_ I3=$abc$44715$auto$rtlil.cc:1836:ReduceOr$15993_new_inv_ O=$abc$44715$techmap\common.pb.uart.tx_mod.symclk.$procmux$15655_Y[13]
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:56"
.param LUT_INIT 1010101010101000
.gate SB_LUT4 I0=$abc$44715$auto$wreduce.cc:455:run$15915[14] I1=$abc$44715$techmap\common.pb.uart.tx_mod.symclk.$eq$uart_mod.v:73$17_Y I2=$abc$44715$new_n2749_ I3=$abc$44715$auto$rtlil.cc:1836:ReduceOr$15993_new_inv_ O=$abc$44715$techmap\common.pb.uart.tx_mod.symclk.$procmux$15655_Y[14]
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:56"
.param LUT_INIT 1010101010101000
.gate SB_LUT4 I0=$abc$44715$auto$wreduce.cc:455:run$15915[15] I1=$abc$44715$techmap\common.pb.uart.tx_mod.symclk.$eq$uart_mod.v:73$17_Y I2=$abc$44715$new_n2749_ I3=$abc$44715$auto$rtlil.cc:1836:ReduceOr$15993_new_inv_ O=$abc$44715$techmap\common.pb.uart.tx_mod.symclk.$procmux$15655_Y[15]
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:56"
.param LUT_INIT 1010101010101000
.gate SB_LUT4 I0=$abc$44715$auto$wreduce.cc:455:run$15915[16] I1=$abc$44715$techmap\common.pb.uart.tx_mod.symclk.$eq$uart_mod.v:73$17_Y I2=$abc$44715$new_n2749_ I3=$abc$44715$auto$rtlil.cc:1836:ReduceOr$15993_new_inv_ O=$abc$44715$techmap\common.pb.uart.tx_mod.symclk.$procmux$15655_Y[16]
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:56"
.param LUT_INIT 1010101010101000
.gate SB_LUT4 I0=$abc$44715$auto$wreduce.cc:455:run$15915[17] I1=$abc$44715$techmap\common.pb.uart.tx_mod.symclk.$eq$uart_mod.v:73$17_Y I2=$abc$44715$new_n2749_ I3=$abc$44715$auto$rtlil.cc:1836:ReduceOr$15993_new_inv_ O=$abc$44715$techmap\common.pb.uart.tx_mod.symclk.$procmux$15655_Y[17]
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:56"
.param LUT_INIT 1010101010101000
.gate SB_LUT4 I0=$abc$44715$auto$wreduce.cc:455:run$15915[18] I1=$abc$44715$techmap\common.pb.uart.tx_mod.symclk.$eq$uart_mod.v:73$17_Y I2=$abc$44715$new_n2749_ I3=$abc$44715$auto$rtlil.cc:1836:ReduceOr$15993_new_inv_ O=$abc$44715$techmap\common.pb.uart.tx_mod.symclk.$procmux$15655_Y[18]
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:56"
.param LUT_INIT 1010101010101000
.gate SB_LUT4 I0=$abc$44715$auto$wreduce.cc:455:run$15915[19] I1=$abc$44715$techmap\common.pb.uart.tx_mod.symclk.$eq$uart_mod.v:73$17_Y I2=$abc$44715$new_n2749_ I3=$abc$44715$auto$rtlil.cc:1836:ReduceOr$15993_new_inv_ O=$abc$44715$techmap\common.pb.uart.tx_mod.symclk.$procmux$15655_Y[19]
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:56"
.param LUT_INIT 1010101010101000
.gate SB_LUT4 I0=$abc$44715$auto$wreduce.cc:455:run$15915[20] I1=$abc$44715$techmap\common.pb.uart.tx_mod.symclk.$eq$uart_mod.v:73$17_Y I2=$abc$44715$new_n2749_ I3=$abc$44715$auto$rtlil.cc:1836:ReduceOr$15993_new_inv_ O=$abc$44715$techmap\common.pb.uart.tx_mod.symclk.$procmux$15655_Y[20]
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:56"
.param LUT_INIT 1010101010101000
.gate SB_LUT4 I0=$abc$44715$auto$wreduce.cc:455:run$15915[21] I1=$abc$44715$techmap\common.pb.uart.tx_mod.symclk.$eq$uart_mod.v:73$17_Y I2=$abc$44715$new_n2749_ I3=$abc$44715$auto$rtlil.cc:1836:ReduceOr$15993_new_inv_ O=$abc$44715$techmap\common.pb.uart.tx_mod.symclk.$procmux$15655_Y[21]
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:56"
.param LUT_INIT 1010101010101000
.gate SB_LUT4 I0=$abc$44715$auto$wreduce.cc:455:run$15915[22] I1=$abc$44715$techmap\common.pb.uart.tx_mod.symclk.$eq$uart_mod.v:73$17_Y I2=$abc$44715$new_n2749_ I3=$abc$44715$auto$rtlil.cc:1836:ReduceOr$15993_new_inv_ O=$abc$44715$techmap\common.pb.uart.tx_mod.symclk.$procmux$15655_Y[22]
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:56"
.param LUT_INIT 1010101010101000
.gate SB_LUT4 I0=$abc$44715$auto$wreduce.cc:455:run$15915[23] I1=$abc$44715$techmap\common.pb.uart.tx_mod.symclk.$eq$uart_mod.v:73$17_Y I2=$abc$44715$new_n2749_ I3=$abc$44715$auto$rtlil.cc:1836:ReduceOr$15993_new_inv_ O=$abc$44715$techmap\common.pb.uart.tx_mod.symclk.$procmux$15655_Y[23]
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:56"
.param LUT_INIT 1010101010101000
.gate SB_LUT4 I0=$false I1=$abc$44715$techmap\common.pb.uart.tx_mod.symclk.$eq$uart_mod.v:73$17_Y I2=$abc$44715$new_n2749_ I3=$abc$44715$auto$rtlil.cc:1836:ReduceOr$15993_new_inv_ O=$abc$44715$techmap\common.pb.uart.tx_mod.symclk.$procmux$15622_Y
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:51"
.param LUT_INIT 0000000000000011
.gate SB_LUT4 I0=common.pb.uart.rx_mod.symclk.count[0] I1=$abc$44715$auto$simplemap.cc:168:logic_reduce$22268_new_inv_ I2=$abc$44715$new_n2753_ I3=$abc$44715$auto$rtlil.cc:1836:ReduceOr$16006_new_inv_ O=$abc$44715$techmap\common.pb.uart.rx_mod.symclk.$procmux$15655_Y[0]
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:56"
.param LUT_INIT 0101010101010100
.gate SB_LUT4 I0=$abc$44715$auto$alumacc.cc:491:replace_alu$15996[31] I1=common.pb.uart.rx_mod.symclk.count[1] I2=$abc$44715$auto$alumacc.cc:474:replace_alu$15981.BB[1] I3=$abc$44715$new_n2733_ O=$abc$44715$auto$rtlil.cc:1836:ReduceOr$16006_new_inv_
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:56"
.param LUT_INIT 0100000101010101
.gate SB_LUT4 I0=$false I1=common.pb.uart_clks_per_sym[1] I2=common.pb.uart_clks_per_sym[0] I3=$abc$44715$auto$alumacc.cc:491:replace_alu$16009[23] O=$abc$44715$auto$alumacc.cc:474:replace_alu$15981.BB[1]
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:51"
.param LUT_INIT 0000000000111100
.gate SB_LUT4 I0=$abc$44715$auto$alumacc.cc:474:replace_alu$15981.B_buf[15] I1=common.pb.uart.rx_mod.symclk.count[15] I2=common.pb.uart.rx_mod.symclk.count[21] I3=$abc$44715$auto$alumacc.cc:474:replace_alu$15981.B_buf[21] O=$abc$44715$new_n2200_
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:56"
.param LUT_INIT 1101110100001101
.gate SB_LUT4 I0=$abc$44715$auto$alumacc.cc:474:replace_alu$15981.B_buf[9] I1=common.pb.uart.rx_mod.symclk.count[9] I2=common.pb.uart.rx_mod.symclk.count[22] I3=$abc$44715$auto$alumacc.cc:474:replace_alu$15981.B_buf[22] O=$abc$44715$new_n2204_
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:56"
.param LUT_INIT 1101110100001101
.gate SB_LUT4 I0=common.pb.uart.rx_mod.symclk.count[11] I1=$abc$44715$auto$alumacc.cc:474:replace_alu$15981.B_buf[11] I2=common.pb.uart.rx_mod.symclk.count[12] I3=$abc$44715$auto$alumacc.cc:474:replace_alu$15981.B_buf[12] O=$abc$44715$new_n2205_
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:56"
.param LUT_INIT 1101110100001101
.gate SB_LUT4 I0=common.pb.uart.rx_mod.symclk.count[9] I1=$abc$44715$auto$alumacc.cc:474:replace_alu$15981.B_buf[9] I2=$abc$44715$auto$alumacc.cc:474:replace_alu$15981.B_buf[21] I3=common.pb.uart.rx_mod.symclk.count[21] O=$abc$44715$new_n2206_
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:56"
.param LUT_INIT 1101110100001101
.gate SB_LUT4 I0=$abc$44715$auto$alumacc.cc:474:replace_alu$15981.B_buf[5] I1=common.pb.uart.rx_mod.symclk.count[5] I2=$abc$44715$auto$alumacc.cc:474:replace_alu$15981.B_buf[12] I3=common.pb.uart.rx_mod.symclk.count[12] O=$abc$44715$new_n2210_
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:56"
.param LUT_INIT 1101110100001101
.gate SB_LUT4 I0=$false I1=$false I2=$abc$44715$auto$alumacc.cc:474:replace_alu$15981.B_buf[16] I3=common.pb.uart.rx_mod.symclk.count[16] O=$abc$44715$auto$alumacc.cc:490:replace_alu$15995[16]_new_
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:46"
.param LUT_INIT 1111000000001111
.gate SB_LUT4 I0=$false I1=$false I2=$abc$44715$auto$alumacc.cc:474:replace_alu$15981.B_buf[19] I3=common.pb.uart.rx_mod.symclk.count[19] O=$abc$44715$auto$alumacc.cc:490:replace_alu$15995[19]_new_
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:46"
.param LUT_INIT 1111000000001111
.gate SB_LUT4 I0=$abc$44715$auto$alumacc.cc:474:replace_alu$15981.B_buf[17] I1=common.pb.uart.rx_mod.symclk.count[17] I2=$abc$44715$auto$alumacc.cc:474:replace_alu$15981.B_buf[4] I3=common.pb.uart.rx_mod.symclk.count[4] O=$abc$44715$new_n2217_
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:56"
.param LUT_INIT 1001000000001001
.gate SB_LUT4 I0=$abc$44715$auto$alumacc.cc:474:replace_alu$15981.B_buf[20] I1=common.pb.uart.rx_mod.symclk.count[20] I2=$abc$44715$auto$alumacc.cc:474:replace_alu$15981.B_buf[2] I3=common.pb.uart.rx_mod.symclk.count[2] O=$abc$44715$new_n2218_
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:56"
.param LUT_INIT 1001000000001001
.gate SB_LUT4 I0=common.pb.uart.rx_mod.symclk.count[1] I1=common.pb.uart_clks_per_sym[2] I2=common.pb.uart_clks_per_sym[1] I3=$abc$44715$auto$alumacc.cc:491:replace_alu$16009[23] O=$abc$44715$auto$simplemap.cc:250:simplemap_eqne$22165[1]_new_
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:56"
.param LUT_INIT 1010101001101001
.gate SB_LUT4 I0=common.pb.uart.rx_mod.symclk.count[8] I1=$abc$44715$techmap\common.pb.uart.rx_mod.symclk.$sub$uart_mod.v:78$19_Y[8] I2=common.pb.uart.rx_mod.symclk.count[17] I3=$abc$44715$techmap\common.pb.uart.rx_mod.symclk.$sub$uart_mod.v:78$19_Y[17] O=$abc$44715$new_n2232_
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:56"
.param LUT_INIT 1101110100001101
.gate SB_LUT4 I0=$false I1=$abc$44715$new_n2237_ I2=$abc$44715$techmap\common.pb.uart.rx_mod.symclk.$sub$uart_mod.v:78$19_Y[6] I3=common.pb.uart.rx_mod.symclk.count[6] O=$abc$44715$new_n2236_
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:51"
.param LUT_INIT 1100000000001100
.gate SB_LUT4 I0=$abc$44715$techmap\common.pb.uart.rx_mod.symclk.$sub$uart_mod.v:78$19_Y[8] I1=common.pb.uart.rx_mod.symclk.count[8] I2=$abc$44715$techmap\common.pb.uart.rx_mod.symclk.$sub$uart_mod.v:78$19_Y[11] I3=common.pb.uart.rx_mod.symclk.count[11] O=$abc$44715$new_n2237_
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:56"
.param LUT_INIT 1101110100001101
.gate SB_LUT4 I0=$abc$44715$techmap\common.pb.uart.rx_mod.symclk.$sub$uart_mod.v:78$19_Y[5] I1=common.pb.uart.rx_mod.symclk.count[5] I2=common.pb.uart.rx_mod.symclk.count[13] I3=$abc$44715$techmap\common.pb.uart.rx_mod.symclk.$sub$uart_mod.v:78$19_Y[13] O=$abc$44715$new_n2241_
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:56"
.param LUT_INIT 1101110100001101
.gate SB_LUT4 I0=$abc$44715$techmap\common.pb.uart.rx_mod.symclk.$sub$uart_mod.v:78$19_Y[13] I1=common.pb.uart.rx_mod.symclk.count[13] I2=$abc$44715$techmap\common.pb.uart.rx_mod.symclk.$sub$uart_mod.v:78$19_Y[21] I3=common.pb.uart.rx_mod.symclk.count[21] O=$abc$44715$new_n2242_
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:56"
.param LUT_INIT 1101110100001101
.gate SB_LUT4 I0=$abc$44715$new_n2248_ I1=$abc$44715$techmap\common.pb.uart.rx_mod.symclk.$sub$uart_mod.v:78$19_Y[15] I2=common.pb.uart.rx_mod.symclk.count[15] I3=$abc$44715$auto$simplemap.cc:250:simplemap_eqne$22165[2]_new_ O=$abc$44715$new_n2246_
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:56"
.param LUT_INIT 0000000010000010
.gate SB_LUT4 I0=$false I1=$false I2=$abc$44715$techmap\common.pb.uart.rx_mod.symclk.$sub$uart_mod.v:78$19_Y[2] I3=common.pb.uart.rx_mod.symclk.count[2] O=$abc$44715$auto$simplemap.cc:250:simplemap_eqne$22165[2]_new_
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:46"
.param LUT_INIT 0000111111110000
.gate SB_LUT4 I0=$abc$44715$techmap\common.pb.uart.rx_mod.symclk.$sub$uart_mod.v:78$19_Y[23] I1=common.pb.uart.rx_mod.symclk.count[23] I2=$abc$44715$techmap\common.pb.uart.rx_mod.symclk.$sub$uart_mod.v:78$19_Y[10] I3=common.pb.uart.rx_mod.symclk.count[10] O=$abc$44715$new_n2248_
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:56"
.param LUT_INIT 1001000000001001
.gate SB_LUT4 I0=common.pb.uart.rx_mod.symclk.count[5] I1=$abc$44715$techmap\common.pb.uart.rx_mod.symclk.$sub$uart_mod.v:78$19_Y[5] I2=common.pb.uart.rx_mod.symclk.count[9] I3=$abc$44715$techmap\common.pb.uart.rx_mod.symclk.$sub$uart_mod.v:78$19_Y[9] O=$abc$44715$new_n2252_
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:56"
.param LUT_INIT 1101110100001101
.gate SB_LUT4 I0=$false I1=$abc$44715$auto$simplemap.cc:168:logic_reduce$22255[0]_new_inv_ I2=$abc$44715$auto$simplemap.cc:168:logic_reduce$22255[1]_new_inv_ I3=$abc$44715$new_n2254_ O=$abc$44715$auto$simplemap.cc:168:logic_reduce$22268_new_inv_
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:51"
.param LUT_INIT 1100000000000000
.gate SB_LUT4 I0=$abc$44715$auto$simplemap.cc:168:logic_reduce$22255[4]_new_inv_ I1=$abc$44715$auto$simplemap.cc:168:logic_reduce$22255[5]_new_inv_ I2=$abc$44715$auto$simplemap.cc:168:logic_reduce$22255[2]_new_inv_ I3=$abc$44715$auto$simplemap.cc:168:logic_reduce$22255[3]_new_inv_ O=$abc$44715$new_n2254_
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:56"
.param LUT_INIT 1000000000000000
.gate SB_LUT4 I0=common.pb.uart.rx_mod.symclk.count[15] I1=common.pb.uart.rx_mod.symclk.count[14] I2=common.pb.uart.rx_mod.symclk.count[13] I3=common.pb.uart.rx_mod.symclk.count[12] O=$abc$44715$auto$simplemap.cc:168:logic_reduce$22255[3]_new_inv_
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:56"
.param LUT_INIT 0000000000000001
.gate SB_LUT4 I0=common.pb.uart.rx_mod.symclk.count[11] I1=common.pb.uart.rx_mod.symclk.count[10] I2=common.pb.uart.rx_mod.symclk.count[9] I3=common.pb.uart.rx_mod.symclk.count[8] O=$abc$44715$auto$simplemap.cc:168:logic_reduce$22255[2]_new_inv_
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:56"
.param LUT_INIT 0000000000000001
.gate SB_LUT4 I0=common.pb.uart.rx_mod.symclk.count[23] I1=common.pb.uart.rx_mod.symclk.count[22] I2=common.pb.uart.rx_mod.symclk.count[21] I3=common.pb.uart.rx_mod.symclk.count[20] O=$abc$44715$auto$simplemap.cc:168:logic_reduce$22255[5]_new_inv_
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:56"
.param LUT_INIT 0000000000000001
.gate SB_LUT4 I0=common.pb.uart.rx_mod.symclk.count[19] I1=common.pb.uart.rx_mod.symclk.count[18] I2=common.pb.uart.rx_mod.symclk.count[17] I3=common.pb.uart.rx_mod.symclk.count[16] O=$abc$44715$auto$simplemap.cc:168:logic_reduce$22255[4]_new_inv_
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:56"
.param LUT_INIT 0000000000000001
.gate SB_LUT4 I0=common.pb.uart.rx_mod.symclk.count[7] I1=common.pb.uart.rx_mod.symclk.count[6] I2=common.pb.uart.rx_mod.symclk.count[5] I3=common.pb.uart.rx_mod.symclk.count[4] O=$abc$44715$auto$simplemap.cc:168:logic_reduce$22255[1]_new_inv_
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:56"
.param LUT_INIT 0000000000000001
.gate SB_LUT4 I0=common.pb.uart.rx_mod.symclk.count[3] I1=common.pb.uart.rx_mod.symclk.count[2] I2=common.pb.uart.rx_mod.symclk.count[1] I3=common.pb.uart.rx_mod.symclk.count[0] O=$abc$44715$auto$simplemap.cc:168:logic_reduce$22255[0]_new_inv_
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:56"
.param LUT_INIT 0000000000000001
.gate SB_LUT4 I0=common.pb.uart.rx_mod.symclk.count[1] I1=common.pb.uart.rx_mod.symclk.count[0] I2=$abc$44715$new_n2753_ I3=$abc$44715$auto$rtlil.cc:1836:ReduceOr$16006_new_inv_ O=$abc$44715$techmap\common.pb.uart.rx_mod.symclk.$procmux$15655_Y[1]
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:56"
.param LUT_INIT 0110011001100000
.gate SB_LUT4 I0=$abc$44715$auto$wreduce.cc:455:run$15912[2] I1=$abc$44715$auto$simplemap.cc:168:logic_reduce$22268_new_inv_ I2=$abc$44715$new_n2753_ I3=$abc$44715$auto$rtlil.cc:1836:ReduceOr$16006_new_inv_ O=$abc$44715$techmap\common.pb.uart.rx_mod.symclk.$procmux$15655_Y[2]
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:56"
.param LUT_INIT 1010101010101000
.gate SB_LUT4 I0=$abc$44715$auto$wreduce.cc:455:run$15912[3] I1=$abc$44715$auto$simplemap.cc:168:logic_reduce$22268_new_inv_ I2=$abc$44715$new_n2753_ I3=$abc$44715$auto$rtlil.cc:1836:ReduceOr$16006_new_inv_ O=$abc$44715$techmap\common.pb.uart.rx_mod.symclk.$procmux$15655_Y[3]
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:56"
.param LUT_INIT 1010101010101000
.gate SB_LUT4 I0=$abc$44715$auto$wreduce.cc:455:run$15912[4] I1=$abc$44715$auto$simplemap.cc:168:logic_reduce$22268_new_inv_ I2=$abc$44715$new_n2753_ I3=$abc$44715$auto$rtlil.cc:1836:ReduceOr$16006_new_inv_ O=$abc$44715$techmap\common.pb.uart.rx_mod.symclk.$procmux$15655_Y[4]
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:56"
.param LUT_INIT 1010101010101000
.gate SB_LUT4 I0=$abc$44715$auto$wreduce.cc:455:run$15912[5] I1=$abc$44715$auto$simplemap.cc:168:logic_reduce$22268_new_inv_ I2=$abc$44715$new_n2753_ I3=$abc$44715$auto$rtlil.cc:1836:ReduceOr$16006_new_inv_ O=$abc$44715$techmap\common.pb.uart.rx_mod.symclk.$procmux$15655_Y[5]
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:56"
.param LUT_INIT 1010101010101000
.gate SB_LUT4 I0=$abc$44715$auto$wreduce.cc:455:run$15912[6] I1=$abc$44715$auto$simplemap.cc:168:logic_reduce$22268_new_inv_ I2=$abc$44715$new_n2753_ I3=$abc$44715$auto$rtlil.cc:1836:ReduceOr$16006_new_inv_ O=$abc$44715$techmap\common.pb.uart.rx_mod.symclk.$procmux$15655_Y[6]
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:56"
.param LUT_INIT 1010101010101000
.gate SB_LUT4 I0=$abc$44715$auto$wreduce.cc:455:run$15912[7] I1=$abc$44715$auto$simplemap.cc:168:logic_reduce$22268_new_inv_ I2=$abc$44715$new_n2753_ I3=$abc$44715$auto$rtlil.cc:1836:ReduceOr$16006_new_inv_ O=$abc$44715$techmap\common.pb.uart.rx_mod.symclk.$procmux$15655_Y[7]
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:56"
.param LUT_INIT 1010101010101000
.gate SB_LUT4 I0=$abc$44715$auto$wreduce.cc:455:run$15912[8] I1=$abc$44715$auto$simplemap.cc:168:logic_reduce$22268_new_inv_ I2=$abc$44715$new_n2753_ I3=$abc$44715$auto$rtlil.cc:1836:ReduceOr$16006_new_inv_ O=$abc$44715$techmap\common.pb.uart.rx_mod.symclk.$procmux$15655_Y[8]
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:56"
.param LUT_INIT 1010101010101000
.gate SB_LUT4 I0=$abc$44715$auto$wreduce.cc:455:run$15912[9] I1=$abc$44715$auto$simplemap.cc:168:logic_reduce$22268_new_inv_ I2=$abc$44715$new_n2753_ I3=$abc$44715$auto$rtlil.cc:1836:ReduceOr$16006_new_inv_ O=$abc$44715$techmap\common.pb.uart.rx_mod.symclk.$procmux$15655_Y[9]
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:56"
.param LUT_INIT 1010101010101000
.gate SB_LUT4 I0=$abc$44715$auto$wreduce.cc:455:run$15912[10] I1=$abc$44715$auto$simplemap.cc:168:logic_reduce$22268_new_inv_ I2=$abc$44715$new_n2753_ I3=$abc$44715$auto$rtlil.cc:1836:ReduceOr$16006_new_inv_ O=$abc$44715$techmap\common.pb.uart.rx_mod.symclk.$procmux$15655_Y[10]
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:56"
.param LUT_INIT 1010101010101000
.gate SB_LUT4 I0=$abc$44715$auto$wreduce.cc:455:run$15912[11] I1=$abc$44715$auto$simplemap.cc:168:logic_reduce$22268_new_inv_ I2=$abc$44715$new_n2753_ I3=$abc$44715$auto$rtlil.cc:1836:ReduceOr$16006_new_inv_ O=$abc$44715$techmap\common.pb.uart.rx_mod.symclk.$procmux$15655_Y[11]
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:56"
.param LUT_INIT 1010101010101000
.gate SB_LUT4 I0=$abc$44715$auto$wreduce.cc:455:run$15912[12] I1=$abc$44715$auto$simplemap.cc:168:logic_reduce$22268_new_inv_ I2=$abc$44715$new_n2753_ I3=$abc$44715$auto$rtlil.cc:1836:ReduceOr$16006_new_inv_ O=$abc$44715$techmap\common.pb.uart.rx_mod.symclk.$procmux$15655_Y[12]
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:56"
.param LUT_INIT 1010101010101000
.gate SB_LUT4 I0=$abc$44715$auto$wreduce.cc:455:run$15912[13] I1=$abc$44715$auto$simplemap.cc:168:logic_reduce$22268_new_inv_ I2=$abc$44715$new_n2753_ I3=$abc$44715$auto$rtlil.cc:1836:ReduceOr$16006_new_inv_ O=$abc$44715$techmap\common.pb.uart.rx_mod.symclk.$procmux$15655_Y[13]
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:56"
.param LUT_INIT 1010101010101000
.gate SB_LUT4 I0=$abc$44715$auto$wreduce.cc:455:run$15912[14] I1=$abc$44715$auto$simplemap.cc:168:logic_reduce$22268_new_inv_ I2=$abc$44715$new_n2753_ I3=$abc$44715$auto$rtlil.cc:1836:ReduceOr$16006_new_inv_ O=$abc$44715$techmap\common.pb.uart.rx_mod.symclk.$procmux$15655_Y[14]
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:56"
.param LUT_INIT 1010101010101000
.gate SB_LUT4 I0=$abc$44715$auto$wreduce.cc:455:run$15912[15] I1=$abc$44715$auto$simplemap.cc:168:logic_reduce$22268_new_inv_ I2=$abc$44715$new_n2753_ I3=$abc$44715$auto$rtlil.cc:1836:ReduceOr$16006_new_inv_ O=$abc$44715$techmap\common.pb.uart.rx_mod.symclk.$procmux$15655_Y[15]
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:56"
.param LUT_INIT 1010101010101000
.gate SB_LUT4 I0=$abc$44715$auto$wreduce.cc:455:run$15912[16] I1=$abc$44715$auto$simplemap.cc:168:logic_reduce$22268_new_inv_ I2=$abc$44715$new_n2753_ I3=$abc$44715$auto$rtlil.cc:1836:ReduceOr$16006_new_inv_ O=$abc$44715$techmap\common.pb.uart.rx_mod.symclk.$procmux$15655_Y[16]
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:56"
.param LUT_INIT 1010101010101000
.gate SB_LUT4 I0=$abc$44715$auto$wreduce.cc:455:run$15912[17] I1=$abc$44715$auto$simplemap.cc:168:logic_reduce$22268_new_inv_ I2=$abc$44715$new_n2753_ I3=$abc$44715$auto$rtlil.cc:1836:ReduceOr$16006_new_inv_ O=$abc$44715$techmap\common.pb.uart.rx_mod.symclk.$procmux$15655_Y[17]
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:56"
.param LUT_INIT 1010101010101000
.gate SB_LUT4 I0=$abc$44715$auto$wreduce.cc:455:run$15912[18] I1=$abc$44715$auto$simplemap.cc:168:logic_reduce$22268_new_inv_ I2=$abc$44715$new_n2753_ I3=$abc$44715$auto$rtlil.cc:1836:ReduceOr$16006_new_inv_ O=$abc$44715$techmap\common.pb.uart.rx_mod.symclk.$procmux$15655_Y[18]
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:56"
.param LUT_INIT 1010101010101000
.gate SB_LUT4 I0=$abc$44715$auto$wreduce.cc:455:run$15912[19] I1=$abc$44715$auto$simplemap.cc:168:logic_reduce$22268_new_inv_ I2=$abc$44715$new_n2753_ I3=$abc$44715$auto$rtlil.cc:1836:ReduceOr$16006_new_inv_ O=$abc$44715$techmap\common.pb.uart.rx_mod.symclk.$procmux$15655_Y[19]
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:56"
.param LUT_INIT 1010101010101000
.gate SB_LUT4 I0=$abc$44715$auto$wreduce.cc:455:run$15912[20] I1=$abc$44715$auto$simplemap.cc:168:logic_reduce$22268_new_inv_ I2=$abc$44715$new_n2753_ I3=$abc$44715$auto$rtlil.cc:1836:ReduceOr$16006_new_inv_ O=$abc$44715$techmap\common.pb.uart.rx_mod.symclk.$procmux$15655_Y[20]
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:56"
.param LUT_INIT 1010101010101000
.gate SB_LUT4 I0=$abc$44715$auto$wreduce.cc:455:run$15912[21] I1=$abc$44715$auto$simplemap.cc:168:logic_reduce$22268_new_inv_ I2=$abc$44715$new_n2753_ I3=$abc$44715$auto$rtlil.cc:1836:ReduceOr$16006_new_inv_ O=$abc$44715$techmap\common.pb.uart.rx_mod.symclk.$procmux$15655_Y[21]
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:56"
.param LUT_INIT 1010101010101000
.gate SB_LUT4 I0=$abc$44715$auto$wreduce.cc:455:run$15912[22] I1=$abc$44715$auto$simplemap.cc:168:logic_reduce$22268_new_inv_ I2=$abc$44715$new_n2753_ I3=$abc$44715$auto$rtlil.cc:1836:ReduceOr$16006_new_inv_ O=$abc$44715$techmap\common.pb.uart.rx_mod.symclk.$procmux$15655_Y[22]
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:56"
.param LUT_INIT 1010101010101000
.gate SB_LUT4 I0=$abc$44715$auto$wreduce.cc:455:run$15912[23] I1=$abc$44715$auto$simplemap.cc:168:logic_reduce$22268_new_inv_ I2=$abc$44715$new_n2753_ I3=$abc$44715$auto$rtlil.cc:1836:ReduceOr$16006_new_inv_ O=$abc$44715$techmap\common.pb.uart.rx_mod.symclk.$procmux$15655_Y[23]
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:56"
.param LUT_INIT 1010101010101000
.gate SB_LUT4 I0=$false I1=$false I2=$abc$44715$new_n2753_ I3=$abc$44715$auto$simplemap.cc:168:logic_reduce$22268_new_inv_ O=$abc$44715$techmap\common.pb.uart.rx_mod.symclk.$procmux$15633_Y
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:46"
.param LUT_INIT 0000000011110000
.gate SB_LUT4 I0=$false I1=$abc$44715$auto$simplemap.cc:168:logic_reduce$22268_new_inv_ I2=$abc$44715$new_n2753_ I3=$abc$44715$auto$rtlil.cc:1836:ReduceOr$16006_new_inv_ O=$abc$44715$techmap\common.pb.uart.rx_mod.symclk.$procmux$15622_Y
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:51"
.param LUT_INIT 0000000000000011
.gate SB_LUT4 I0=$false I1=$false I2=common.pb.uart_clks_per_sym[0] I3=$abc$44715$auto$alumacc.cc:491:replace_alu$16009[23] O=common.pb.uart.rx_mod.symclk.clks_per_sym_limited
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:46"
.param LUT_INIT 0000000011110000
.gate SB_LUT4 I0=$false I1=$false I2=common.pb.uart_clks_per_sym[1] I3=$abc$44715$auto$alumacc.cc:491:replace_alu$16009[23] O=common.pb.uart.tx_mod.symclk.clks_per_sym_limited[1]
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:46"
.param LUT_INIT 0000000011110000
.gate SB_LUT4 I0=$false I1=$false I2=common.pb.uart_clks_per_sym[2] I3=$abc$44715$auto$alumacc.cc:491:replace_alu$16009[23] O=common.pb.uart.tx_mod.symclk.clks_per_sym_limited[2]
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:46"
.param LUT_INIT 1111111111110000
.gate SB_LUT4 I0=$false I1=$false I2=common.pb.uart_clks_per_sym[3] I3=$abc$44715$auto$alumacc.cc:491:replace_alu$16009[23] O=common.pb.uart.tx_mod.symclk.clks_per_sym_limited[3]
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:46"
.param LUT_INIT 0000000011110000
.gate SB_LUT4 I0=$false I1=$false I2=common.pb.uart_clks_per_sym[4] I3=$abc$44715$auto$alumacc.cc:491:replace_alu$16009[23] O=common.pb.uart.tx_mod.symclk.clks_per_sym_limited[4]
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:46"
.param LUT_INIT 0000000011110000
.gate SB_LUT4 I0=$false I1=$false I2=common.pb.uart_clks_per_sym[5] I3=$abc$44715$auto$alumacc.cc:491:replace_alu$16009[23] O=common.pb.uart.tx_mod.symclk.clks_per_sym_limited[5]
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:46"
.param LUT_INIT 0000000011110000
.gate SB_LUT4 I0=$false I1=$false I2=common.pb.uart_clks_per_sym[6] I3=$abc$44715$auto$alumacc.cc:491:replace_alu$16009[23] O=common.pb.uart.tx_mod.symclk.clks_per_sym_limited[6]
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:46"
.param LUT_INIT 0000000011110000
.gate SB_LUT4 I0=$false I1=$false I2=common.pb.uart_clks_per_sym[7] I3=$abc$44715$auto$alumacc.cc:491:replace_alu$16009[23] O=common.pb.uart.tx_mod.symclk.clks_per_sym_limited[7]
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:46"
.param LUT_INIT 0000000011110000
.gate SB_LUT4 I0=$false I1=$false I2=common.pb.uart_clks_per_sym[8] I3=$abc$44715$auto$alumacc.cc:491:replace_alu$16009[23] O=common.pb.uart.tx_mod.symclk.clks_per_sym_limited[8]
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:46"
.param LUT_INIT 0000000011110000
.gate SB_LUT4 I0=$false I1=$false I2=common.pb.uart_clks_per_sym[9] I3=$abc$44715$auto$alumacc.cc:491:replace_alu$16009[23] O=common.pb.uart.tx_mod.symclk.clks_per_sym_limited[9]
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:46"
.param LUT_INIT 0000000011110000
.gate SB_LUT4 I0=$false I1=$false I2=common.pb.uart_clks_per_sym[10] I3=$abc$44715$auto$alumacc.cc:491:replace_alu$16009[23] O=common.pb.uart.tx_mod.symclk.clks_per_sym_limited[10]
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:46"
.param LUT_INIT 0000000011110000
.gate SB_LUT4 I0=$false I1=$false I2=common.pb.uart_clks_per_sym[11] I3=$abc$44715$auto$alumacc.cc:491:replace_alu$16009[23] O=common.pb.uart.tx_mod.symclk.clks_per_sym_limited[11]
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:46"
.param LUT_INIT 0000000011110000
.gate SB_LUT4 I0=$false I1=$false I2=common.pb.uart_clks_per_sym[12] I3=$abc$44715$auto$alumacc.cc:491:replace_alu$16009[23] O=common.pb.uart.tx_mod.symclk.clks_per_sym_limited[12]
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:46"
.param LUT_INIT 0000000011110000
.gate SB_LUT4 I0=$false I1=$false I2=common.pb.uart_clks_per_sym[13] I3=$abc$44715$auto$alumacc.cc:491:replace_alu$16009[23] O=common.pb.uart.tx_mod.symclk.clks_per_sym_limited[13]
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:46"
.param LUT_INIT 0000000011110000
.gate SB_LUT4 I0=$false I1=$false I2=common.pb.uart_clks_per_sym[14] I3=$abc$44715$auto$alumacc.cc:491:replace_alu$16009[23] O=common.pb.uart.tx_mod.symclk.clks_per_sym_limited[14]
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:46"
.param LUT_INIT 0000000011110000
.gate SB_LUT4 I0=$false I1=$false I2=common.pb.uart_clks_per_sym[15] I3=$abc$44715$auto$alumacc.cc:491:replace_alu$16009[23] O=common.pb.uart.tx_mod.symclk.clks_per_sym_limited[15]
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:46"
.param LUT_INIT 0000000011110000
.gate SB_LUT4 I0=$false I1=$false I2=common.pb.uart_clks_per_sym[16] I3=$abc$44715$auto$alumacc.cc:491:replace_alu$16009[23] O=common.pb.uart.tx_mod.symclk.clks_per_sym_limited[16]
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:46"
.param LUT_INIT 0000000011110000
.gate SB_LUT4 I0=$false I1=$false I2=common.pb.uart_clks_per_sym[17] I3=$abc$44715$auto$alumacc.cc:491:replace_alu$16009[23] O=common.pb.uart.tx_mod.symclk.clks_per_sym_limited[17]
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:46"
.param LUT_INIT 0000000011110000
.gate SB_LUT4 I0=$false I1=$false I2=common.pb.uart_clks_per_sym[18] I3=$abc$44715$auto$alumacc.cc:491:replace_alu$16009[23] O=common.pb.uart.tx_mod.symclk.clks_per_sym_limited[18]
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:46"
.param LUT_INIT 0000000011110000
.gate SB_LUT4 I0=$false I1=$false I2=common.pb.uart_clks_per_sym[19] I3=$abc$44715$auto$alumacc.cc:491:replace_alu$16009[23] O=common.pb.uart.tx_mod.symclk.clks_per_sym_limited[19]
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:46"
.param LUT_INIT 0000000011110000
.gate SB_LUT4 I0=$false I1=$false I2=common.pb.uart_clks_per_sym[20] I3=$abc$44715$auto$alumacc.cc:491:replace_alu$16009[23] O=common.pb.uart.tx_mod.symclk.clks_per_sym_limited[20]
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:46"
.param LUT_INIT 0000000011110000
.gate SB_LUT4 I0=$false I1=$false I2=common.pb.uart_clks_per_sym[21] I3=$abc$44715$auto$alumacc.cc:491:replace_alu$16009[23] O=common.pb.uart.tx_mod.symclk.clks_per_sym_limited[21]
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:46"
.param LUT_INIT 0000000011110000
.gate SB_LUT4 I0=$false I1=$false I2=common.pb.uart_clks_per_sym[22] I3=$abc$44715$auto$alumacc.cc:491:replace_alu$16009[23] O=common.pb.uart.tx_mod.symclk.clks_per_sym_limited[22]
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:46"
.param LUT_INIT 0000000011110000
.gate SB_LUT4 I0=$false I1=$false I2=common.pb.uart_clks_per_sym[23] I3=$abc$44715$auto$alumacc.cc:491:replace_alu$16009[23] O=common.pb.uart.tx_mod.symclk.clks_per_sym_limited[23]
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:46"
.param LUT_INIT 0000000011110000
.gate SB_LUT4 I0=$false I1=$false I2=$abc$44715$auto$simplemap.cc:127:simplemap_reduce$23012_new_inv_ I3=$abc$44715$techmap$techmap\common.pb.spirx_lencalc.$procmux$14747.$and$/home/mb/fpga-toolchain/yosys/bin/../share/yosys/techmap.v:434$18294_Y[0]_new_ O=$abc$44715$techmap$techmap\common.pb.spirx_lencalc.$procmux$14747.$ternary$/home/mb/fpga-toolchain/yosys/bin/../share/yosys/techmap.v:445$18291_Y[0]
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:46"
.param LUT_INIT 1111111100001111
.gate SB_LUT4 I0=common.pb.spirx_lencalc.length[0] I1=$abc$44715$new_n2312_ I2=common.pb.spirx_lencalc.byte_le[0] I3=$abc$44715$new_n2321_ O=$abc$44715$auto$simplemap.cc:127:simplemap_reduce$23012_new_inv_
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:56"
.param LUT_INIT 0000110111011101
.gate SB_LUT4 I0=$false I1=common.pb.spirx_lencalc.state[1] I2=common.pb.spirx_lencalc.state[0] I3=$abc$44715$new_n2741_ O=$abc$44715$new_n2312_
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:51"
.param LUT_INIT 1100111111000011
.gate SB_LUT4 I0=$false I1=$false I2=common.pb.spirx_lencalc.byte_le[1] I3=common.pb.spirx_lencalc_byte[1] O=$abc$44715$auto$simplemap.cc:250:simplemap_eqne$20197[1]_new_
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:46"
.param LUT_INIT 0000111111110000
.gate SB_LUT4 I0=$false I1=common.pb.spirx_lencalc.state[1] I2=$abc$44715$new_n2741_ I3=common.pb.spirx_lencalc.state[0] O=$abc$44715$new_n2321_
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:51"
.param LUT_INIT 0000000011000000
.gate SB_LUT4 I0=$abc$44715$auto$simplemap.cc:168:logic_reduce$20153_new_inv_ I1=$abc$44715$new_n2323_ I2=common.pb.spirx_lencalc.length[0] I3=common.pb.spirx_lencalc_new O=$abc$44715$techmap$techmap\common.pb.spirx_lencalc.$procmux$14747.$and$/home/mb/fpga-toolchain/yosys/bin/../share/yosys/techmap.v:434$18294_Y[0]_new_
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:56"
.param LUT_INIT 0010001010100010
.gate SB_LUT4 I0=$abc$44715$new_n2324_ I1=$abc$44715$new_n2328_ I2=$abc$44715$new_n2327_ I3=$abc$44715$auto$simplemap.cc:127:simplemap_reduce$20665[2]_new_ O=$abc$44715$new_n2323_
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:56"
.param LUT_INIT 0001010101010101
.gate SB_LUT4 I0=$false I1=common.pb.spirx_lencalc_byte[2] I2=$abc$44715$new_n2326_ I3=$abc$44715$new_n2325_ O=$abc$44715$new_n2324_
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:51"
.param LUT_INIT 1100000000000000
.gate SB_LUT4 I0=common.pb.spirx_lencalc_byte[4] I1=common.pb.spirx_lencalc_byte[1] I2=common.pb.spirx_lencalc_byte[0] I3=common.pb.spirx_lencalc_byte[5] O=$abc$44715$new_n2325_
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:56"
.param LUT_INIT 0000000000000010
.gate SB_LUT4 I0=common.pb.spirx_lencalc_new I1=common.pb.spirx_lencalc_byte[3] I2=common.pb.spirx_lencalc_byte[6] I3=common.pb.spirx_lencalc_byte[7] O=$abc$44715$new_n2326_
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:56"
.param LUT_INIT 1000000000000000
.gate SB_LUT4 I0=$false I1=common.pb.spirx_lencalc_new I2=common.pb.spirx_lencalc_byte[5] I3=common.pb.spirx_lencalc_byte[4] O=$abc$44715$new_n2327_
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:51"
.param LUT_INIT 0000000011000000
.gate SB_LUT4 I0=common.pb.spirx_lencalc_byte[7] I1=common.pb.spirx_lencalc_byte[0] I2=common.pb.spirx_lencalc_byte[6] I3=common.pb.spirx_lencalc_byte[1] O=$abc$44715$new_n2328_
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:56"
.param LUT_INIT 0000000010000000
.gate SB_LUT4 I0=$false I1=$false I2=common.pb.spirx_lencalc_byte[2] I3=common.pb.spirx_lencalc_byte[3] O=$abc$44715$auto$simplemap.cc:127:simplemap_reduce$20665[2]_new_
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:46"
.param LUT_INIT 0000000011110000
.gate SB_LUT4 I0=$false I1=$false I2=common.pb.spirx_lencalc.state[1] I3=common.pb.spirx_lencalc.state[0] O=$abc$44715$auto$simplemap.cc:168:logic_reduce$20153_new_inv_
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:46"
.param LUT_INIT 0000000000001111
.gate SB_LUT4 I0=$abc$44715$new_n2333_ I1=$abc$44715$new_n2334_ I2=$abc$44715$new_n2332_ I3=common.pb.spirx_lencalc.length[1] O=$abc$44715$techmap$techmap\common.pb.spirx_lencalc.$procmux$14747.$ternary$/home/mb/fpga-toolchain/yosys/bin/../share/yosys/techmap.v:445$18291_Y[1]
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:56"
.param LUT_INIT 1110111111101110
.gate SB_LUT4 I0=$false I1=$abc$44715$new_n2312_ I2=$abc$44715$auto$simplemap.cc:168:logic_reduce$20153_new_inv_ I3=common.pb.spirx_lencalc_new O=$abc$44715$new_n2332_
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:51"
.param LUT_INIT 1100110000001100
.gate SB_LUT4 I0=$false I1=$false I2=$abc$44715$new_n2321_ I3=common.pb.spirx_lencalc.byte_le[1] O=$abc$44715$new_n2333_
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:46"
.param LUT_INIT 0000000011110000
.gate SB_LUT4 I0=$false I1=$abc$44715$auto$simplemap.cc:168:logic_reduce$20153_new_inv_ I2=$abc$44715$new_n2335_ I3=$abc$44715$new_n2324_ O=$abc$44715$new_n2334_
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:51"
.param LUT_INIT 1100110000001100
.gate SB_LUT4 I0=$abc$44715$new_n2336_ I1=$abc$44715$new_n2337_ I2=$abc$44715$new_n2325_ I3=$abc$44715$auto$simplemap.cc:127:simplemap_reduce$20665[0]_new_ O=$abc$44715$new_n2335_
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:56"
.param LUT_INIT 0001010101010101
.gate SB_LUT4 I0=$abc$44715$new_n2338_ I1=$abc$44715$new_n2337_ I2=common.pb.spirx_lencalc_byte[0] I3=common.pb.spirx_lencalc_byte[6] O=$abc$44715$new_n2336_
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:56"
.param LUT_INIT 0000000000001000
.gate SB_LUT4 I0=$false I1=common.pb.spirx_lencalc_new I2=common.pb.spirx_lencalc_byte[2] I3=common.pb.spirx_lencalc_byte[3] O=$abc$44715$new_n2337_
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:51"
.param LUT_INIT 0000000000001100
.gate SB_LUT4 I0=common.pb.spirx_lencalc_byte[1] I1=common.pb.spirx_lencalc_byte[7] I2=common.pb.spirx_lencalc_byte[5] I3=common.pb.spirx_lencalc_byte[4] O=$abc$44715$new_n2338_
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:56"
.param LUT_INIT 0000000010000000
.gate SB_LUT4 I0=$false I1=$false I2=common.pb.spirx_lencalc_byte[6] I3=common.pb.spirx_lencalc_byte[7] O=$abc$44715$auto$simplemap.cc:127:simplemap_reduce$20665[0]_new_
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:46"
.param LUT_INIT 0000000000001111
.gate SB_LUT4 I0=$false I1=$abc$44715$new_n2341_ I2=common.pb.spirx_lencalc.length[2] I3=$abc$44715$new_n2312_ O=$abc$44715$techmap$techmap\common.pb.spirx_lencalc.$procmux$14747.$ternary$/home/mb/fpga-toolchain/yosys/bin/../share/yosys/techmap.v:445$18291_Y[2]
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:51"
.param LUT_INIT 0011001111110011
.gate SB_LUT4 I0=$abc$44715$techmap$techmap\common.pb.spirx_lencalc.$procmux$14747.$and$/home/mb/fpga-toolchain/yosys/bin/../share/yosys/techmap.v:434$18294_Y[2]_new_ I1=common.pb.spirx_lencalc.byte_le[2] I2=common.pb.spirx_lencalc.byte_le[1] I3=$abc$44715$new_n2321_ O=$abc$44715$new_n2341_
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:56"
.param LUT_INIT 0001010001010101
.gate SB_LUT4 I0=$abc$44715$auto$simplemap.cc:168:logic_reduce$20153_new_inv_ I1=$abc$44715$new_n2335_ I2=common.pb.spirx_lencalc.length[2] I3=common.pb.spirx_lencalc_new O=$abc$44715$techmap$techmap\common.pb.spirx_lencalc.$procmux$14747.$and$/home/mb/fpga-toolchain/yosys/bin/../share/yosys/techmap.v:434$18294_Y[2]_new_
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:56"
.param LUT_INIT 0010001010100010
.gate SB_LUT4 I0=$false I1=$false I2=$abc$44715$auto$simplemap.cc:127:simplemap_reduce$23024_new_inv_ I3=$abc$44715$techmap$techmap\common.pb.spirx_lencalc.$procmux$14747.$and$/home/mb/fpga-toolchain/yosys/bin/../share/yosys/techmap.v:434$18294_Y[3]_new_ O=$abc$44715$techmap$techmap\common.pb.spirx_lencalc.$procmux$14747.$ternary$/home/mb/fpga-toolchain/yosys/bin/../share/yosys/techmap.v:445$18291_Y[3]
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:46"
.param LUT_INIT 1111111100001111
.gate SB_LUT4 I0=common.pb.spirx_lencalc.length[3] I1=$abc$44715$new_n2312_ I2=$abc$44715$auto$wreduce.cc:455:run$15910[3] I3=$abc$44715$new_n2321_ O=$abc$44715$auto$simplemap.cc:127:simplemap_reduce$23024_new_inv_
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:56"
.param LUT_INIT 0000110111011101
.gate SB_LUT4 I0=$abc$44715$auto$simplemap.cc:168:logic_reduce$20153_new_inv_ I1=$abc$44715$new_n2336_ I2=common.pb.spirx_lencalc.length[3] I3=common.pb.spirx_lencalc_new O=$abc$44715$techmap$techmap\common.pb.spirx_lencalc.$procmux$14747.$and$/home/mb/fpga-toolchain/yosys/bin/../share/yosys/techmap.v:434$18294_Y[3]_new_
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:56"
.param LUT_INIT 1000100010101000
.gate SB_LUT4 I0=common.pb.spirx_lencalc.length[4] I1=$abc$44715$new_n2332_ I2=$abc$44715$auto$wreduce.cc:455:run$15910[4] I3=$abc$44715$new_n2321_ O=$abc$44715$techmap$techmap\common.pb.spirx_lencalc.$procmux$14747.$ternary$/home/mb/fpga-toolchain/yosys/bin/../share/yosys/techmap.v:445$18291_Y[4]
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:56"
.param LUT_INIT 1111001000100010
.gate SB_LUT4 I0=common.pb.spirx_lencalc.length[5] I1=$abc$44715$new_n2332_ I2=$abc$44715$auto$wreduce.cc:455:run$15910[5] I3=$abc$44715$new_n2321_ O=$abc$44715$techmap$techmap\common.pb.spirx_lencalc.$procmux$14747.$ternary$/home/mb/fpga-toolchain/yosys/bin/../share/yosys/techmap.v:445$18291_Y[5]
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:56"
.param LUT_INIT 1111001000100010
.gate SB_LUT4 I0=common.pb.spirx_lencalc.length[6] I1=$abc$44715$new_n2332_ I2=$abc$44715$auto$wreduce.cc:455:run$15910[6] I3=$abc$44715$new_n2321_ O=$abc$44715$techmap$techmap\common.pb.spirx_lencalc.$procmux$14747.$ternary$/home/mb/fpga-toolchain/yosys/bin/../share/yosys/techmap.v:445$18291_Y[6]
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:56"
.param LUT_INIT 1111001000100010
.gate SB_LUT4 I0=common.pb.spirx_lencalc.length[7] I1=$abc$44715$new_n2332_ I2=$abc$44715$auto$wreduce.cc:455:run$15910[7] I3=$abc$44715$new_n2321_ O=$abc$44715$techmap$techmap\common.pb.spirx_lencalc.$procmux$14747.$ternary$/home/mb/fpga-toolchain/yosys/bin/../share/yosys/techmap.v:445$18291_Y[7]
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:56"
.param LUT_INIT 1111001000100010
.gate SB_LUT4 I0=common.pb.spirx_lencalc.state[0] I1=common.pb.spirx_lencalc.state[1] I2=$abc$44715$new_n2351_ I3=common.pb.spirx_lencalc_new O=$abc$44715$techmap$techmap\common.pb.spirx_lencalc.$procmux$14776.$ternary$/home/mb/fpga-toolchain/yosys/bin/../share/yosys/techmap.v:445$20137_Y[0]
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:56"
.param LUT_INIT 0001000000110010
.gate SB_LUT4 I0=$abc$44715$new_n2327_ I1=common.pb.spirx_lencalc_byte[3] I2=$abc$44715$new_n2352_ I3=common.pb.spirx_lencalc_byte[2] O=$abc$44715$new_n2351_
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:56"
.param LUT_INIT 0000000010000000
.gate SB_LUT4 I0=common.pb.spirx_lencalc_byte[6] I1=common.pb.spirx_lencalc_byte[1] I2=common.pb.spirx_lencalc_byte[0] I3=common.pb.spirx_lencalc_byte[7] O=$abc$44715$new_n2352_
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:56"
.param LUT_INIT 0000000000000010
.gate SB_LUT4 I0=common.pb.spirx_lencalc_new I1=common.pb.spirx_lencalc.state[0] I2=common.pb.spirx_lencalc.state[1] I3=$abc$44715$techmap\common.pb.spirx_lencalc.$logic_and$profibus_phy_mod.v:144$5341_Y_new_ O=$abc$44715$techmap$techmap\common.pb.spirx_lencalc.$procmux$14776.$ternary$/home/mb/fpga-toolchain/yosys/bin/../share/yosys/techmap.v:445$20137_Y[1]
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:56"
.param LUT_INIT 0001100000010000
.gate SB_LUT4 I0=$abc$44715$auto$rtlil.cc:1836:ReduceOr$16033_new_inv_ I1=$abc$44715$auto$alumacc.cc:491:replace_alu$16018[7] I2=$abc$44715$new_n2357_ I3=$abc$44715$new_n2328_ O=$abc$44715$techmap\common.pb.spirx_lencalc.$logic_and$profibus_phy_mod.v:144$5341_Y_new_
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:56"
.param LUT_INIT 0101000100010001
.gate SB_LUT4 I0=$abc$44715$auto$alumacc.cc:491:replace_alu$16027[7] I1=$abc$44715$new_n2356_ I2=$abc$44715$auto$simplemap.cc:127:simplemap_reduce$20665[0]_new_ I3=$abc$44715$auto$simplemap.cc:127:simplemap_reduce$20665[2]_new_ O=$abc$44715$auto$rtlil.cc:1836:ReduceOr$16033_new_inv_
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:56"
.param LUT_INIT 0010101010101010
.gate SB_LUT4 I0=common.pb.spirx_lencalc_byte[1] I1=common.pb.spirx_lencalc_byte[0] I2=common.pb.spirx_lencalc_byte[4] I3=common.pb.spirx_lencalc_byte[5] O=$abc$44715$new_n2356_
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:56"
.param LUT_INIT 0000000000000001
.gate SB_LUT4 I0=common.pb.spirx_lencalc_byte[5] I1=common.pb.spirx_lencalc_byte[3] I2=common.pb.spirx_lencalc_byte[4] I3=common.pb.spirx_lencalc_byte[2] O=$abc$44715$new_n2357_
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:56"
.param LUT_INIT 0000000010000000
.gate SB_LUT4 I0=common.pb.spirx_lencalc.state[0] I1=common.pb.spirx_lencalc.byte_le[0] I2=$abc$44715$techmap\common.pb.spirx_lencalc.$procmux$14802_Y[0]_new_inv_ I3=common.pb.spirx_lencalc.state[1] O=$abc$44715$techmap$techmap\common.pb.spirx_lencalc.$procmux$14797.$ternary$/home/mb/fpga-toolchain/yosys/bin/../share/yosys/techmap.v:445$17894_Y[0]
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:56"
.param LUT_INIT 0100010001001110
.gate SB_LUT4 I0=$false I1=$abc$44715$new_n2360_ I2=common.pb.spirx_lencalc_byte[0] I3=common.pb.spirx_lencalc.byte_le[0] O=$abc$44715$techmap\common.pb.spirx_lencalc.$procmux$14802_Y[0]_new_inv_
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:51"
.param LUT_INIT 0000110000111111
.gate SB_LUT4 I0=$false I1=$false I2=common.pb.spirx_lencalc_new I3=$abc$44715$techmap\common.pb.spirx_lencalc.$logic_and$profibus_phy_mod.v:144$5341_Y_new_ O=$abc$44715$new_n2360_
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:46"
.param LUT_INIT 1111000000000000
.gate SB_LUT4 I0=common.pb.spirx_lencalc.state[0] I1=common.pb.spirx_lencalc.byte_le[1] I2=$abc$44715$techmap\common.pb.spirx_lencalc.$procmux$14802_Y[1]_new_inv_ I3=common.pb.spirx_lencalc.state[1] O=$abc$44715$techmap$techmap\common.pb.spirx_lencalc.$procmux$14797.$ternary$/home/mb/fpga-toolchain/yosys/bin/../share/yosys/techmap.v:445$17894_Y[1]
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:56"
.param LUT_INIT 0100010001001110
.gate SB_LUT4 I0=$false I1=$abc$44715$new_n2360_ I2=common.pb.spirx_lencalc_byte[1] I3=common.pb.spirx_lencalc.byte_le[1] O=$abc$44715$techmap\common.pb.spirx_lencalc.$procmux$14802_Y[1]_new_inv_
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:51"
.param LUT_INIT 0000110000111111
.gate SB_LUT4 I0=common.pb.spirx_lencalc.byte_le[2] I1=$abc$44715$new_n2364_ I2=$abc$44715$new_n2360_ I3=common.pb.spirx_lencalc.state[0] O=$abc$44715$techmap$techmap\common.pb.spirx_lencalc.$procmux$14797.$ternary$/home/mb/fpga-toolchain/yosys/bin/../share/yosys/techmap.v:445$17894_Y[2]
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:56"
.param LUT_INIT 1100100011101010
.gate SB_LUT4 I0=common.pb.spirx_lencalc.state[0] I1=common.pb.spirx_lencalc.state[1] I2=$abc$44715$new_n2360_ I3=common.pb.spirx_lencalc_byte[2] O=$abc$44715$new_n2364_
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:56"
.param LUT_INIT 0010001000000010
.gate SB_LUT4 I0=common.pb.spirx_lencalc.byte_le[3] I1=$abc$44715$new_n2366_ I2=$abc$44715$new_n2360_ I3=common.pb.spirx_lencalc.state[0] O=$abc$44715$techmap$techmap\common.pb.spirx_lencalc.$procmux$14797.$ternary$/home/mb/fpga-toolchain/yosys/bin/../share/yosys/techmap.v:445$17894_Y[3]
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:56"
.param LUT_INIT 1100100011101010
.gate SB_LUT4 I0=common.pb.spirx_lencalc.state[0] I1=common.pb.spirx_lencalc.state[1] I2=$abc$44715$new_n2360_ I3=common.pb.spirx_lencalc_byte[3] O=$abc$44715$new_n2366_
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:56"
.param LUT_INIT 0010001000000010
.gate SB_LUT4 I0=common.pb.spirx_lencalc.state[0] I1=common.pb.spirx_lencalc.byte_le[4] I2=$abc$44715$techmap\common.pb.spirx_lencalc.$procmux$14802_Y[4]_new_inv_ I3=common.pb.spirx_lencalc.state[1] O=$abc$44715$techmap$techmap\common.pb.spirx_lencalc.$procmux$14797.$ternary$/home/mb/fpga-toolchain/yosys/bin/../share/yosys/techmap.v:445$17894_Y[4]
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:56"
.param LUT_INIT 0100010001001110
.gate SB_LUT4 I0=$false I1=$abc$44715$new_n2360_ I2=common.pb.spirx_lencalc_byte[4] I3=common.pb.spirx_lencalc.byte_le[4] O=$abc$44715$techmap\common.pb.spirx_lencalc.$procmux$14802_Y[4]_new_inv_
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:51"
.param LUT_INIT 0000110000111111
.gate SB_LUT4 I0=common.pb.spirx_lencalc.state[0] I1=common.pb.spirx_lencalc.byte_le[5] I2=$abc$44715$techmap\common.pb.spirx_lencalc.$procmux$14802_Y[5]_new_inv_ I3=common.pb.spirx_lencalc.state[1] O=$abc$44715$techmap$techmap\common.pb.spirx_lencalc.$procmux$14797.$ternary$/home/mb/fpga-toolchain/yosys/bin/../share/yosys/techmap.v:445$17894_Y[5]
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:56"
.param LUT_INIT 0100010001001110
.gate SB_LUT4 I0=$false I1=$abc$44715$new_n2360_ I2=common.pb.spirx_lencalc_byte[5] I3=common.pb.spirx_lencalc.byte_le[5] O=$abc$44715$techmap\common.pb.spirx_lencalc.$procmux$14802_Y[5]_new_inv_
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:51"
.param LUT_INIT 0000110000111111
.gate SB_LUT4 I0=common.pb.spirx_lencalc.state[0] I1=common.pb.spirx_lencalc.byte_le[6] I2=$abc$44715$techmap\common.pb.spirx_lencalc.$procmux$14802_Y[6]_new_inv_ I3=common.pb.spirx_lencalc.state[1] O=$abc$44715$techmap$techmap\common.pb.spirx_lencalc.$procmux$14797.$ternary$/home/mb/fpga-toolchain/yosys/bin/../share/yosys/techmap.v:445$17894_Y[6]
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:56"
.param LUT_INIT 0100010001001110
.gate SB_LUT4 I0=$false I1=$abc$44715$new_n2360_ I2=common.pb.spirx_lencalc_byte[6] I3=common.pb.spirx_lencalc.byte_le[6] O=$abc$44715$techmap\common.pb.spirx_lencalc.$procmux$14802_Y[6]_new_inv_
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:51"
.param LUT_INIT 0000110000111111
.gate SB_LUT4 I0=common.pb.spirx_lencalc.byte_le[7] I1=$abc$44715$new_n2374_ I2=$abc$44715$new_n2360_ I3=common.pb.spirx_lencalc.state[0] O=$abc$44715$techmap$techmap\common.pb.spirx_lencalc.$procmux$14797.$ternary$/home/mb/fpga-toolchain/yosys/bin/../share/yosys/techmap.v:445$17894_Y[7]
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:56"
.param LUT_INIT 1100100011101010
.gate SB_LUT4 I0=common.pb.spirx_lencalc.state[0] I1=common.pb.spirx_lencalc.state[1] I2=$abc$44715$new_n2360_ I3=common.pb.spirx_lencalc_byte[7] O=$abc$44715$new_n2374_
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:56"
.param LUT_INIT 0010001000000010
.gate SB_LUT4 I0=$false I1=$false I2=$abc$44715$new_n2335_ I3=$abc$44715$new_n2323_ O=$abc$44715$new_n2378_
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:46"
.param LUT_INIT 1111000000000000
.gate SB_LUT4 I0=$abc$44715$new_n2321_ I1=$abc$44715$techmap$techmap\common.pb.spirx_lencalc.$procmux$14850.$and$/home/mb/fpga-toolchain/yosys/bin/../share/yosys/techmap.v:434$18552_Y_new_ I2=$abc$44715$new_n2383_ I3=common.pb.spirx_lencalc.length_valid O=$abc$44715$techmap$techmap\common.pb.spirx_lencalc.$procmux$14850.$ternary$/home/mb/fpga-toolchain/yosys/bin/../share/yosys/techmap.v:445$18549_Y
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:56"
.param LUT_INIT 1110111111101110
.gate SB_LUT4 I0=$abc$44715$auto$simplemap.cc:168:logic_reduce$20153_new_inv_ I1=$abc$44715$new_n2378_ I2=common.pb.spirx_lencalc.length_valid I3=common.pb.spirx_lencalc_new O=$abc$44715$techmap$techmap\common.pb.spirx_lencalc.$procmux$14850.$and$/home/mb/fpga-toolchain/yosys/bin/../share/yosys/techmap.v:434$18552_Y_new_
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:56"
.param LUT_INIT 0010001010100010
.gate SB_LUT4 I0=common.pb.spirx_lencalc.state[1] I1=common.pb.spirx_lencalc.state[0] I2=common.pb.spirx_lencalc_new I3=$abc$44715$techmap\common.pb.spirx_lencalc.$logic_and$profibus_phy_mod.v:144$5341_Y_new_ O=$abc$44715$new_n2383_
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:56"
.param LUT_INIT 1011100111111001
.gate SB_LUT4 I0=$false I1=$abc$44715$new_n2386_ I2=$abc$44715$new_n2385_ I3=$abc$44715$auto$opt_reduce.cc:132:opt_mux$15866_new_inv_ O=$abc$44715$techmap$techmap\common.pb.$procmux$14257.$ternary$/home/mb/fpga-toolchain/yosys/bin/../share/yosys/techmap.v:445$18549_Y
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:51"
.param LUT_INIT 0011000000110011
.gate SB_LUT4 I0=$false I1=$abc$44715$new_n1695_ I2=common.pb.spirx_len_valid I3=common.pb.spirx_lencalc.length_valid O=$abc$44715$new_n2385_
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:51"
.param LUT_INIT 1100000011001100
.gate SB_LUT4 I0=common.pb.spirx_lencalc_n_reset I1=$abc$44715$new_n1673_ I2=$abc$44715$auto$simplemap.cc:309:simplemap_lut$20537_new_ I3=common.pb.spi.rx_data_r[1] O=$abc$44715$new_n2386_
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:56"
.param LUT_INIT 0101010100010101
.gate SB_LUT4 I0=$false I1=common.pb.spirx_state[2] I2=common.pb.spirx_state[0] I3=common.pb.spirx_state[1] O=$abc$44715$auto$opt_reduce.cc:132:opt_mux$15866_new_inv_
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:51"
.param LUT_INIT 1100001100000011
.gate SB_LUT4 I0=common.pb.spirx_ctrl_data[0] I1=$abc$44715$new_n2389_ I2=$abc$44715$techmap$techmap\common.pb.$procmux$14444.$and$/home/mb/fpga-toolchain/yosys/bin/../share/yosys/techmap.v:434$18189_Y[2]_new_ I3=$abc$44715$new_n2391_ O=$abc$44715$techmap$techmap\common.pb.$procmux$14316.$ternary$/home/mb/fpga-toolchain/yosys/bin/../share/yosys/techmap.v:445$18472_Y[0]
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:56"
.param LUT_INIT 1111001000100010
.gate SB_LUT4 I0=$false I1=$false I2=$abc$44715$new_n2390_ I3=$abc$44715$new_n1694_ O=$abc$44715$new_n2389_
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:46"
.param LUT_INIT 0000000011110000
.gate SB_LUT4 I0=common.pb.spirx_state[0] I1=common.pb.spirx_state[1] I2=common.pb.spirx_state[2] I3=common.pb.spi.rx_irq_r O=$abc$44715$new_n2390_
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:56"
.param LUT_INIT 1001000110000001
.gate SB_LUT4 I0=$false I1=$false I2=common.pb.spi.rx_irq_r I3=common.pb.spi.rx_data_r[0] O=$abc$44715$new_n2391_
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:46"
.param LUT_INIT 1111000000000000
.gate SB_LUT4 I0=common.pb.spirx_ctrl_data[1] I1=$abc$44715$new_n2389_ I2=$abc$44715$new_n1641_ I3=$abc$44715$techmap$techmap\common.pb.$procmux$14444.$and$/home/mb/fpga-toolchain/yosys/bin/../share/yosys/techmap.v:434$18189_Y[2]_new_ O=$abc$44715$techmap$techmap\common.pb.$procmux$14316.$ternary$/home/mb/fpga-toolchain/yosys/bin/../share/yosys/techmap.v:445$18472_Y[1]
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:56"
.param LUT_INIT 1111001000100010
.gate SB_LUT4 I0=common.pb.spirx_ctrl_data[2] I1=$abc$44715$new_n2389_ I2=$abc$44715$techmap$techmap\common.pb.$procmux$14444.$and$/home/mb/fpga-toolchain/yosys/bin/../share/yosys/techmap.v:434$18189_Y[2]_new_ I3=$abc$44715$new_n2394_ O=$abc$44715$techmap$techmap\common.pb.$procmux$14316.$ternary$/home/mb/fpga-toolchain/yosys/bin/../share/yosys/techmap.v:445$18472_Y[2]
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:56"
.param LUT_INIT 1111001000100010
.gate SB_LUT4 I0=$false I1=$false I2=common.pb.spi.rx_irq_r I3=common.pb.spi.rx_data_r[2] O=$abc$44715$new_n2394_
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:46"
.param LUT_INIT 1111000000000000
.gate SB_LUT4 I0=common.pb.spirx_ctrl_data[3] I1=$abc$44715$new_n2389_ I2=$abc$44715$techmap$techmap\common.pb.$procmux$14444.$and$/home/mb/fpga-toolchain/yosys/bin/../share/yosys/techmap.v:434$18189_Y[2]_new_ I3=$abc$44715$new_n2396_ O=$abc$44715$techmap$techmap\common.pb.$procmux$14316.$ternary$/home/mb/fpga-toolchain/yosys/bin/../share/yosys/techmap.v:445$18472_Y[3]
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:56"
.param LUT_INIT 1111001000100010
.gate SB_LUT4 I0=$false I1=$false I2=common.pb.spi.rx_data_r[3] I3=common.pb.spi.rx_irq_r O=$abc$44715$new_n2396_
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:46"
.param LUT_INIT 1111000000000000
.gate SB_LUT4 I0=common.pb.spirx_ctrl_data[4] I1=$abc$44715$new_n2389_ I2=$abc$44715$techmap$techmap\common.pb.$procmux$14444.$and$/home/mb/fpga-toolchain/yosys/bin/../share/yosys/techmap.v:434$18189_Y[2]_new_ I3=$abc$44715$new_n2398_ O=$abc$44715$techmap$techmap\common.pb.$procmux$14316.$ternary$/home/mb/fpga-toolchain/yosys/bin/../share/yosys/techmap.v:445$18472_Y[4]
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:56"
.param LUT_INIT 1111001000100010
.gate SB_LUT4 I0=$false I1=$false I2=common.pb.spi.rx_irq_r I3=common.pb.spi.rx_data_r[4] O=$abc$44715$new_n2398_
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:46"
.param LUT_INIT 1111000000000000
.gate SB_LUT4 I0=common.pb.spirx_ctrl_data[5] I1=$abc$44715$new_n2389_ I2=$abc$44715$techmap$techmap\common.pb.$procmux$14444.$and$/home/mb/fpga-toolchain/yosys/bin/../share/yosys/techmap.v:434$18189_Y[2]_new_ I3=$abc$44715$new_n2400_ O=$abc$44715$techmap$techmap\common.pb.$procmux$14316.$ternary$/home/mb/fpga-toolchain/yosys/bin/../share/yosys/techmap.v:445$18472_Y[5]
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:56"
.param LUT_INIT 1111001000100010
.gate SB_LUT4 I0=$false I1=$false I2=common.pb.spi.rx_data_r[5] I3=common.pb.spi.rx_irq_r O=$abc$44715$new_n2400_
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:46"
.param LUT_INIT 1111000000000000
.gate SB_LUT4 I0=common.pb.spirx_ctrl_data[6] I1=$abc$44715$new_n2389_ I2=$abc$44715$techmap$techmap\common.pb.$procmux$14444.$and$/home/mb/fpga-toolchain/yosys/bin/../share/yosys/techmap.v:434$18189_Y[2]_new_ I3=$abc$44715$new_n2402_ O=$abc$44715$techmap$techmap\common.pb.$procmux$14316.$ternary$/home/mb/fpga-toolchain/yosys/bin/../share/yosys/techmap.v:445$18472_Y[6]
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:56"
.param LUT_INIT 1111001000100010
.gate SB_LUT4 I0=$false I1=$false I2=common.pb.spi.rx_irq_r I3=common.pb.spi.rx_data_r[6] O=$abc$44715$new_n2402_
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:46"
.param LUT_INIT 1111000000000000
.gate SB_LUT4 I0=common.pb.spirx_ctrl_data[7] I1=$abc$44715$new_n2389_ I2=$abc$44715$techmap$techmap\common.pb.$procmux$14444.$and$/home/mb/fpga-toolchain/yosys/bin/../share/yosys/techmap.v:434$18189_Y[2]_new_ I3=$abc$44715$new_n2404_ O=$abc$44715$techmap$techmap\common.pb.$procmux$14316.$ternary$/home/mb/fpga-toolchain/yosys/bin/../share/yosys/techmap.v:445$18472_Y[7]
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:56"
.param LUT_INIT 1111001000100010
.gate SB_LUT4 I0=$false I1=$false I2=common.pb.spi.rx_data_r[7] I3=common.pb.spi.rx_irq_r O=$abc$44715$new_n2404_
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:46"
.param LUT_INIT 1111000000000000
.gate SB_LUT4 I0=common.pb.spirx_ctrl_data[8] I1=$abc$44715$new_n2389_ I2=$abc$44715$new_n1681_ I3=common.pb.spirx_ctrl_data[0] O=$abc$44715$techmap$techmap\common.pb.$procmux$14316.$ternary$/home/mb/fpga-toolchain/yosys/bin/../share/yosys/techmap.v:445$18472_Y[8]
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:56"
.param LUT_INIT 1111001000100010
.gate SB_LUT4 I0=common.pb.spirx_ctrl_data[9] I1=$abc$44715$new_n2389_ I2=$abc$44715$new_n1681_ I3=common.pb.spirx_ctrl_data[1] O=$abc$44715$techmap$techmap\common.pb.$procmux$14316.$ternary$/home/mb/fpga-toolchain/yosys/bin/../share/yosys/techmap.v:445$18472_Y[9]
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:56"
.param LUT_INIT 1111001000100010
.gate SB_LUT4 I0=common.pb.spirx_ctrl_data[10] I1=$abc$44715$new_n2389_ I2=$abc$44715$new_n1681_ I3=common.pb.spirx_ctrl_data[2] O=$abc$44715$techmap$techmap\common.pb.$procmux$14316.$ternary$/home/mb/fpga-toolchain/yosys/bin/../share/yosys/techmap.v:445$18472_Y[10]
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:56"
.param LUT_INIT 1111001000100010
.gate SB_LUT4 I0=common.pb.spirx_ctrl_data[11] I1=$abc$44715$new_n2389_ I2=$abc$44715$new_n1681_ I3=common.pb.spirx_ctrl_data[3] O=$abc$44715$techmap$techmap\common.pb.$procmux$14316.$ternary$/home/mb/fpga-toolchain/yosys/bin/../share/yosys/techmap.v:445$18472_Y[11]
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:56"
.param LUT_INIT 1111001000100010
.gate SB_LUT4 I0=common.pb.spirx_ctrl_data[12] I1=$abc$44715$new_n2389_ I2=$abc$44715$new_n1681_ I3=common.pb.spirx_ctrl_data[4] O=$abc$44715$techmap$techmap\common.pb.$procmux$14316.$ternary$/home/mb/fpga-toolchain/yosys/bin/../share/yosys/techmap.v:445$18472_Y[12]
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:56"
.param LUT_INIT 1111001000100010
.gate SB_LUT4 I0=common.pb.spirx_ctrl_data[13] I1=$abc$44715$new_n2389_ I2=$abc$44715$new_n1681_ I3=common.pb.spirx_ctrl_data[5] O=$abc$44715$techmap$techmap\common.pb.$procmux$14316.$ternary$/home/mb/fpga-toolchain/yosys/bin/../share/yosys/techmap.v:445$18472_Y[13]
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:56"
.param LUT_INIT 1111001000100010
.gate SB_LUT4 I0=common.pb.spirx_ctrl_data[14] I1=$abc$44715$new_n2389_ I2=$abc$44715$new_n1681_ I3=common.pb.spirx_ctrl_data[6] O=$abc$44715$techmap$techmap\common.pb.$procmux$14316.$ternary$/home/mb/fpga-toolchain/yosys/bin/../share/yosys/techmap.v:445$18472_Y[14]
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:56"
.param LUT_INIT 1111001000100010
.gate SB_LUT4 I0=common.pb.spirx_ctrl_data[15] I1=$abc$44715$new_n2389_ I2=$abc$44715$new_n1681_ I3=common.pb.spirx_ctrl_data[7] O=$abc$44715$techmap$techmap\common.pb.$procmux$14316.$ternary$/home/mb/fpga-toolchain/yosys/bin/../share/yosys/techmap.v:445$18472_Y[15]
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:56"
.param LUT_INIT 1111001000100010
.gate SB_LUT4 I0=common.pb.spirx_ctrl_data[16] I1=$abc$44715$new_n2389_ I2=$abc$44715$new_n1681_ I3=common.pb.spirx_ctrl_data[8] O=$abc$44715$techmap$techmap\common.pb.$procmux$14316.$ternary$/home/mb/fpga-toolchain/yosys/bin/../share/yosys/techmap.v:445$18472_Y[16]
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:56"
.param LUT_INIT 1111001000100010
.gate SB_LUT4 I0=common.pb.spirx_ctrl_data[17] I1=$abc$44715$new_n2389_ I2=$abc$44715$new_n1681_ I3=common.pb.spirx_ctrl_data[9] O=$abc$44715$techmap$techmap\common.pb.$procmux$14316.$ternary$/home/mb/fpga-toolchain/yosys/bin/../share/yosys/techmap.v:445$18472_Y[17]
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:56"
.param LUT_INIT 1111001000100010
.gate SB_LUT4 I0=common.pb.spirx_ctrl_data[18] I1=$abc$44715$new_n2389_ I2=$abc$44715$new_n1681_ I3=common.pb.spirx_ctrl_data[10] O=$abc$44715$techmap$techmap\common.pb.$procmux$14316.$ternary$/home/mb/fpga-toolchain/yosys/bin/../share/yosys/techmap.v:445$18472_Y[18]
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:56"
.param LUT_INIT 1111001000100010
.gate SB_LUT4 I0=common.pb.spirx_ctrl_data[19] I1=$abc$44715$new_n2389_ I2=$abc$44715$new_n1681_ I3=common.pb.spirx_ctrl_data[11] O=$abc$44715$techmap$techmap\common.pb.$procmux$14316.$ternary$/home/mb/fpga-toolchain/yosys/bin/../share/yosys/techmap.v:445$18472_Y[19]
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:56"
.param LUT_INIT 1111001000100010
.gate SB_LUT4 I0=common.pb.spirx_ctrl_data[20] I1=$abc$44715$new_n2389_ I2=$abc$44715$new_n1681_ I3=common.pb.spirx_ctrl_data[12] O=$abc$44715$techmap$techmap\common.pb.$procmux$14316.$ternary$/home/mb/fpga-toolchain/yosys/bin/../share/yosys/techmap.v:445$18472_Y[20]
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:56"
.param LUT_INIT 1111001000100010
.gate SB_LUT4 I0=common.pb.spirx_ctrl_data[21] I1=$abc$44715$new_n2389_ I2=$abc$44715$new_n1681_ I3=common.pb.spirx_ctrl_data[13] O=$abc$44715$techmap$techmap\common.pb.$procmux$14316.$ternary$/home/mb/fpga-toolchain/yosys/bin/../share/yosys/techmap.v:445$18472_Y[21]
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:56"
.param LUT_INIT 1111001000100010
.gate SB_LUT4 I0=common.pb.spirx_ctrl_data[22] I1=$abc$44715$new_n2389_ I2=$abc$44715$new_n1681_ I3=common.pb.spirx_ctrl_data[14] O=$abc$44715$techmap$techmap\common.pb.$procmux$14316.$ternary$/home/mb/fpga-toolchain/yosys/bin/../share/yosys/techmap.v:445$18472_Y[22]
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:56"
.param LUT_INIT 1111001000100010
.gate SB_LUT4 I0=common.pb.spirx_ctrl_data[23] I1=$abc$44715$new_n2389_ I2=$abc$44715$new_n1681_ I3=common.pb.spirx_ctrl_data[15] O=$abc$44715$techmap$techmap\common.pb.$procmux$14316.$ternary$/home/mb/fpga-toolchain/yosys/bin/../share/yosys/techmap.v:445$18472_Y[23]
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:56"
.param LUT_INIT 1111001000100010
.gate SB_LUT4 I0=common.pb.spirx_ctrl[0] I1=$abc$44715$new_n2422_ I2=$abc$44715$auto$simplemap.cc:309:simplemap_lut$17319_new_ I3=$abc$44715$new_n2391_ O=$abc$44715$techmap$techmap\common.pb.$procmux$14335.$ternary$/home/mb/fpga-toolchain/yosys/bin/../share/yosys/techmap.v:445$18291_Y[0]
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:56"
.param LUT_INIT 1111001000100010
.gate SB_LUT4 I0=$abc$44715$auto$simplemap.cc:127:simplemap_reduce$25443[1]_new_ I1=$abc$44715$auto$simplemap.cc:309:simplemap_lut$17316[0]_new_ I2=$abc$44715$auto$simplemap.cc:168:logic_reduce$18573_new_inv_ I3=$abc$44715$new_n1640_ O=$abc$44715$new_n2422_
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:56"
.param LUT_INIT 0101010001000100
.gate SB_LUT4 I0=$false I1=$false I2=$abc$44715$auto$simplemap.cc:309:simplemap_lut$17319_new_ I3=common.pb.spi.rx_irq_r O=$abc$44715$auto$simplemap.cc:127:simplemap_reduce$25443[1]_new_
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:46"
.param LUT_INIT 0000000011110000
.gate SB_LUT4 I0=common.pb.spirx_ctrl[1] I1=$abc$44715$new_n2422_ I2=$abc$44715$auto$simplemap.cc:309:simplemap_lut$17319_new_ I3=$abc$44715$new_n1641_ O=$abc$44715$techmap$techmap\common.pb.$procmux$14335.$ternary$/home/mb/fpga-toolchain/yosys/bin/../share/yosys/techmap.v:445$18291_Y[1]
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:56"
.param LUT_INIT 1111001000100010
.gate SB_LUT4 I0=common.pb.spirx_ctrl[2] I1=$abc$44715$new_n2422_ I2=$abc$44715$auto$simplemap.cc:309:simplemap_lut$17319_new_ I3=$abc$44715$new_n2394_ O=$abc$44715$techmap$techmap\common.pb.$procmux$14335.$ternary$/home/mb/fpga-toolchain/yosys/bin/../share/yosys/techmap.v:445$18291_Y[2]
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:56"
.param LUT_INIT 1111001000100010
.gate SB_LUT4 I0=common.pb.spirx_ctrl[3] I1=$abc$44715$new_n2422_ I2=$abc$44715$auto$simplemap.cc:309:simplemap_lut$17319_new_ I3=$abc$44715$new_n2396_ O=$abc$44715$techmap$techmap\common.pb.$procmux$14335.$ternary$/home/mb/fpga-toolchain/yosys/bin/../share/yosys/techmap.v:445$18291_Y[3]
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:56"
.param LUT_INIT 1111001000100010
.gate SB_LUT4 I0=common.pb.spirx_ctrl[4] I1=$abc$44715$new_n2422_ I2=$abc$44715$auto$simplemap.cc:309:simplemap_lut$17319_new_ I3=$abc$44715$new_n2398_ O=$abc$44715$techmap$techmap\common.pb.$procmux$14335.$ternary$/home/mb/fpga-toolchain/yosys/bin/../share/yosys/techmap.v:445$18291_Y[4]
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:56"
.param LUT_INIT 1111001000100010
.gate SB_LUT4 I0=common.pb.spirx_ctrl[5] I1=$abc$44715$new_n2422_ I2=$abc$44715$auto$simplemap.cc:309:simplemap_lut$17319_new_ I3=$abc$44715$new_n2400_ O=$abc$44715$techmap$techmap\common.pb.$procmux$14335.$ternary$/home/mb/fpga-toolchain/yosys/bin/../share/yosys/techmap.v:445$18291_Y[5]
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:56"
.param LUT_INIT 1111001000100010
.gate SB_LUT4 I0=common.pb.spirx_ctrl[6] I1=$abc$44715$new_n2422_ I2=$abc$44715$auto$simplemap.cc:309:simplemap_lut$17319_new_ I3=$abc$44715$new_n2402_ O=$abc$44715$techmap$techmap\common.pb.$procmux$14335.$ternary$/home/mb/fpga-toolchain/yosys/bin/../share/yosys/techmap.v:445$18291_Y[6]
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:56"
.param LUT_INIT 1111001000100010
.gate SB_LUT4 I0=common.pb.spirx_ctrl[7] I1=$abc$44715$new_n2422_ I2=$abc$44715$auto$simplemap.cc:309:simplemap_lut$17319_new_ I3=$abc$44715$new_n2404_ O=$abc$44715$techmap$techmap\common.pb.$procmux$14335.$ternary$/home/mb/fpga-toolchain/yosys/bin/../share/yosys/techmap.v:445$18291_Y[7]
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:56"
.param LUT_INIT 1111001000100010
.gate SB_LUT4 I0=$abc$44715$new_n2432_ I1=common.pb.spi.rx_irq_r I2=$abc$44715$auto$simplemap.cc:250:simplemap_eqne$32268[3]_new_inv_ I3=$abc$44715$auto$simplemap.cc:309:simplemap_lut$17319_new_ O=$abc$44715$techmap$techmap\common.pb.$procmux$14444.$ternary$/home/mb/fpga-toolchain/yosys/bin/../share/yosys/techmap.v:445$18186_Y[0]
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:56"
.param LUT_INIT 0111011101110101
.gate SB_LUT4 I0=$abc$44715$techmap$techmap\common.pb.$procmux$14444.$and$/home/mb/fpga-toolchain/yosys/bin/../share/yosys/techmap.v:434$18189_Y[0]_new_ I1=$abc$44715$auto$simplemap.cc:127:simplemap_reduce$25434[2]_new_ I2=$abc$44715$new_n1640_ I3=$abc$44715$auto$simplemap.cc:168:logic_reduce$18573_new_inv_ O=$abc$44715$new_n2432_
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:56"
.param LUT_INIT 0000000100010001
.gate SB_LUT4 I0=$false I1=$abc$44715$auto$simplemap.cc:309:simplemap_lut$20537_new_ I2=$abc$44715$new_n2434_ I3=common.pb.spi.rx_irq_r O=$abc$44715$auto$simplemap.cc:127:simplemap_reduce$25434[2]_new_
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:51"
.param LUT_INIT 1100000011001100
.gate SB_LUT4 I0=$false I1=$abc$44715$new_n1641_ I2=$abc$44715$techmap\common.pb.$xor$parity_func.v:39$5527_Y_new_ I3=$abc$44715$new_n1674_ O=$abc$44715$new_n2434_
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:51"
.param LUT_INIT 0000110011000000
.gate SB_LUT4 I0=$abc$44715$new_n1681_ I1=$abc$44715$auto$alumacc.cc:491:replace_alu$16085[7] I2=$abc$44715$auto$simplemap.cc:127:simplemap_reduce$16926[1]_new_ I3=$abc$44715$auto$simplemap.cc:127:simplemap_reduce$16926[0]_new_ O=$abc$44715$techmap$techmap\common.pb.$procmux$14444.$and$/home/mb/fpga-toolchain/yosys/bin/../share/yosys/techmap.v:434$18189_Y[0]_new_
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:56"
.param LUT_INIT 1010001000100010
.gate SB_LUT4 I0=common.pb.spirx_bytecount[7] I1=common.pb.spirx_bytecount[6] I2=common.pb.spirx_bytecount[5] I3=common.pb.spirx_bytecount[4] O=$abc$44715$auto$simplemap.cc:127:simplemap_reduce$16926[0]_new_
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:56"
.param LUT_INIT 0000000000000001
.gate SB_LUT4 I0=common.pb.spirx_bytecount[1] I1=common.pb.spirx_bytecount[0] I2=common.pb.spirx_bytecount[3] I3=common.pb.spirx_bytecount[2] O=$abc$44715$auto$simplemap.cc:127:simplemap_reduce$16926[1]_new_
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:56"
.param LUT_INIT 0000000000001000
.gate SB_LUT4 I0=$abc$44715$auto$simplemap.cc:127:simplemap_reduce$25443[1]_new_ I1=$abc$44715$new_n2450_ I2=$abc$44715$techmap$techmap\common.pb.$procmux$14444.$and$/home/mb/fpga-toolchain/yosys/bin/../share/yosys/techmap.v:434$18191_Y[1]_new_ I3=$abc$44715$new_n2439_ O=$abc$44715$techmap$techmap\common.pb.$procmux$14444.$ternary$/home/mb/fpga-toolchain/yosys/bin/../share/yosys/techmap.v:445$18186_Y[1]
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:56"
.param LUT_INIT 1111111111111110
.gate SB_LUT4 I0=$false I1=common.pb.spi.rx_irq_r I2=$abc$44715$new_n2441_ I3=$abc$44715$techmap$techmap\common.pb.$procmux$14444.$and$/home/mb/fpga-toolchain/yosys/bin/../share/yosys/techmap.v:434$18188_Y[2]_new_ O=$abc$44715$new_n2439_
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:51"
.param LUT_INIT 1100110011000000
.gate SB_LUT4 I0=$false I1=$false I2=$abc$44715$auto$simplemap.cc:250:simplemap_eqne$32268[3]_new_inv_ I3=$abc$44715$new_n1765_ O=$abc$44715$techmap$techmap\common.pb.$procmux$14444.$and$/home/mb/fpga-toolchain/yosys/bin/../share/yosys/techmap.v:434$18188_Y[2]_new_
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:46"
.param LUT_INIT 0000000011110000
.gate SB_LUT4 I0=$abc$44715$auto$simplemap.cc:309:simplemap_lut$20537_new_ I1=$abc$44715$techmap\common.pb.$xor$parity_func.v:39$5527_Y_new_ I2=$abc$44715$new_n1674_ I3=common.pb.spi.rx_irq_r O=$abc$44715$new_n2441_
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:56"
.param LUT_INIT 0010100010101010
.gate SB_LUT4 I0=$abc$44715$new_n1695_ I1=common.pb.spirx_len_valid I2=$abc$44715$auto$alumacc.cc:491:replace_alu$16094[7] I3=$abc$44715$auto$rtlil.cc:1835:ReduceAnd$16100_new_ O=$abc$44715$techmap$techmap\common.pb.$procmux$14444.$and$/home/mb/fpga-toolchain/yosys/bin/../share/yosys/techmap.v:434$18191_Y[1]_new_
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:56"
.param LUT_INIT 0010001000101010
.gate SB_LUT4 I0=$false I1=$abc$44715$new_n2446_ I2=common.pb.spirx_bytecount[1] I3=common.pb.spirx_len[1] O=$abc$44715$new_n2445_
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:51"
.param LUT_INIT 1100000000001100
.gate SB_LUT4 I0=common.pb.spirx_bytecount[7] I1=common.pb.spirx_len[7] I2=common.pb.spirx_bytecount[2] I3=common.pb.spirx_len[2] O=$abc$44715$new_n2446_
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:56"
.param LUT_INIT 1001000000001001
.gate SB_LUT4 I0=$false I1=$abc$44715$auto$simplemap.cc:250:simplemap_eqne$30609[2]_new_inv_ I2=$abc$44715$auto$simplemap.cc:250:simplemap_eqne$19803_new_inv_ I3=$abc$44715$auto$simplemap.cc:250:simplemap_eqne$30621[1]_new_ O=$abc$44715$new_n2450_
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:51"
.param LUT_INIT 0000000000001100
.gate SB_LUT4 I0=$false I1=$abc$44715$auto$simplemap.cc:127:simplemap_reduce$25452[1]_new_inv_ I2=$abc$44715$techmap$techmap\common.pb.$procmux$14444.$and$/home/mb/fpga-toolchain/yosys/bin/../share/yosys/techmap.v:434$18188_Y[2]_new_ I3=$abc$44715$new_n2450_ O=$abc$44715$techmap$techmap\common.pb.$procmux$14444.$ternary$/home/mb/fpga-toolchain/yosys/bin/../share/yosys/techmap.v:445$18186_Y[2]
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:51"
.param LUT_INIT 1111111111110011
.gate SB_LUT4 I0=$false I1=$abc$44715$techmap$techmap\common.pb.$procmux$14444.$and$/home/mb/fpga-toolchain/yosys/bin/../share/yosys/techmap.v:434$18189_Y[2]_new_ I2=$abc$44715$auto$simplemap.cc:309:simplemap_lut$17319_new_ I3=common.pb.spi.rx_irq_r O=$abc$44715$auto$simplemap.cc:127:simplemap_reduce$25452[1]_new_inv_
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:51"
.param LUT_INIT 0000001100110011
.gate SB_LUT4 I0=$false I1=$abc$44715$techmap$techmap\common.pb.$procmux$14541.$and$/home/mb/fpga-toolchain/yosys/bin/../share/yosys/techmap.v:434$17951_Y_new_ I2=common.pb.tx_buf_wr I3=$abc$44715$auto$opt_reduce.cc:132:opt_mux$15866_new_inv_ O=$abc$44715$techmap$techmap\common.pb.$procmux$14541.$ternary$/home/mb/fpga-toolchain/yosys/bin/../share/yosys/techmap.v:445$17949_Y
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:51"
.param LUT_INIT 1100110011111100
.gate SB_LUT4 I0=$false I1=$false I2=$abc$44715$auto$simplemap.cc:250:simplemap_eqne$35177[4]_new_inv_ I3=$abc$44715$techmap\common.pb.$procmux$14552_Y_new_ O=$abc$44715$techmap$techmap\common.pb.$procmux$14541.$and$/home/mb/fpga-toolchain/yosys/bin/../share/yosys/techmap.v:434$17951_Y_new_
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:46"
.param LUT_INIT 1111000000000000
.gate SB_LUT4 I0=$false I1=$false I2=$abc$44715$auto$simplemap.cc:127:simplemap_reduce$35185[1]_new_inv_ I3=$abc$44715$auto$simplemap.cc:250:simplemap_eqne$35177[1]_new_ O=$abc$44715$techmap\common.pb.$procmux$14552_Y_new_
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:46"
.param LUT_INIT 0000000011110000
.gate SB_LUT4 I0=$false I1=$abc$44715$new_n2457_ I2=common.pb.tx_buf_wr_data[0] I3=$abc$44715$techmap$techmap\common.pb.$procmux$14541.$and$/home/mb/fpga-toolchain/yosys/bin/../share/yosys/techmap.v:434$17951_Y_new_ O=$abc$44715$techmap$techmap\common.pb.$procmux$14563.$ternary$/home/mb/fpga-toolchain/yosys/bin/../share/yosys/techmap.v:445$17894_Y[0]
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:51"
.param LUT_INIT 0011001100110000
.gate SB_LUT4 I0=$abc$44715$auto$opt_reduce.cc:132:opt_mux$15868_new_inv_ I1=$abc$44715$auto$simplemap.cc:250:simplemap_eqne$35177[4]_new_inv_ I2=$abc$44715$techmap\common.pb.$procmux$14552_Y_new_ I3=common.pb.spi.rx_data_r[0] O=$abc$44715$new_n2457_
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:56"
.param LUT_INIT 0010001010100010
.gate SB_LUT4 I0=$false I1=common.pb.spirx_state[1] I2=common.pb.spirx_state[2] I3=common.pb.spirx_state[0] O=$abc$44715$auto$opt_reduce.cc:132:opt_mux$15868_new_inv_
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:51"
.param LUT_INIT 1100000000001100
.gate SB_LUT4 I0=$false I1=$abc$44715$new_n2460_ I2=common.pb.tx_buf_wr_data[1] I3=$abc$44715$techmap$techmap\common.pb.$procmux$14541.$and$/home/mb/fpga-toolchain/yosys/bin/../share/yosys/techmap.v:434$17951_Y_new_ O=$abc$44715$techmap$techmap\common.pb.$procmux$14563.$ternary$/home/mb/fpga-toolchain/yosys/bin/../share/yosys/techmap.v:445$17894_Y[1]
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:51"
.param LUT_INIT 0011001100110000
.gate SB_LUT4 I0=$abc$44715$auto$opt_reduce.cc:132:opt_mux$15868_new_inv_ I1=$abc$44715$auto$simplemap.cc:250:simplemap_eqne$35177[4]_new_inv_ I2=$abc$44715$techmap\common.pb.$procmux$14552_Y_new_ I3=common.pb.spi.rx_data_r[1] O=$abc$44715$new_n2460_
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:56"
.param LUT_INIT 0010001010100010
.gate SB_LUT4 I0=$false I1=$abc$44715$new_n2462_ I2=common.pb.tx_buf_wr_data[2] I3=$abc$44715$techmap$techmap\common.pb.$procmux$14541.$and$/home/mb/fpga-toolchain/yosys/bin/../share/yosys/techmap.v:434$17951_Y_new_ O=$abc$44715$techmap$techmap\common.pb.$procmux$14563.$ternary$/home/mb/fpga-toolchain/yosys/bin/../share/yosys/techmap.v:445$17894_Y[2]
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:51"
.param LUT_INIT 0011001100110000
.gate SB_LUT4 I0=$abc$44715$auto$opt_reduce.cc:132:opt_mux$15868_new_inv_ I1=$abc$44715$auto$simplemap.cc:250:simplemap_eqne$35177[4]_new_inv_ I2=$abc$44715$techmap\common.pb.$procmux$14552_Y_new_ I3=common.pb.spi.rx_data_r[2] O=$abc$44715$new_n2462_
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:56"
.param LUT_INIT 0010001010100010
.gate SB_LUT4 I0=$false I1=$abc$44715$new_n2464_ I2=common.pb.tx_buf_wr_data[3] I3=$abc$44715$techmap$techmap\common.pb.$procmux$14541.$and$/home/mb/fpga-toolchain/yosys/bin/../share/yosys/techmap.v:434$17951_Y_new_ O=$abc$44715$techmap$techmap\common.pb.$procmux$14563.$ternary$/home/mb/fpga-toolchain/yosys/bin/../share/yosys/techmap.v:445$17894_Y[3]
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:51"
.param LUT_INIT 0011001100110000
.gate SB_LUT4 I0=$abc$44715$auto$opt_reduce.cc:132:opt_mux$15868_new_inv_ I1=$abc$44715$auto$simplemap.cc:250:simplemap_eqne$35177[4]_new_inv_ I2=$abc$44715$techmap\common.pb.$procmux$14552_Y_new_ I3=common.pb.spi.rx_data_r[3] O=$abc$44715$new_n2464_
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:56"
.param LUT_INIT 0010001010100010
.gate SB_LUT4 I0=$false I1=$abc$44715$new_n2466_ I2=common.pb.tx_buf_wr_data[4] I3=$abc$44715$techmap$techmap\common.pb.$procmux$14541.$and$/home/mb/fpga-toolchain/yosys/bin/../share/yosys/techmap.v:434$17951_Y_new_ O=$abc$44715$techmap$techmap\common.pb.$procmux$14563.$ternary$/home/mb/fpga-toolchain/yosys/bin/../share/yosys/techmap.v:445$17894_Y[4]
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:51"
.param LUT_INIT 0011001100110000
.gate SB_LUT4 I0=$abc$44715$auto$opt_reduce.cc:132:opt_mux$15868_new_inv_ I1=$abc$44715$auto$simplemap.cc:250:simplemap_eqne$35177[4]_new_inv_ I2=$abc$44715$techmap\common.pb.$procmux$14552_Y_new_ I3=common.pb.spi.rx_data_r[4] O=$abc$44715$new_n2466_
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:56"
.param LUT_INIT 0010001010100010
.gate SB_LUT4 I0=$false I1=$abc$44715$new_n2468_ I2=common.pb.tx_buf_wr_data[5] I3=$abc$44715$techmap$techmap\common.pb.$procmux$14541.$and$/home/mb/fpga-toolchain/yosys/bin/../share/yosys/techmap.v:434$17951_Y_new_ O=$abc$44715$techmap$techmap\common.pb.$procmux$14563.$ternary$/home/mb/fpga-toolchain/yosys/bin/../share/yosys/techmap.v:445$17894_Y[5]
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:51"
.param LUT_INIT 0011001100110000
.gate SB_LUT4 I0=$abc$44715$auto$opt_reduce.cc:132:opt_mux$15868_new_inv_ I1=$abc$44715$auto$simplemap.cc:250:simplemap_eqne$35177[4]_new_inv_ I2=$abc$44715$techmap\common.pb.$procmux$14552_Y_new_ I3=common.pb.spi.rx_data_r[5] O=$abc$44715$new_n2468_
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:56"
.param LUT_INIT 0010001010100010
.gate SB_LUT4 I0=$false I1=$abc$44715$new_n2470_ I2=common.pb.tx_buf_wr_data[6] I3=$abc$44715$techmap$techmap\common.pb.$procmux$14541.$and$/home/mb/fpga-toolchain/yosys/bin/../share/yosys/techmap.v:434$17951_Y_new_ O=$abc$44715$techmap$techmap\common.pb.$procmux$14563.$ternary$/home/mb/fpga-toolchain/yosys/bin/../share/yosys/techmap.v:445$17894_Y[6]
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:51"
.param LUT_INIT 0011001100110000
.gate SB_LUT4 I0=$abc$44715$auto$opt_reduce.cc:132:opt_mux$15868_new_inv_ I1=$abc$44715$auto$simplemap.cc:250:simplemap_eqne$35177[4]_new_inv_ I2=$abc$44715$techmap\common.pb.$procmux$14552_Y_new_ I3=common.pb.spi.rx_data_r[6] O=$abc$44715$new_n2470_
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:56"
.param LUT_INIT 0010001010100010
.gate SB_LUT4 I0=$false I1=$abc$44715$new_n2472_ I2=common.pb.tx_buf_wr_data[7] I3=$abc$44715$techmap$techmap\common.pb.$procmux$14541.$and$/home/mb/fpga-toolchain/yosys/bin/../share/yosys/techmap.v:434$17951_Y_new_ O=$abc$44715$techmap$techmap\common.pb.$procmux$14563.$ternary$/home/mb/fpga-toolchain/yosys/bin/../share/yosys/techmap.v:445$17894_Y[7]
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:51"
.param LUT_INIT 0011001100110000
.gate SB_LUT4 I0=$abc$44715$auto$opt_reduce.cc:132:opt_mux$15868_new_inv_ I1=$abc$44715$auto$simplemap.cc:250:simplemap_eqne$35177[4]_new_inv_ I2=$abc$44715$techmap\common.pb.$procmux$14552_Y_new_ I3=common.pb.spi.rx_data_r[7] O=$abc$44715$new_n2472_
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:56"
.param LUT_INIT 0010001010100010
.gate SB_LUT4 I0=$false I1=$abc$44715$new_n2475_ I2=common.pb.tx_buf_wr_addr[0] I3=$abc$44715$new_n2474_ O=$abc$44715$techmap$techmap\common.pb.$procmux$14583.$ternary$/home/mb/fpga-toolchain/yosys/bin/../share/yosys/techmap.v:445$17894_Y[0]
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:51"
.param LUT_INIT 1100110011111100
.gate SB_LUT4 I0=$false I1=$abc$44715$auto$opt_reduce.cc:132:opt_mux$15866_new_inv_ I2=$abc$44715$auto$opt_reduce.cc:132:opt_mux$15904_new_inv_ I3=common.pb.tx_buf_wr O=$abc$44715$new_n2474_
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:51"
.param LUT_INIT 1100110011000000
.gate SB_LUT4 I0=$false I1=common.pb.tx_buf_wr_addr_next[0] I2=common.pb.tx_buf_wr I3=$abc$44715$auto$opt_reduce.cc:132:opt_mux$15904_new_inv_ O=$abc$44715$new_n2475_
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:51"
.param LUT_INIT 0000000011000000
.gate SB_LUT4 I0=$false I1=$abc$44715$new_n2477_ I2=common.pb.tx_buf_wr_addr[1] I3=$abc$44715$new_n2474_ O=$abc$44715$techmap$techmap\common.pb.$procmux$14583.$ternary$/home/mb/fpga-toolchain/yosys/bin/../share/yosys/techmap.v:445$17894_Y[1]
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:51"
.param LUT_INIT 1100110011111100
.gate SB_LUT4 I0=common.pb.tx_buf_wr I1=common.pb.tx_buf_wr_addr[1] I2=common.pb.tx_buf_wr_addr[0] I3=$abc$44715$auto$opt_reduce.cc:132:opt_mux$15904_new_inv_ O=$abc$44715$new_n2477_
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:56"
.param LUT_INIT 0000000000101000
.gate SB_LUT4 I0=$false I1=$abc$44715$new_n2479_ I2=common.pb.tx_buf_wr_addr[2] I3=$abc$44715$new_n2474_ O=$abc$44715$techmap$techmap\common.pb.$procmux$14583.$ternary$/home/mb/fpga-toolchain/yosys/bin/../share/yosys/techmap.v:445$17894_Y[2]
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:51"
.param LUT_INIT 1100110011111100
.gate SB_LUT4 I0=$false I1=common.pb.tx_buf_wr_addr_next[2] I2=common.pb.tx_buf_wr I3=$abc$44715$auto$opt_reduce.cc:132:opt_mux$15904_new_inv_ O=$abc$44715$new_n2479_
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:51"
.param LUT_INIT 0000000011000000
.gate SB_LUT4 I0=$false I1=$abc$44715$new_n2481_ I2=common.pb.tx_buf_wr_addr[3] I3=$abc$44715$new_n2474_ O=$abc$44715$techmap$techmap\common.pb.$procmux$14583.$ternary$/home/mb/fpga-toolchain/yosys/bin/../share/yosys/techmap.v:445$17894_Y[3]
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:51"
.param LUT_INIT 1100110011111100
.gate SB_LUT4 I0=$false I1=common.pb.tx_buf_wr_addr_next[3] I2=common.pb.tx_buf_wr I3=$abc$44715$auto$opt_reduce.cc:132:opt_mux$15904_new_inv_ O=$abc$44715$new_n2481_
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:51"
.param LUT_INIT 0000000011000000
.gate SB_LUT4 I0=$false I1=$abc$44715$new_n2483_ I2=common.pb.tx_buf_wr_addr[4] I3=$abc$44715$new_n2474_ O=$abc$44715$techmap$techmap\common.pb.$procmux$14583.$ternary$/home/mb/fpga-toolchain/yosys/bin/../share/yosys/techmap.v:445$17894_Y[4]
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:51"
.param LUT_INIT 1100110011111100
.gate SB_LUT4 I0=$false I1=common.pb.tx_buf_wr_addr_next[4] I2=common.pb.tx_buf_wr I3=$abc$44715$auto$opt_reduce.cc:132:opt_mux$15904_new_inv_ O=$abc$44715$new_n2483_
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:51"
.param LUT_INIT 0000000011000000
.gate SB_LUT4 I0=$false I1=$abc$44715$new_n2485_ I2=common.pb.tx_buf_wr_addr[5] I3=$abc$44715$new_n2474_ O=$abc$44715$techmap$techmap\common.pb.$procmux$14583.$ternary$/home/mb/fpga-toolchain/yosys/bin/../share/yosys/techmap.v:445$17894_Y[5]
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:51"
.param LUT_INIT 1100110011111100
.gate SB_LUT4 I0=$false I1=common.pb.tx_buf_wr_addr_next[5] I2=common.pb.tx_buf_wr I3=$abc$44715$auto$opt_reduce.cc:132:opt_mux$15904_new_inv_ O=$abc$44715$new_n2485_
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:51"
.param LUT_INIT 0000000011000000
.gate SB_LUT4 I0=$false I1=$abc$44715$new_n2487_ I2=common.pb.tx_buf_wr_addr[6] I3=$abc$44715$new_n2474_ O=$abc$44715$techmap$techmap\common.pb.$procmux$14583.$ternary$/home/mb/fpga-toolchain/yosys/bin/../share/yosys/techmap.v:445$17894_Y[6]
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:51"
.param LUT_INIT 1100110011111100
.gate SB_LUT4 I0=$false I1=common.pb.tx_buf_wr_addr_next[6] I2=common.pb.tx_buf_wr I3=$abc$44715$auto$opt_reduce.cc:132:opt_mux$15904_new_inv_ O=$abc$44715$new_n2487_
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:51"
.param LUT_INIT 0000000011000000
.gate SB_LUT4 I0=$false I1=$abc$44715$new_n2489_ I2=common.pb.tx_buf_wr_addr[7] I3=$abc$44715$new_n2474_ O=$abc$44715$techmap$techmap\common.pb.$procmux$14583.$ternary$/home/mb/fpga-toolchain/yosys/bin/../share/yosys/techmap.v:445$17894_Y[7]
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:51"
.param LUT_INIT 1100110011111100
.gate SB_LUT4 I0=$false I1=common.pb.tx_buf_wr_addr_next[7] I2=common.pb.tx_buf_wr I3=$abc$44715$auto$opt_reduce.cc:132:opt_mux$15904_new_inv_ O=$abc$44715$new_n2489_
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:51"
.param LUT_INIT 0000000011000000
.gate SB_LUT4 I0=$false I1=$false I2=common.pb.spirx_ctrl_data[5] I3=common.pb.spirx_ctrl_data[0] O=$abc$44715$auto$simplemap.cc:309:simplemap_lut$26877[0]
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:46"
.param LUT_INIT 0000111111110000
.gate SB_LUT4 I0=$false I1=$false I2=$abc$44715$techmap\common.pb.$eq$profibus_phy_mod.v:990$6250_Y_new_ I3=common.pb.rx_buf_wr O=PIN_20
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:46"
.param LUT_INIT 1111111100001111
.gate SB_LUT4 I0=$false I1=$false I2=common.pb.uart.arb_mod.rx I3=common.pb.uart.rx_mod.rx_frame_error_start O=$abc$44715$techmap\common.pb.uart.rx_mod.$0\rx_frame_error[0:0]
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:46"
.param LUT_INIT 1111111100001111
.gate SB_LUT4 I0=$abc$44715$auto$simplemap.cc:250:simplemap_eqne$35177[4]_new_inv_ I1=common.pb.spirx_len_valid I2=common.pb.spi.rx_irq_r I3=common.pb.spirx_lencalc_new O=$abc$44715$techmap$techmap\common.pb.$procmux$14236.$and$/home/mb/fpga-toolchain/yosys/bin/../share/yosys/techmap.v:434$17950_Y
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:56"
.param LUT_INIT 1010100000100000
.gate SB_LUT4 I0=$abc$44715$auto$simplemap.cc:250:simplemap_eqne$35177[4]_new_inv_ I1=common.pb.spirx_len_valid I2=common.pb.spirx_lencalc_byte[0] I3=common.pb.spi.rx_data_r[0] O=$abc$44715$techmap$techmap\common.pb.$procmux$14250.$and$/home/mb/fpga-toolchain/yosys/bin/../share/yosys/techmap.v:434$17895_Y[0]
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:56"
.param LUT_INIT 1010001010000000
.gate SB_LUT4 I0=$abc$44715$auto$simplemap.cc:250:simplemap_eqne$35177[4]_new_inv_ I1=common.pb.spirx_len_valid I2=common.pb.spirx_lencalc_byte[1] I3=common.pb.spi.rx_data_r[1] O=$abc$44715$techmap$techmap\common.pb.$procmux$14250.$and$/home/mb/fpga-toolchain/yosys/bin/../share/yosys/techmap.v:434$17895_Y[1]
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:56"
.param LUT_INIT 1010001010000000
.gate SB_LUT4 I0=$abc$44715$auto$simplemap.cc:250:simplemap_eqne$35177[4]_new_inv_ I1=common.pb.spirx_len_valid I2=common.pb.spi.rx_data_r[2] I3=common.pb.spirx_lencalc_byte[2] O=$abc$44715$techmap$techmap\common.pb.$procmux$14250.$and$/home/mb/fpga-toolchain/yosys/bin/../share/yosys/techmap.v:434$17895_Y[2]
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:56"
.param LUT_INIT 1010100000100000
.gate SB_LUT4 I0=$abc$44715$auto$simplemap.cc:250:simplemap_eqne$35177[4]_new_inv_ I1=common.pb.spirx_len_valid I2=common.pb.spirx_lencalc_byte[3] I3=common.pb.spi.rx_data_r[3] O=$abc$44715$techmap$techmap\common.pb.$procmux$14250.$and$/home/mb/fpga-toolchain/yosys/bin/../share/yosys/techmap.v:434$17895_Y[3]
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:56"
.param LUT_INIT 1010001010000000
.gate SB_LUT4 I0=$abc$44715$auto$simplemap.cc:250:simplemap_eqne$35177[4]_new_inv_ I1=common.pb.spirx_len_valid I2=common.pb.spirx_lencalc_byte[4] I3=common.pb.spi.rx_data_r[4] O=$abc$44715$techmap$techmap\common.pb.$procmux$14250.$and$/home/mb/fpga-toolchain/yosys/bin/../share/yosys/techmap.v:434$17895_Y[4]
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:56"
.param LUT_INIT 1010001010000000
.gate SB_LUT4 I0=$abc$44715$auto$simplemap.cc:250:simplemap_eqne$35177[4]_new_inv_ I1=common.pb.spirx_len_valid I2=common.pb.spirx_lencalc_byte[5] I3=common.pb.spi.rx_data_r[5] O=$abc$44715$techmap$techmap\common.pb.$procmux$14250.$and$/home/mb/fpga-toolchain/yosys/bin/../share/yosys/techmap.v:434$17895_Y[5]
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:56"
.param LUT_INIT 1010001010000000
.gate SB_LUT4 I0=$abc$44715$auto$simplemap.cc:250:simplemap_eqne$35177[4]_new_inv_ I1=common.pb.spirx_len_valid I2=common.pb.spirx_lencalc_byte[6] I3=common.pb.spi.rx_data_r[6] O=$abc$44715$techmap$techmap\common.pb.$procmux$14250.$and$/home/mb/fpga-toolchain/yosys/bin/../share/yosys/techmap.v:434$17895_Y[6]
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:56"
.param LUT_INIT 1010001010000000
.gate SB_LUT4 I0=$abc$44715$auto$simplemap.cc:250:simplemap_eqne$35177[4]_new_inv_ I1=common.pb.spirx_len_valid I2=common.pb.spirx_lencalc_byte[7] I3=common.pb.spi.rx_data_r[7] O=$abc$44715$techmap$techmap\common.pb.$procmux$14250.$and$/home/mb/fpga-toolchain/yosys/bin/../share/yosys/techmap.v:434$17895_Y[7]
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:56"
.param LUT_INIT 1010001010000000
.gate SB_LUT4 I0=$false I1=$false I2=$false I3=$abc$44715$auto$ice40_ffinit.cc:141:execute$43999 O=common.pb.timer_idle_saved[1]
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:41"
.param LUT_INIT 0000000011111111
.gate SB_LUT4 I0=$false I1=$false I2=$false I3=$abc$44715$auto$ice40_ffinit.cc:141:execute$44003 O=common.pb.timer_idle_saved[2]
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:41"
.param LUT_INIT 0000000011111111
.gate SB_LUT4 I0=$false I1=$false I2=$false I3=$abc$44715$auto$ice40_ffinit.cc:141:execute$44007 O=common.pb.timer_idle_saved[3]
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:41"
.param LUT_INIT 0000000011111111
.gate SB_LUT4 I0=$false I1=$false I2=$false I3=$abc$44715$auto$ice40_ffinit.cc:141:execute$44011 O=common.pb.timer_idle_saved[4]
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:41"
.param LUT_INIT 0000000011111111
.gate SB_LUT4 I0=$false I1=$false I2=$false I3=$abc$44715$auto$ice40_ffinit.cc:141:execute$44015 O=common.pb.timer_idle_saved[5]
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:41"
.param LUT_INIT 0000000011111111
.gate SB_LUT4 I0=$false I1=$false I2=$false I3=$abc$44715$auto$ice40_ffinit.cc:141:execute$44019 O=common.pb.timer_idle_saved[6]
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:41"
.param LUT_INIT 0000000011111111
.gate SB_LUT4 I0=$false I1=$false I2=$false I3=$abc$44715$auto$ice40_ffinit.cc:141:execute$44023 O=common.pb.timer_idle_saved[7]
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:41"
.param LUT_INIT 0000000011111111
.gate SB_LUT4 I0=$false I1=$false I2=$false I3=$abc$44715$auto$ice40_ffinit.cc:141:execute$44027 O=common.pb.timer_idle_saved[8]
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:41"
.param LUT_INIT 0000000011111111
.gate SB_LUT4 I0=$false I1=$false I2=$false I3=$abc$44715$auto$ice40_ffinit.cc:141:execute$44031 O=common.pb.timer_idle_saved[9]
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:41"
.param LUT_INIT 0000000011111111
.gate SB_LUT4 I0=$false I1=$false I2=$false I3=$abc$44715$auto$ice40_ffinit.cc:141:execute$44035 O=common.pb.timer_idle_saved[10]
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:41"
.param LUT_INIT 0000000011111111
.gate SB_LUT4 I0=$false I1=$false I2=$false I3=$abc$44715$auto$ice40_ffinit.cc:141:execute$44039 O=common.pb.timer_idle_saved[11]
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:41"
.param LUT_INIT 0000000011111111
.gate SB_LUT4 I0=$false I1=$false I2=$false I3=$abc$44715$auto$ice40_ffinit.cc:141:execute$44043 O=common.pb.timer_idle_saved[12]
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:41"
.param LUT_INIT 0000000011111111
.gate SB_LUT4 I0=$false I1=$false I2=$false I3=$abc$44715$auto$ice40_ffinit.cc:141:execute$44047 O=common.pb.timer_idle_saved[13]
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:41"
.param LUT_INIT 0000000011111111
.gate SB_LUT4 I0=$false I1=$false I2=$false I3=$abc$44715$auto$ice40_ffinit.cc:141:execute$44051 O=common.pb.timer_idle_saved[14]
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:41"
.param LUT_INIT 0000000011111111
.gate SB_LUT4 I0=$false I1=$false I2=$false I3=$abc$44715$auto$ice40_ffinit.cc:141:execute$44055 O=common.pb.timer_idle_saved[15]
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:41"
.param LUT_INIT 0000000011111111
.gate SB_LUT4 I0=$false I1=$false I2=$false I3=$abc$44715$auto$ice40_ffinit.cc:141:execute$44059 O=common.pb.timer_idle_saved[16]
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:41"
.param LUT_INIT 0000000011111111
.gate SB_LUT4 I0=$false I1=$false I2=$false I3=$abc$44715$auto$ice40_ffinit.cc:141:execute$44063 O=common.pb.timer_idle_saved[17]
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:41"
.param LUT_INIT 0000000011111111
.gate SB_LUT4 I0=$false I1=$false I2=$false I3=$abc$44715$auto$ice40_ffinit.cc:141:execute$44067 O=common.pb.timer_idle_saved[18]
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:41"
.param LUT_INIT 0000000011111111
.gate SB_LUT4 I0=$false I1=$false I2=$false I3=$abc$44715$auto$ice40_ffinit.cc:141:execute$44071 O=common.pb.timer_idle_saved[19]
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:41"
.param LUT_INIT 0000000011111111
.gate SB_LUT4 I0=$false I1=$false I2=$false I3=$abc$44715$auto$ice40_ffinit.cc:141:execute$44075 O=common.pb.timer_idle_saved[20]
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:41"
.param LUT_INIT 0000000011111111
.gate SB_LUT4 I0=$false I1=$false I2=$false I3=$abc$44715$auto$ice40_ffinit.cc:141:execute$44079 O=common.pb.timer_idle_saved[21]
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:41"
.param LUT_INIT 0000000011111111
.gate SB_LUT4 I0=$false I1=$false I2=$false I3=$abc$44715$auto$ice40_ffinit.cc:141:execute$44083 O=common.pb.timer_idle_saved[22]
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:41"
.param LUT_INIT 0000000011111111
.gate SB_LUT4 I0=$false I1=$false I2=$false I3=$abc$44715$auto$ice40_ffinit.cc:141:execute$44087 O=common.pb.timer_idle_saved[23]
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:41"
.param LUT_INIT 0000000011111111
.gate SB_LUT4 I0=$false I1=$false I2=$false I3=$abc$44715$auto$ice40_ffinit.cc:141:execute$44091 O=common.pb.timer_idle_saved[0]
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:41"
.param LUT_INIT 0000000011111111
.gate SB_LUT4 I0=$false I1=$false I2=$false I3=$abc$44715$auto$ice40_ffinit.cc:141:execute$44095 O=PIN_15
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:41"
.param LUT_INIT 0000000011111111
.gate SB_LUT4 I0=$false I1=$false I2=$false I3=common.pb.n_reset O=$abc$44715$auto$rtlil.cc:1969:NotGate$44099
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:41"
.param LUT_INIT 0000000011111111
.gate SB_LUT4 I0=$false I1=$false I2=$false I3=common.pb.uart.tx_mod.symclk_n_reset O=$abc$44715$auto$rtlil.cc:1969:NotGate$44103
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:41"
.param LUT_INIT 0000000011111111
.gate SB_LUT4 I0=$false I1=$false I2=$false I3=$abc$44715$auto$dff2dffe.cc:158:make_patterns_logic$29217 O=$abc$44715$auto$rtlil.cc:1969:NotGate$44101
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:41"
.param LUT_INIT 0000000011111111
.gate SB_LUT4 I0=$false I1=$false I2=$false I3=common.pb.uart.rx_mod.symclk_n_reset O=$abc$44715$auto$rtlil.cc:1969:NotGate$44655
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:41"
.param LUT_INIT 0000000011111111
.gate SB_LUT4 I0=$false I1=$false I2=$false I3=common.pb.spirx_bytecount[7] O=$abc$44715$auto$alumacc.cc:474:replace_alu$16083.BB[7]
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:41"
.param LUT_INIT 0000000011111111
.gate SB_LUT4 I0=$false I1=$false I2=$false I3=common.pb.spirx_bytecount[6] O=$abc$44715$auto$alumacc.cc:474:replace_alu$16083.BB[6]
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:41"
.param LUT_INIT 0000000011111111
.gate SB_LUT4 I0=$false I1=$false I2=$false I3=common.pb.spirx_bytecount[5] O=$abc$44715$auto$alumacc.cc:474:replace_alu$16083.BB[5]
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:41"
.param LUT_INIT 0000000011111111
.gate SB_LUT4 I0=$false I1=$false I2=$false I3=common.pb.spirx_bytecount[4] O=$abc$44715$auto$alumacc.cc:474:replace_alu$16083.BB[4]
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:41"
.param LUT_INIT 0000000011111111
.gate SB_LUT4 I0=$false I1=$false I2=$false I3=common.pb.spirx_bytecount[3] O=$abc$44715$auto$alumacc.cc:474:replace_alu$16083.BB[3]
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:41"
.param LUT_INIT 0000000011111111
.gate SB_LUT4 I0=$false I1=$false I2=$false I3=common.pb.spirx_bytecount[2] O=$abc$44715$auto$alumacc.cc:474:replace_alu$16083.BB[2]
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:41"
.param LUT_INIT 0000000011111111
.gate SB_LUT4 I0=$false I1=$false I2=$false I3=common.pb.uart_clks_per_sym[23] O=$abc$44715$auto$alumacc.cc:474:replace_alu$16007.BB[23]
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:41"
.param LUT_INIT 0000000011111111
.gate SB_LUT4 I0=$false I1=$false I2=$false I3=common.pb.uart_clks_per_sym[22] O=$abc$44715$auto$alumacc.cc:474:replace_alu$16007.BB[22]
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:41"
.param LUT_INIT 0000000011111111
.gate SB_LUT4 I0=$false I1=$false I2=$false I3=common.pb.uart_clks_per_sym[21] O=$abc$44715$auto$alumacc.cc:474:replace_alu$16007.BB[21]
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:41"
.param LUT_INIT 0000000011111111
.gate SB_LUT4 I0=$false I1=$false I2=$false I3=common.pb.uart_clks_per_sym[20] O=$abc$44715$auto$alumacc.cc:474:replace_alu$16007.BB[20]
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:41"
.param LUT_INIT 0000000011111111
.gate SB_LUT4 I0=$false I1=$false I2=$false I3=common.pb.uart_clks_per_sym[19] O=$abc$44715$auto$alumacc.cc:474:replace_alu$16007.BB[19]
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:41"
.param LUT_INIT 0000000011111111
.gate SB_LUT4 I0=$false I1=$false I2=$false I3=common.pb.uart_clks_per_sym[18] O=$abc$44715$auto$alumacc.cc:474:replace_alu$16007.BB[18]
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:41"
.param LUT_INIT 0000000011111111
.gate SB_LUT4 I0=$false I1=$false I2=$false I3=common.pb.uart_clks_per_sym[17] O=$abc$44715$auto$alumacc.cc:474:replace_alu$16007.BB[17]
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:41"
.param LUT_INIT 0000000011111111
.gate SB_LUT4 I0=$false I1=$false I2=$false I3=common.pb.uart_clks_per_sym[16] O=$abc$44715$auto$alumacc.cc:474:replace_alu$16007.BB[16]
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:41"
.param LUT_INIT 0000000011111111
.gate SB_LUT4 I0=$false I1=$false I2=$false I3=common.pb.uart_clks_per_sym[15] O=$abc$44715$auto$alumacc.cc:474:replace_alu$16007.BB[15]
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:41"
.param LUT_INIT 0000000011111111
.gate SB_LUT4 I0=$false I1=$false I2=$false I3=common.pb.uart_clks_per_sym[14] O=$abc$44715$auto$alumacc.cc:474:replace_alu$16007.BB[14]
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:41"
.param LUT_INIT 0000000011111111
.gate SB_LUT4 I0=$false I1=$false I2=$false I3=common.pb.uart_clks_per_sym[13] O=$abc$44715$auto$alumacc.cc:474:replace_alu$16007.BB[13]
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:41"
.param LUT_INIT 0000000011111111
.gate SB_LUT4 I0=$false I1=$false I2=$false I3=common.pb.uart_clks_per_sym[12] O=$abc$44715$auto$alumacc.cc:474:replace_alu$16007.BB[12]
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:41"
.param LUT_INIT 0000000011111111
.gate SB_LUT4 I0=$false I1=$false I2=$false I3=common.pb.uart_clks_per_sym[11] O=$abc$44715$auto$alumacc.cc:474:replace_alu$16007.BB[11]
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:41"
.param LUT_INIT 0000000011111111
.gate SB_LUT4 I0=$false I1=$false I2=$false I3=common.pb.uart_clks_per_sym[10] O=$abc$44715$auto$alumacc.cc:474:replace_alu$16007.BB[10]
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:41"
.param LUT_INIT 0000000011111111
.gate SB_LUT4 I0=$false I1=$false I2=$false I3=common.pb.uart_clks_per_sym[9] O=$abc$44715$auto$alumacc.cc:474:replace_alu$16007.BB[9]
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:41"
.param LUT_INIT 0000000011111111
.gate SB_LUT4 I0=$false I1=$false I2=$false I3=common.pb.uart_clks_per_sym[8] O=$abc$44715$auto$alumacc.cc:474:replace_alu$16007.BB[8]
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:41"
.param LUT_INIT 0000000011111111
.gate SB_LUT4 I0=$false I1=$false I2=$false I3=common.pb.uart_clks_per_sym[7] O=$abc$44715$auto$alumacc.cc:474:replace_alu$16007.BB[7]
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:41"
.param LUT_INIT 0000000011111111
.gate SB_LUT4 I0=$false I1=$false I2=$false I3=common.pb.uart_clks_per_sym[6] O=$abc$44715$auto$alumacc.cc:474:replace_alu$16007.BB[6]
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:41"
.param LUT_INIT 0000000011111111
.gate SB_LUT4 I0=$false I1=$false I2=$false I3=common.pb.uart_clks_per_sym[5] O=$abc$44715$auto$alumacc.cc:474:replace_alu$16007.BB[5]
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:41"
.param LUT_INIT 0000000011111111
.gate SB_LUT4 I0=$false I1=$false I2=$false I3=common.pb.uart_clks_per_sym[4] O=$abc$44715$auto$alumacc.cc:474:replace_alu$16007.BB[4]
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:41"
.param LUT_INIT 0000000011111111
.gate SB_LUT4 I0=$false I1=$false I2=$false I3=common.pb.uart_clks_per_sym[3] O=$abc$44715$auto$alumacc.cc:474:replace_alu$16007.BB[3]
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:41"
.param LUT_INIT 0000000011111111
.gate SB_LUT4 I0=$false I1=$false I2=$false I3=common.pb.uart_clks_per_sym[1] O=$abc$44715$auto$alumacc.cc:474:replace_alu$16007.BB[1]
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:41"
.param LUT_INIT 0000000011111111
.gate SB_LUT4 I0=$false I1=$false I2=$false I3=common.pb.uart_clks_per_sym[0] O=$abc$44715$auto$alumacc.cc:474:replace_alu$16007.BB[0]
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:41"
.param LUT_INIT 0000000011111111
.gate SB_LUT4 I0=$false I1=$false I2=$false I3=common.pb.spi.bit_count[5] O=$abc$44715$auto$alumacc.cc:474:replace_alu$16034.BB[5]
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:41"
.param LUT_INIT 0000000011111111
.gate SB_LUT4 I0=$false I1=$false I2=$false I3=common.pb.spi.bit_count[4] O=$abc$44715$auto$alumacc.cc:474:replace_alu$16034.BB[4]
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:41"
.param LUT_INIT 0000000011111111
.gate SB_LUT4 I0=$false I1=$false I2=$false I3=common.pb.spi.bit_count[2] O=$abc$44715$auto$alumacc.cc:474:replace_alu$16034.BB[2]
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:41"
.param LUT_INIT 0000000011111111
.gate SB_LUT4 I0=$false I1=$false I2=$false I3=common.pb.spi.bit_count[1] O=$abc$44715$auto$alumacc.cc:474:replace_alu$16034.BB[1]
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:41"
.param LUT_INIT 0000000011111111
.gate SB_LUT4 I0=$false I1=$false I2=$false I3=common.pb.spi.bit_count[0] O=$abc$44715$auto$alumacc.cc:474:replace_alu$16034.BB[0]
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:41"
.param LUT_INIT 0000000011111111
.gate SB_LUT4 I0=$false I1=$false I2=$false I3=common.pb.spitx_bytecount[3] O=$abc$44715$auto$alumacc.cc:474:replace_alu$16052.BB[3]
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:41"
.param LUT_INIT 0000000011111111
.gate SB_LUT4 I0=$false I1=$false I2=$false I3=common.pb.spitx_bytecount[2] O=$abc$44715$auto$alumacc.cc:474:replace_alu$16052.BB[2]
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:41"
.param LUT_INIT 0000000011111111
.gate SB_LUT4 I0=$false I1=$false I2=$false I3=common.pb.spitx_bytecount[0] O=$abc$44715$auto$alumacc.cc:474:replace_alu$16052.BB[0]
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:41"
.param LUT_INIT 0000000011111111
.gate SB_LUT4 I0=$false I1=$false I2=$false I3=common.pb.spitx_bytecount[7] O=$abc$44715$auto$alumacc.cc:474:replace_alu$16052.BB[7]
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:41"
.param LUT_INIT 0000000011111111
.gate SB_LUT4 I0=$false I1=$false I2=$false I3=common.pb.spitx_bytecount[6] O=$abc$44715$auto$alumacc.cc:474:replace_alu$16052.BB[6]
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:41"
.param LUT_INIT 0000000011111111
.gate SB_LUT4 I0=$false I1=$false I2=$false I3=common.pb.spitx_bytecount[5] O=$abc$44715$auto$alumacc.cc:474:replace_alu$16052.BB[5]
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:41"
.param LUT_INIT 0000000011111111
.gate SB_LUT4 I0=$false I1=$false I2=$false I3=common.pb.spitx_bytecount[4] O=$abc$44715$auto$alumacc.cc:474:replace_alu$16052.BB[4]
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:41"
.param LUT_INIT 0000000011111111
.gate SB_LUT4 I0=$false I1=$false I2=$false I3=common.pb.spitx_bytecount[1] O=$abc$44715$auto$alumacc.cc:474:replace_alu$16052.BB[1]
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:41"
.param LUT_INIT 0000000011111111
.gate SB_LUT4 I0=$false I1=$false I2=$false I3=common.pb.spirx_lencalc_byte[7] O=$abc$44715$auto$alumacc.cc:474:replace_alu$16025.BB[7]
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:41"
.param LUT_INIT 0000000011111111
.gate SB_LUT4 I0=$false I1=$false I2=$false I3=common.pb.spirx_lencalc_byte[6] O=$abc$44715$auto$alumacc.cc:474:replace_alu$16025.BB[6]
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:41"
.param LUT_INIT 0000000011111111
.gate SB_LUT4 I0=$false I1=$false I2=$false I3=common.pb.spirx_lencalc_byte[5] O=$abc$44715$auto$alumacc.cc:474:replace_alu$16025.BB[5]
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:41"
.param LUT_INIT 0000000011111111
.gate SB_LUT4 I0=$false I1=$false I2=$false I3=common.pb.spirx_lencalc_byte[4] O=$abc$44715$auto$alumacc.cc:474:replace_alu$16025.BB[4]
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:41"
.param LUT_INIT 0000000011111111
.gate SB_LUT4 I0=$false I1=$false I2=$false I3=common.pb.spirx_lencalc_byte[3] O=$abc$44715$auto$alumacc.cc:474:replace_alu$16025.BB[3]
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:41"
.param LUT_INIT 0000000011111111
.gate SB_LUT4 I0=$false I1=$false I2=$false I3=common.pb.spirx_lencalc_byte[1] O=$abc$44715$auto$alumacc.cc:474:replace_alu$16025.BB[1]
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:41"
.param LUT_INIT 0000000011111111
.gate SB_LUT4 I0=$false I1=$false I2=$false I3=common.pb.spirx_lencalc_byte[0] O=$abc$44715$auto$alumacc.cc:474:replace_alu$16025.BB[0]
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:41"
.param LUT_INIT 0000000011111111
.gate SB_LUT4 I0=$false I1=$false I2=$false I3=$abc$44715$auto$alumacc.cc:474:replace_alu$15981.B_buf[24] O=$abc$44715$auto$alumacc.cc:474:replace_alu$15981.BB[24]
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:41"
.param LUT_INIT 0000000011111111
.gate SB_LUT4 I0=$false I1=$false I2=$false I3=common.pb.tx_buf_rd_addr[1] O=$abc$44715$auto$simplemap.cc:309:simplemap_lut$25661[1]
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:41"
.param LUT_INIT 0000000011111111
.gate SB_LUT4 I0=$false I1=$false I2=$false I3=common.pb.rx_buf_rd_addr[1] O=$abc$44715$auto$simplemap.cc:309:simplemap_lut$25737[1]
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:41"
.param LUT_INIT 0000000011111111
.gate SB_LUT4 I0=$false I1=$false I2=$false I3=common.pb.spitx_ctrl_pending_ack O=$abc$44715$techmap\common.pb.$0\spitx_ctrl_pending[0:0]
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:41"
.param LUT_INIT 0000000011111111
.gate SB_LUT4 I0=$false I1=$false I2=$false I3=common.pb.spirx_ctrl_crcerr[1] O=$abc$44715$techmap\common.pb.$0\spirx_ctrl_crcerr[1:0][0]
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:41"
.param LUT_INIT 0000000011111111
.gate SB_LUT4 I0=$false I1=$false I2=$false I3=common.pb.tx_buf_overflow[1] O=$abc$44715$techmap\common.pb.$0\tx_buf_overflow[1:0][0]
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:41"
.param LUT_INIT 0000000011111111
.gate SB_LUT4 I0=$false I1=$false I2=$false I3=common.pb.rx_buf_overflow[1] O=$abc$44715$techmap\common.pb.$0\rx_buf_overflow[0:0]
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:41"
.param LUT_INIT 0000000011111111
.gate SB_LUT4 I0=$false I1=$false I2=$false I3=common.pb.rx_buf_wr O=$abc$44715$auto$opt_expr.cc:189:group_cell_inputs$16197
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:41"
.param LUT_INIT 0000000011111111
.gate SB_LUT4 I0=$false I1=$false I2=$false I3=PIN_13 O=$abc$44715$auto$rtlil.cc:1832:Not$15840
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:41"
.param LUT_INIT 0000000011111111
.gate SB_LUT4 I0=$false I1=$false I2=$false I3=common.pb.spi.bit_count[3] O=$abc$44715$auto$alumacc.cc:474:replace_alu$16034.BB[3]
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:41"
.param LUT_INIT 0000000011111111
.gate SB_LUT4 I0=$false I1=$false I2=$false I3=common.pb.spirx_lencalc_byte[2] O=$abc$44715$auto$alumacc.cc:474:replace_alu$16025.BB[2]
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:41"
.param LUT_INIT 0000000011111111
.gate SB_LUT4 I0=$false I1=$false I2=$false I3=common.pb.tsyn_clks[0] O=$abc$44715$auto$alumacc.cc:474:replace_alu$16105.BB[0]
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:41"
.param LUT_INIT 0000000011111111
.gate SB_LUT4 I0=$false I1=$false I2=$false I3=common.pb.tsyn_clks[1] O=$abc$44715$auto$alumacc.cc:474:replace_alu$16105.BB[1]
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:41"
.param LUT_INIT 0000000011111111
.gate SB_LUT4 I0=$false I1=$false I2=$false I3=common.pb.tsyn_clks[2] O=$abc$44715$auto$alumacc.cc:474:replace_alu$16105.BB[2]
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:41"
.param LUT_INIT 0000000011111111
.gate SB_LUT4 I0=$false I1=$false I2=$false I3=common.pb.tsyn_clks[3] O=$abc$44715$auto$alumacc.cc:474:replace_alu$16105.BB[3]
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:41"
.param LUT_INIT 0000000011111111
.gate SB_LUT4 I0=$false I1=$false I2=$false I3=common.pb.tsyn_clks[4] O=$abc$44715$auto$alumacc.cc:474:replace_alu$16105.BB[4]
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:41"
.param LUT_INIT 0000000011111111
.gate SB_LUT4 I0=$false I1=$false I2=$false I3=common.pb.tsyn_clks[5] O=$abc$44715$auto$alumacc.cc:474:replace_alu$16105.BB[5]
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:41"
.param LUT_INIT 0000000011111111
.gate SB_LUT4 I0=$false I1=$false I2=$false I3=common.pb.tsyn_clks[6] O=$abc$44715$auto$alumacc.cc:474:replace_alu$16105.BB[6]
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:41"
.param LUT_INIT 0000000011111111
.gate SB_LUT4 I0=$false I1=$false I2=$false I3=common.pb.tsyn_clks[7] O=$abc$44715$auto$alumacc.cc:474:replace_alu$16105.BB[7]
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:41"
.param LUT_INIT 0000000011111111
.gate SB_LUT4 I0=$false I1=$false I2=$false I3=common.pb.tsyn_clks[8] O=$abc$44715$auto$alumacc.cc:474:replace_alu$16105.BB[8]
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:41"
.param LUT_INIT 0000000011111111
.gate SB_LUT4 I0=$false I1=$false I2=$false I3=common.pb.tsyn_clks[9] O=$abc$44715$auto$alumacc.cc:474:replace_alu$16105.BB[9]
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:41"
.param LUT_INIT 0000000011111111
.gate SB_LUT4 I0=$false I1=$false I2=$false I3=common.pb.tsyn_clks[10] O=$abc$44715$auto$alumacc.cc:474:replace_alu$16105.BB[10]
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:41"
.param LUT_INIT 0000000011111111
.gate SB_LUT4 I0=$false I1=$false I2=$false I3=common.pb.tsyn_clks[11] O=$abc$44715$auto$alumacc.cc:474:replace_alu$16105.BB[11]
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:41"
.param LUT_INIT 0000000011111111
.gate SB_LUT4 I0=$false I1=$false I2=$false I3=common.pb.tsyn_clks[12] O=$abc$44715$auto$alumacc.cc:474:replace_alu$16105.BB[12]
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:41"
.param LUT_INIT 0000000011111111
.gate SB_LUT4 I0=$false I1=$false I2=$false I3=common.pb.tsyn_clks[13] O=$abc$44715$auto$alumacc.cc:474:replace_alu$16105.BB[13]
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:41"
.param LUT_INIT 0000000011111111
.gate SB_LUT4 I0=$false I1=$false I2=$false I3=common.pb.tsyn_clks[14] O=$abc$44715$auto$alumacc.cc:474:replace_alu$16105.BB[14]
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:41"
.param LUT_INIT 0000000011111111
.gate SB_LUT4 I0=$false I1=$false I2=$false I3=common.pb.tsyn_clks[15] O=$abc$44715$auto$alumacc.cc:474:replace_alu$16105.BB[15]
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:41"
.param LUT_INIT 0000000011111111
.gate SB_LUT4 I0=$false I1=$false I2=$false I3=common.pb.tsyn_clks[16] O=$abc$44715$auto$alumacc.cc:474:replace_alu$16105.BB[16]
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:41"
.param LUT_INIT 0000000011111111
.gate SB_LUT4 I0=$false I1=$false I2=$false I3=common.pb.tsyn_clks[17] O=$abc$44715$auto$alumacc.cc:474:replace_alu$16105.BB[17]
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:41"
.param LUT_INIT 0000000011111111
.gate SB_LUT4 I0=$false I1=$false I2=$false I3=common.pb.tsyn_clks[18] O=$abc$44715$auto$alumacc.cc:474:replace_alu$16105.BB[18]
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:41"
.param LUT_INIT 0000000011111111
.gate SB_LUT4 I0=$false I1=$false I2=$false I3=common.pb.tsyn_clks[19] O=$abc$44715$auto$alumacc.cc:474:replace_alu$16105.BB[19]
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:41"
.param LUT_INIT 0000000011111111
.gate SB_LUT4 I0=$false I1=$false I2=$false I3=common.pb.tsyn_clks[20] O=$abc$44715$auto$alumacc.cc:474:replace_alu$16105.BB[20]
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:41"
.param LUT_INIT 0000000011111111
.gate SB_LUT4 I0=$false I1=$false I2=$false I3=common.pb.tsyn_clks[21] O=$abc$44715$auto$alumacc.cc:474:replace_alu$16105.BB[21]
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:41"
.param LUT_INIT 0000000011111111
.gate SB_LUT4 I0=$false I1=$false I2=$false I3=common.pb.tsyn_clks[22] O=$abc$44715$auto$alumacc.cc:474:replace_alu$16105.BB[22]
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:41"
.param LUT_INIT 0000000011111111
.gate SB_LUT4 I0=$false I1=$false I2=$false I3=common.pb.tsyn_clks[23] O=$abc$44715$auto$alumacc.cc:474:replace_alu$16105.BB[23]
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:41"
.param LUT_INIT 0000000011111111
.gate SB_LUT4 I0=$false I1=$false I2=$false I3=common.pb.spirx_len[0] O=$abc$44715$auto$alumacc.cc:474:replace_alu$16092.BB[0]
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:41"
.param LUT_INIT 0000000011111111
.gate SB_LUT4 I0=$false I1=$false I2=$false I3=common.pb.spirx_len[1] O=$abc$44715$auto$alumacc.cc:474:replace_alu$16092.BB[1]
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:41"
.param LUT_INIT 0000000011111111
.gate SB_LUT4 I0=$false I1=$false I2=$false I3=common.pb.spirx_len[2] O=$abc$44715$auto$alumacc.cc:474:replace_alu$16092.BB[2]
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:41"
.param LUT_INIT 0000000011111111
.gate SB_LUT4 I0=$false I1=$false I2=$false I3=common.pb.spirx_len[3] O=$abc$44715$auto$alumacc.cc:474:replace_alu$16092.BB[3]
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:41"
.param LUT_INIT 0000000011111111
.gate SB_LUT4 I0=$false I1=$false I2=$false I3=common.pb.spirx_len[4] O=$abc$44715$auto$alumacc.cc:474:replace_alu$16092.BB[4]
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:41"
.param LUT_INIT 0000000011111111
.gate SB_LUT4 I0=$false I1=$false I2=$false I3=common.pb.spirx_len[5] O=$abc$44715$auto$alumacc.cc:474:replace_alu$16092.BB[5]
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:41"
.param LUT_INIT 0000000011111111
.gate SB_LUT4 I0=$false I1=$false I2=$false I3=common.pb.spirx_len[6] O=$abc$44715$auto$alumacc.cc:474:replace_alu$16092.BB[6]
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:41"
.param LUT_INIT 0000000011111111
.gate SB_LUT4 I0=$false I1=$false I2=$false I3=common.pb.spirx_len[7] O=$abc$44715$auto$alumacc.cc:474:replace_alu$16092.BB[7]
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:41"
.param LUT_INIT 0000000011111111
.gate SB_LUT4 I0=$false I1=$false I2=$false I3=common.pb.uart_clks_per_sym[2] O=$abc$44715$auto$alumacc.cc:474:replace_alu$16007.BB[2]
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:41"
.param LUT_INIT 0000000011111111
.gate SB_LUT4 I0=$false I1=$false I2=$false I3=$abc$44715$auto$alumacc.cc:474:replace_alu$15981.B_buf[0] O=$abc$44715$auto$alumacc.cc:474:replace_alu$15981.BB[0]
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:41"
.param LUT_INIT 0000000011111111
.gate SB_LUT4 I0=$false I1=$false I2=$false I3=$abc$44715$auto$alumacc.cc:474:replace_alu$15981.B_buf[2] O=$abc$44715$auto$alumacc.cc:474:replace_alu$15981.BB[2]
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:41"
.param LUT_INIT 0000000011111111
.gate SB_LUT4 I0=$false I1=$false I2=$false I3=$abc$44715$auto$alumacc.cc:474:replace_alu$15981.B_buf[3] O=$abc$44715$auto$alumacc.cc:474:replace_alu$15981.BB[3]
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:41"
.param LUT_INIT 0000000011111111
.gate SB_LUT4 I0=$false I1=$false I2=$false I3=$abc$44715$auto$alumacc.cc:474:replace_alu$15981.B_buf[4] O=$abc$44715$auto$alumacc.cc:474:replace_alu$15981.BB[4]
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:41"
.param LUT_INIT 0000000011111111
.gate SB_LUT4 I0=$false I1=$false I2=$false I3=$abc$44715$auto$alumacc.cc:474:replace_alu$15981.B_buf[5] O=$abc$44715$auto$alumacc.cc:474:replace_alu$15981.BB[5]
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:41"
.param LUT_INIT 0000000011111111
.gate SB_LUT4 I0=$false I1=$false I2=$false I3=$abc$44715$auto$alumacc.cc:474:replace_alu$15981.B_buf[6] O=$abc$44715$auto$alumacc.cc:474:replace_alu$15981.BB[6]
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:41"
.param LUT_INIT 0000000011111111
.gate SB_LUT4 I0=$false I1=$false I2=$false I3=$abc$44715$auto$alumacc.cc:474:replace_alu$15981.B_buf[7] O=$abc$44715$auto$alumacc.cc:474:replace_alu$15981.BB[7]
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:41"
.param LUT_INIT 0000000011111111
.gate SB_LUT4 I0=$false I1=$false I2=$false I3=$abc$44715$auto$alumacc.cc:474:replace_alu$15981.B_buf[8] O=$abc$44715$auto$alumacc.cc:474:replace_alu$15981.BB[8]
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:41"
.param LUT_INIT 0000000011111111
.gate SB_LUT4 I0=$false I1=$false I2=$false I3=$abc$44715$auto$alumacc.cc:474:replace_alu$15981.B_buf[9] O=$abc$44715$auto$alumacc.cc:474:replace_alu$15981.BB[9]
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:41"
.param LUT_INIT 0000000011111111
.gate SB_LUT4 I0=$false I1=$false I2=$false I3=$abc$44715$auto$alumacc.cc:474:replace_alu$15981.B_buf[10] O=$abc$44715$auto$alumacc.cc:474:replace_alu$15981.BB[10]
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:41"
.param LUT_INIT 0000000011111111
.gate SB_LUT4 I0=$false I1=$false I2=$false I3=$abc$44715$auto$alumacc.cc:474:replace_alu$15981.B_buf[11] O=$abc$44715$auto$alumacc.cc:474:replace_alu$15981.BB[11]
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:41"
.param LUT_INIT 0000000011111111
.gate SB_LUT4 I0=$false I1=$false I2=$false I3=$abc$44715$auto$alumacc.cc:474:replace_alu$15981.B_buf[12] O=$abc$44715$auto$alumacc.cc:474:replace_alu$15981.BB[12]
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:41"
.param LUT_INIT 0000000011111111
.gate SB_LUT4 I0=$false I1=$false I2=$false I3=$abc$44715$auto$alumacc.cc:474:replace_alu$15981.B_buf[13] O=$abc$44715$auto$alumacc.cc:474:replace_alu$15981.BB[13]
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:41"
.param LUT_INIT 0000000011111111
.gate SB_LUT4 I0=$false I1=$false I2=$false I3=$abc$44715$auto$alumacc.cc:474:replace_alu$15981.B_buf[14] O=$abc$44715$auto$alumacc.cc:474:replace_alu$15981.BB[14]
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:41"
.param LUT_INIT 0000000011111111
.gate SB_LUT4 I0=$false I1=$false I2=$false I3=$abc$44715$auto$alumacc.cc:474:replace_alu$15981.B_buf[15] O=$abc$44715$auto$alumacc.cc:474:replace_alu$15981.BB[15]
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:41"
.param LUT_INIT 0000000011111111
.gate SB_LUT4 I0=$false I1=$false I2=$false I3=$abc$44715$auto$alumacc.cc:474:replace_alu$15981.B_buf[16] O=$abc$44715$auto$alumacc.cc:474:replace_alu$15981.BB[16]
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:41"
.param LUT_INIT 0000000011111111
.gate SB_LUT4 I0=$false I1=$false I2=$false I3=$abc$44715$auto$alumacc.cc:474:replace_alu$15981.B_buf[17] O=$abc$44715$auto$alumacc.cc:474:replace_alu$15981.BB[17]
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:41"
.param LUT_INIT 0000000011111111
.gate SB_LUT4 I0=$false I1=$false I2=$false I3=$abc$44715$auto$alumacc.cc:474:replace_alu$15981.B_buf[18] O=$abc$44715$auto$alumacc.cc:474:replace_alu$15981.BB[18]
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:41"
.param LUT_INIT 0000000011111111
.gate SB_LUT4 I0=$false I1=$false I2=$false I3=$abc$44715$auto$alumacc.cc:474:replace_alu$15981.B_buf[20] O=$abc$44715$auto$alumacc.cc:474:replace_alu$15981.BB[20]
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:41"
.param LUT_INIT 0000000011111111
.gate SB_LUT4 I0=$false I1=$false I2=$false I3=$abc$44715$auto$alumacc.cc:474:replace_alu$15981.B_buf[22] O=$abc$44715$auto$alumacc.cc:474:replace_alu$15981.BB[22]
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:41"
.param LUT_INIT 0000000011111111
.gate SB_LUT4 I0=$false I1=$false I2=$false I3=$abc$44715$auto$alumacc.cc:474:replace_alu$15981.B_buf[19] O=$abc$44715$auto$alumacc.cc:474:replace_alu$15981.BB[19]
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:41"
.param LUT_INIT 0000000011111111
.gate SB_LUT4 I0=$false I1=$false I2=$false I3=$abc$44715$auto$alumacc.cc:474:replace_alu$15981.B_buf[21] O=$abc$44715$auto$alumacc.cc:474:replace_alu$15981.BB[21]
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:41"
.param LUT_INIT 0000000011111111
.gate SB_LUT4 I0=$false I1=$false I2=$false I3=$abc$44715$auto$alumacc.cc:474:replace_alu$15981.B_buf[23] O=$abc$44715$auto$alumacc.cc:474:replace_alu$15981.BB[23]
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:41"
.param LUT_INIT 0000000011111111
.gate SB_LUT4 I0=common.pb.uart.tx_mod.sym_count[2] I1=common.pb.uart.tx_mod.sym_count[1] I2=common.pb.uart.tx_mod.tx_buf[4] I3=common.pb.uart.tx_mod.tx_buf[0] O=$abc$44715$new_n2648_
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:56"
.param LUT_INIT 1110011010100010
.gate SB_LUT4 I0=$abc$44715$new_n2648_ I1=common.pb.uart.tx_mod.sym_count[1] I2=common.pb.uart.tx_mod.tx_buf[6] I3=common.pb.uart.tx_mod.tx_buf[2] O=$abc$44715$techmap$techmap\common.pb.uart.tx_mod.$shiftx$uart_mod.v:356$9125.$11\buffer[23:0][16]_new_inv_
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:56"
.param LUT_INIT 0100010101100111
.gate SB_LUT4 I0=$false I1=common.pb.uart.tx_mod.sym_count[0] I2=$abc$44715$techmap$techmap\common.pb.uart.tx_mod.$shiftx$uart_mod.v:356$9125.$11\buffer[23:0][16]_new_inv_ I3=$abc$44715$techmap$techmap\common.pb.uart.tx_mod.$shiftx$uart_mod.v:356$9125.$11\buffer[23:0][17]_new_inv_ O=$abc$44715$techmap\common.pb.uart.tx_mod.$procmux$15493_Y_new_inv_
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:51"
.param LUT_INIT 1111110000110000
.gate SB_LUT4 I0=$abc$44715$techmap\common.pb.uart.tx_mod.$logic_or$uart_mod.v:353$9121_Y_new_ I1=$abc$44715$new_n1430_ I2=$abc$44715$techmap\common.pb.uart.tx_mod.$procmux$15493_Y_new_inv_ I3=$abc$44715$common.pb.uart.tx_mod.calc_tx_parity_new_inv_ O=$abc$44715$techmap\common.pb.uart.tx_mod.$procmux$15495_Y_new_
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:56"
.param LUT_INIT 1100111011011111
.gate SB_LUT4 I0=$false I1=$abc$44715$auto$rtlil.cc:1969:NotGate$44285 I2=$abc$44715$techmap\common.pb.uart.tx_mod.$procmux$15495_Y_new_ I3=$abc$44715$auto$simplemap.cc:250:simplemap_eqne$40309[1]_new_inv_ O=$abc$44715$auto$ice40_ffinit.cc:140:execute$44094
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:51"
.param LUT_INIT 0011001100000011
.gate SB_LUT4 I0=common.pb.uart.tx_mod.sym_count[2] I1=common.pb.uart.tx_mod.sym_count[1] I2=common.pb.uart.tx_mod.tx_buf[5] I3=common.pb.uart.tx_mod.tx_buf[1] O=$abc$44715$new_n2653_
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:56"
.param LUT_INIT 0010101001101110
.gate SB_LUT4 I0=$abc$44715$new_n2653_ I1=common.pb.uart.tx_mod.sym_count[1] I2=common.pb.uart.tx_mod.tx_buf[3] I3=common.pb.uart.tx_mod.tx_buf[7] O=$abc$44715$techmap$techmap\common.pb.uart.tx_mod.$shiftx$uart_mod.v:356$9125.$11\buffer[23:0][17]_new_inv_
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:56"
.param LUT_INIT 1000101010011011
.gate SB_LUT4 I0=common.pb.tsyn_clks[2] I1=common.pb.tsyn_clks[7] I2=$abc$44715$auto$ice40_ffinit.cc:141:execute$44023 I3=$abc$44715$auto$ice40_ffinit.cc:141:execute$44003 O=$abc$44715$new_n2655_
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:56"
.param LUT_INIT 0001010000101000
.gate SB_LUT4 I0=common.pb.tsyn_clks[20] I1=common.pb.tsyn_clks[0] I2=$abc$44715$auto$ice40_ffinit.cc:141:execute$44091 I3=$abc$44715$auto$ice40_ffinit.cc:141:execute$44075 O=$abc$44715$new_n2656_
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:56"
.param LUT_INIT 0001010000101000
.gate SB_LUT4 I0=$abc$44715$new_n1460_ I1=$abc$44715$new_n1443_ I2=$abc$44715$new_n2656_ I3=$abc$44715$new_n2655_ O=$abc$44715$new_n2657_
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:56"
.param LUT_INIT 0111111111111111
.gate SB_LUT4 I0=$false I1=$false I2=$abc$44715$new_n2657_ I3=$abc$44715$auto$alumacc.cc:491:replace_alu$16107[23] O=$abc$44715$auto$rtlil.cc:1836:ReduceOr$16117
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:46"
.param LUT_INIT 1111111100001111
.gate SB_LUT4 I0=common.pb.tsyn_clks[6] I1=$abc$44715$auto$ice40_ffinit.cc:141:execute$44019 I2=common.pb.tsyn_clks[5] I3=$abc$44715$auto$ice40_ffinit.cc:141:execute$44015 O=$abc$44715$new_n2659_
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:56"
.param LUT_INIT 0110011001100000
.gate SB_LUT4 I0=$abc$44715$auto$ice40_ffinit.cc:141:execute$44063 I1=common.pb.tsyn_clks[17] I2=common.pb.tsyn_clks[19] I3=$abc$44715$auto$ice40_ffinit.cc:141:execute$44071 O=$abc$44715$new_n2660_
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:56"
.param LUT_INIT 0110011001100000
.gate SB_LUT4 I0=$abc$44715$new_n1450_ I1=$abc$44715$new_n1449_ I2=$abc$44715$new_n2660_ I3=$abc$44715$new_n2659_ O=$abc$44715$new_n2661_
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:56"
.param LUT_INIT 1000000000000000
.gate SB_LUT4 I0=$false I1=$abc$44715$new_n2661_ I2=common.pb.tsyn_clks[1] I3=$abc$44715$auto$ice40_ffinit.cc:141:execute$43999 O=$abc$44715$new_n2662_
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:51"
.param LUT_INIT 0000110011000000
.gate SB_LUT4 I0=$abc$44715$auto$simplemap.cc:250:simplemap_eqne$19820[6]_new_inv_ I1=common.pb.spirx_crc[0] I2=common.pb.spi.rx_data_r[1] I3=common.pb.spi.rx_data_r[0] O=$abc$44715$new_n2663_
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:56"
.param LUT_INIT 1001011001101001
.gate SB_LUT4 I0=common.pb.spirx_crc[1] I1=$abc$44715$auto$opt_reduce.cc:132:opt_mux$15900_new_inv_ I2=common.pb.spi.rx_irq_r I3=$abc$44715$new_n2663_ O=$abc$44715$techmap$techmap\common.pb.$procmux$14301.$and$/home/mb/fpga-toolchain/yosys/bin/../share/yosys/techmap.v:434$17895_Y[1]_new_
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:56"
.param LUT_INIT 0001001000100010
.gate SB_LUT4 I0=common.pb.tx_buf_rd_addr[1] I1=common.pb.tx_buf_wr_addr[1] I2=common.pb.tx_buf_wr_addr[0] I3=common.pb.tx_buf_rd_addr[0] O=$abc$44715$auto$simplemap.cc:127:simplemap_reduce$19996[0]_new_inv_
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:56"
.param LUT_INIT 1001000000001001
.gate SB_LUT4 I0=common.pb.tx_buf_rd_addr[6] I1=common.pb.tx_buf_wr_addr[6] I2=common.pb.tx_buf_rd_addr[5] I3=common.pb.tx_buf_wr_addr[5] O=$abc$44715$new_n2666_
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:56"
.param LUT_INIT 1001000000001001
.gate SB_LUT4 I0=$abc$44715$auto$simplemap.cc:250:simplemap_eqne$29929[2]_new_inv_ I1=common.pb.uart.tx_mod.tx_active I2=common.pb.uart.tx_trigger_req I3=common.pb.uart_tx_trigger O=$abc$44715$techmap\common.pb.$procmux$14662_Y
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:56"
.param LUT_INIT 0000000000000010
.gate SB_LUT4 I0=$abc$44715$new_n1437_ I1=common.pb.uart.rx_mod.sym_count[3] I2=common.pb.uart.rx_mod.symclk.sample I3=common.pb.uart.rx_mod.sym_count[0] O=$abc$44715$new_n2669_
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:56"
.param LUT_INIT 1001000010110010
.gate SB_LUT4 I0=$false I1=$abc$44715$new_n2669_ I2=$abc$44715$new_n1851_ I3=$abc$44715$auto$rtlil.cc:1969:NotGate$44281 O=$abc$44715$new_n2670_
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:51"
.param LUT_INIT 0000000000001100
.gate SB_LUT4 I0=$abc$44715$new_n1466_ I1=$abc$44715$new_n1999_ I2=$abc$44715$techmap\common.pb.$xor$parity_func.v:39$5915_Y_new_ I3=common.pb.rx_buf_rd_data[8] O=$abc$44715$new_n2671_
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:56"
.param LUT_INIT 0110111011100110
.gate SB_LUT4 I0=common.pb.spitx_len[7] I1=$abc$44715$auto$simplemap.cc:250:simplemap_eqne$35852[3]_new_ I2=$abc$44715$new_n1823_ I3=common.pb.rx_buf_rd_data[7] O=$abc$44715$techmap\common.pb.$procmux$9321_Y_new_inv_
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:56"
.param LUT_INIT 0000110111011101
.gate SB_LUT4 I0=$abc$44715$new_n2671_ I1=$abc$44715$new_n1466_ I2=$abc$44715$new_n2031_ I3=$abc$44715$techmap\common.pb.$procmux$9321_Y_new_inv_ O=$abc$44715$techmap\common.pb.$2\spi_tx_data[7:0][7]
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:56"
.param LUT_INIT 1111010011110110
.gate SB_LUT4 I0=$abc$44715$auto$alumacc.cc:474:replace_alu$15981.B_buf[7] I1=common.pb.uart.tx_mod.symclk.count[7] I2=common.pb.uart.tx_mod.symclk.count[0] I3=$abc$44715$auto$alumacc.cc:474:replace_alu$15981.B_buf[0] O=$abc$44715$new_n2674_
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:56"
.param LUT_INIT 1001100100001001
.gate SB_LUT4 I0=$abc$44715$auto$alumacc.cc:474:replace_alu$15981.B_buf[15] I1=common.pb.uart.tx_mod.symclk.count[15] I2=$abc$44715$auto$alumacc.cc:474:replace_alu$15981.B_buf[8] I3=common.pb.uart.tx_mod.symclk.count[8] O=$abc$44715$new_n2675_
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:56"
.param LUT_INIT 1001100100001001
.gate SB_LUT4 I0=$abc$44715$new_n2674_ I1=$abc$44715$auto$alumacc.cc:490:replace_alu$15982[1]_new_ I2=$abc$44715$new_n2675_ I3=$abc$44715$auto$alumacc.cc:490:replace_alu$15982[16]_new_inv_ O=$abc$44715$new_n2676_
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:56"
.param LUT_INIT 0000000010000000
.gate SB_LUT4 I0=$abc$44715$auto$alumacc.cc:491:replace_alu$15983[31] I1=$abc$44715$new_n2134_ I2=$abc$44715$new_n2681_ I3=$abc$44715$new_n2676_ O=$abc$44715$auto$rtlil.cc:1836:ReduceOr$15993_new_inv_
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:56"
.param LUT_INIT 0001010101010101
.gate SB_LUT4 I0=$abc$44715$auto$alumacc.cc:474:replace_alu$15981.B_buf[6] I1=common.pb.uart.tx_mod.symclk.count[6] I2=$abc$44715$auto$alumacc.cc:474:replace_alu$15981.B_buf[14] I3=common.pb.uart.tx_mod.symclk.count[14] O=$abc$44715$new_n2678_
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:56"
.param LUT_INIT 1001100100001001
.gate SB_LUT4 I0=$abc$44715$auto$alumacc.cc:474:replace_alu$15981.B_buf[22] I1=common.pb.uart.tx_mod.symclk.count[22] I2=common.pb.uart.tx_mod.symclk.count[18] I3=$abc$44715$auto$alumacc.cc:474:replace_alu$15981.B_buf[18] O=$abc$44715$new_n2679_
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:56"
.param LUT_INIT 1001100100001001
.gate SB_LUT4 I0=$abc$44715$new_n2121_ I1=$abc$44715$new_n2120_ I2=$abc$44715$new_n2679_ I3=$abc$44715$new_n2678_ O=$abc$44715$new_n2680_
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:56"
.param LUT_INIT 1000000000000000
.gate SB_LUT4 I0=$abc$44715$new_n2109_ I1=$abc$44715$new_n2680_ I2=$abc$44715$auto$alumacc.cc:474:replace_alu$15981.B_buf[5] I3=common.pb.uart.tx_mod.symclk.count[5] O=$abc$44715$new_n2681_
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:56"
.param LUT_INIT 1000000000001000
.gate SB_LUT4 I0=$abc$44715$techmap\common.pb.uart.rx_mod.symclk.$sub$uart_mod.v:78$19_Y[23] I1=common.pb.uart.tx_mod.symclk.count[23] I2=common.pb.uart.tx_mod.symclk.count[20] I3=$abc$44715$techmap\common.pb.uart.rx_mod.symclk.$sub$uart_mod.v:78$19_Y[20] O=$abc$44715$new_n2682_
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:56"
.param LUT_INIT 1001100100001001
.gate SB_LUT4 I0=$abc$44715$auto$alumacc.cc:474:replace_alu$15981.B_buf[10] I1=common.pb.uart.rx_mod.symclk.count[10] I2=common.pb.uart.rx_mod.symclk.count[0] I3=$abc$44715$auto$alumacc.cc:474:replace_alu$15981.B_buf[0] O=$abc$44715$new_n2686_
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:56"
.param LUT_INIT 1001100100001001
.gate SB_LUT4 I0=$abc$44715$auto$alumacc.cc:474:replace_alu$15981.B_buf[18] I1=common.pb.uart.rx_mod.symclk.count[18] I2=$abc$44715$auto$alumacc.cc:474:replace_alu$15981.B_buf[22] I3=common.pb.uart.rx_mod.symclk.count[22] O=$abc$44715$new_n2687_
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:56"
.param LUT_INIT 1001100100001001
.gate SB_LUT4 I0=$abc$44715$auto$alumacc.cc:474:replace_alu$15981.BB[31] I1=$abc$44715$auto$alumacc.cc:474:replace_alu$15981.B_buf[23] I2=common.pb.uart.rx_mod.symclk.count[23] I3=$abc$44715$auto$alumacc.cc:474:replace_alu$15981.B_buf[24] O=$abc$44715$new_n2690_
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:56"
.param LUT_INIT 0000000010000010
.gate SB_LUT4 I0=$abc$44715$new_n2218_ I1=$abc$44715$new_n2217_ I2=$abc$44715$auto$alumacc.cc:490:replace_alu$15995[19]_new_ I3=$abc$44715$auto$alumacc.cc:490:replace_alu$15995[16]_new_ O=$abc$44715$new_n2691_
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:56"
.param LUT_INIT 1000000000000000
.gate SB_LUT4 I0=$abc$44715$auto$alumacc.cc:474:replace_alu$15981.B_buf[7] I1=common.pb.uart.rx_mod.symclk.count[7] I2=$abc$44715$auto$alumacc.cc:474:replace_alu$15981.B_buf[6] I3=common.pb.uart.rx_mod.symclk.count[6] O=$abc$44715$auto$simplemap.cc:127:simplemap_reduce$16935[12]_new_
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:56"
.param LUT_INIT 1001000000001001
.gate SB_LUT4 I0=$abc$44715$auto$alumacc.cc:474:replace_alu$15981.B_buf[11] I1=common.pb.uart.rx_mod.symclk.count[11] I2=common.pb.uart.rx_mod.symclk.count[15] I3=$abc$44715$auto$alumacc.cc:474:replace_alu$15981.B_buf[15] O=$abc$44715$new_n2694_
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:56"
.param LUT_INIT 1101110100001101
.gate SB_LUT4 I0=$abc$44715$techmap\common.pb.uart.rx_mod.symclk.$sub$uart_mod.v:78$19_Y[16] I1=common.pb.uart.rx_mod.symclk.count[16] I2=$abc$44715$techmap\common.pb.uart.rx_mod.symclk.$sub$uart_mod.v:78$19_Y[17] I3=common.pb.uart.rx_mod.symclk.count[17] O=$abc$44715$new_n2696_
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:56"
.param LUT_INIT 1001100100001001
.gate SB_LUT4 I0=$abc$44715$techmap\common.pb.uart.rx_mod.symclk.$sub$uart_mod.v:78$19_Y[22] I1=common.pb.uart.rx_mod.symclk.count[22] I2=common.pb.uart.rx_mod.symclk.count[21] I3=$abc$44715$techmap\common.pb.uart.rx_mod.symclk.$sub$uart_mod.v:78$19_Y[21] O=$abc$44715$new_n2697_
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:56"
.param LUT_INIT 1001100100001001
.gate SB_LUT4 I0=$abc$44715$techmap\common.pb.uart.rx_mod.symclk.$sub$uart_mod.v:78$19_Y[12] I1=common.pb.uart.rx_mod.symclk.count[12] I2=$abc$44715$techmap\common.pb.uart.rx_mod.symclk.$sub$uart_mod.v:78$19_Y[9] I3=common.pb.uart.rx_mod.symclk.count[9] O=$abc$44715$new_n2700_
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:56"
.param LUT_INIT 1001100100001001
.gate SB_LUT4 I0=$abc$44715$techmap\common.pb.uart.rx_mod.symclk.$sub$uart_mod.v:78$19_Y[20] I1=common.pb.uart.rx_mod.symclk.count[20] I2=$abc$44715$techmap\common.pb.uart.rx_mod.symclk.$sub$uart_mod.v:78$19_Y[19] I3=common.pb.uart.rx_mod.symclk.count[19] O=$abc$44715$new_n2701_
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:56"
.param LUT_INIT 1001000000001001
.gate SB_LUT4 I0=$abc$44715$new_n2242_ I1=$abc$44715$new_n2241_ I2=$abc$44715$new_n2701_ I3=$abc$44715$new_n2700_ O=$abc$44715$new_n2702_
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:56"
.param LUT_INIT 1000000000000000
.gate SB_LUT4 I0=$abc$44715$new_n2236_ I1=$abc$44715$new_n2702_ I2=common.pb.uart.rx_mod.symclk.count[7] I3=$abc$44715$techmap\common.pb.uart.rx_mod.symclk.$sub$uart_mod.v:78$19_Y[7] O=$abc$44715$new_n2703_
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:56"
.param LUT_INIT 1000100000001000
.gate SB_LUT4 I0=$abc$44715$new_n2252_ I1=$abc$44715$auto$alumacc.cc:474:replace_alu$16166.C[31] I2=$abc$44715$techmap\common.pb.uart.rx_mod.symclk.$sub$uart_mod.v:78$19_Y[3] I3=common.pb.uart.rx_mod.symclk.count[3] O=$abc$44715$new_n2704_
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:56"
.param LUT_INIT 1000000000001000
.gate SB_LUT4 I0=common.pb.spirx_lencalc_byte[3] I1=common.pb.spirx_lencalc.byte_le[3] I2=common.pb.spirx_lencalc.byte_le[5] I3=common.pb.spirx_lencalc_byte[5] O=$abc$44715$new_n2708_
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:56"
.param LUT_INIT 1001000000001001
.gate SB_LUT4 I0=common.pb.spirx_lencalc.error I1=common.pb.spirx_lencalc_new I2=$abc$44715$techmap\common.pb.spirx_lencalc.$logic_and$profibus_phy_mod.v:144$5341_Y_new_ I3=common.pb.spirx_lencalc.state[0] O=$abc$44715$new_n2710_
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:56"
.param LUT_INIT 1010111011101110
.gate SB_LUT4 I0=common.pb.spirx_lencalc.state[1] I1=$abc$44715$new_n2741_ I2=$abc$44715$new_n2378_ I3=$abc$44715$new_n2351_ O=$abc$44715$new_n2711_
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:56"
.param LUT_INIT 0111011100100111
.gate SB_LUT4 I0=$abc$44715$new_n2710_ I1=common.pb.spirx_lencalc.state[1] I2=$abc$44715$new_n2711_ I3=common.pb.spirx_lencalc.state[0] O=$abc$44715$techmap$techmap\common.pb.spirx_lencalc.$procmux$14815.$ternary$/home/mb/fpga-toolchain/yosys/bin/../share/yosys/techmap.v:445$18549_Y
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:56"
.param LUT_INIT 0010001010000010
.gate SB_LUT4 I0=common.pb.spirx_bytecount[4] I1=common.pb.spirx_len[4] I2=common.pb.spirx_bytecount[3] I3=common.pb.spirx_len[3] O=$abc$44715$new_n2713_
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:56"
.param LUT_INIT 1001000000001001
.gate SB_LUT4 I0=common.pb.spirx_bytecount[6] I1=common.pb.spirx_len[6] I2=common.pb.spirx_bytecount[5] I3=common.pb.spirx_len[5] O=$abc$44715$new_n2714_
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:56"
.param LUT_INIT 1001000000001001
.gate SB_LUT4 I0=$abc$44715$new_n2713_ I1=$abc$44715$new_n2714_ I2=common.pb.spirx_bytecount[0] I3=common.pb.spirx_len[0] O=$abc$44715$new_n2715_
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:56"
.param LUT_INIT 1000000000001000
.gate SB_LUT4 I0=$false I1=$false I2=$abc$44715$new_n2445_ I3=$abc$44715$new_n2715_ O=$abc$44715$auto$rtlil.cc:1835:ReduceAnd$16100_new_
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:46"
.param LUT_INIT 1111000000000000
.gate SB_LUT4 I0=common.pb.tx_buf_rd_addr[3] I1=common.pb.tx_buf_wr_addr[3] I2=common.pb.tx_buf_rd_addr[2] I3=common.pb.tx_buf_wr_addr[2] O=$abc$44715$auto$simplemap.cc:127:simplemap_reduce$19996[1]_new_inv_
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:56"
.param LUT_INIT 1001000000001001
.gate SB_LUT4 I0=common.pb.tx_buf_rd_addr[7] I1=common.pb.tx_buf_wr_addr[7] I2=common.pb.tx_buf_rd_addr[4] I3=common.pb.tx_buf_wr_addr[4] O=$abc$44715$new_n2718_
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:56"
.param LUT_INIT 1001000000001001
.gate SB_LUT4 I0=$abc$44715$new_n2666_ I1=$abc$44715$auto$simplemap.cc:127:simplemap_reduce$19996[0]_new_inv_ I2=$abc$44715$new_n2718_ I3=$abc$44715$auto$simplemap.cc:127:simplemap_reduce$19996[1]_new_inv_ O=$abc$44715$auto$simplemap.cc:250:simplemap_eqne$29929[2]_new_inv_
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:56"
.param LUT_INIT 0111111111111111
.gate SB_LUT4 I0=$abc$44715$techmap\common.pb.uart.rx_mod.symclk.$sub$uart_mod.v:78$19_Y[7] I1=common.pb.uart.tx_mod.symclk.count[7] I2=$abc$44715$techmap\common.pb.uart.rx_mod.symclk.$sub$uart_mod.v:78$19_Y[5] I3=common.pb.uart.tx_mod.symclk.count[5] O=$abc$44715$new_n2720_
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:56"
.param LUT_INIT 1001000000001001
.gate SB_LUT4 I0=$false I1=$abc$44715$new_n2720_ I2=$abc$44715$auto$alumacc.cc:474:replace_alu$16166.C[31] I3=$abc$44715$auto$simplemap.cc:250:simplemap_eqne$21955[1]_new_ O=$abc$44715$new_n2721_
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:51"
.param LUT_INIT 0000000011000000
.gate SB_LUT4 I0=$abc$44715$auto$alumacc.cc:474:replace_alu$15981.B_buf[8] I1=common.pb.uart.rx_mod.symclk.count[8] I2=common.pb.uart.rx_mod.symclk.count[14] I3=$abc$44715$auto$alumacc.cc:474:replace_alu$15981.B_buf[14] O=$abc$44715$new_n2726_
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:56"
.param LUT_INIT 1001100100001001
.gate SB_LUT4 I0=$abc$44715$new_n2206_ I1=$abc$44715$new_n2205_ I2=$abc$44715$new_n2204_ I3=$abc$44715$new_n2726_ O=$abc$44715$new_n2727_
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:56"
.param LUT_INIT 1000000000000000
.gate SB_LUT4 I0=$abc$44715$new_n2694_ I1=$abc$44715$auto$simplemap.cc:127:simplemap_reduce$16935[12]_new_ I2=$abc$44715$new_n2687_ I3=$abc$44715$new_n2210_ O=$abc$44715$new_n2728_
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:56"
.param LUT_INIT 1000000000000000
.gate SB_LUT4 I0=$abc$44715$new_n2728_ I1=$abc$44715$new_n2727_ I2=common.pb.uart.rx_mod.symclk.count[0] I3=$abc$44715$auto$alumacc.cc:474:replace_alu$15981.B_buf[0] O=$abc$44715$new_n2729_
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:56"
.param LUT_INIT 1000000010001000
.gate SB_LUT4 I0=$abc$44715$auto$alumacc.cc:474:replace_alu$15981.B_buf[3] I1=common.pb.uart.rx_mod.symclk.count[3] I2=common.pb.uart.rx_mod.symclk.count[5] I3=$abc$44715$auto$alumacc.cc:474:replace_alu$15981.B_buf[5] O=$abc$44715$new_n2730_
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:56"
.param LUT_INIT 1001100100001001
.gate SB_LUT4 I0=$abc$44715$auto$alumacc.cc:474:replace_alu$15981.B_buf[13] I1=common.pb.uart.rx_mod.symclk.count[13] I2=$abc$44715$auto$alumacc.cc:474:replace_alu$15981.B_buf[14] I3=common.pb.uart.rx_mod.symclk.count[14] O=$abc$44715$new_n2731_
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:56"
.param LUT_INIT 1001100100001001
.gate SB_LUT4 I0=$abc$44715$new_n2690_ I1=$abc$44715$new_n2686_ I2=$abc$44715$new_n2200_ I3=$abc$44715$new_n2731_ O=$abc$44715$new_n2732_
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:56"
.param LUT_INIT 1000000000000000
.gate SB_LUT4 I0=$abc$44715$new_n2729_ I1=$abc$44715$new_n2691_ I2=$abc$44715$new_n2732_ I3=$abc$44715$new_n2730_ O=$abc$44715$new_n2733_
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:56"
.param LUT_INIT 1000000000000000
.gate SB_LUT4 I0=$abc$44715$techmap\common.pb.uart.rx_mod.symclk.$sub$uart_mod.v:78$19_Y[18] I1=common.pb.uart.rx_mod.symclk.count[18] I2=$abc$44715$techmap\common.pb.uart.rx_mod.symclk.$sub$uart_mod.v:78$19_Y[7] I3=common.pb.uart.rx_mod.symclk.count[7] O=$abc$44715$new_n2734_
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:56"
.param LUT_INIT 1001100100001001
.gate SB_LUT4 I0=$abc$44715$new_n2734_ I1=common.pb.uart.rx_mod.symclk.count[0] I2=$abc$44715$techmap\common.pb.uart.rx_mod.symclk.$sub$uart_mod.v:78$19_Y[0] I3=$abc$44715$auto$simplemap.cc:250:simplemap_eqne$22165[1]_new_ O=$abc$44715$new_n2735_
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:56"
.param LUT_INIT 0000000010000010
.gate SB_LUT4 I0=common.pb.spirx_lencalc_byte[4] I1=common.pb.spirx_lencalc.byte_le[4] I2=common.pb.spirx_lencalc.byte_le[6] I3=common.pb.spirx_lencalc_byte[6] O=$abc$44715$new_n2738_
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:56"
.param LUT_INIT 1001000000001001
.gate SB_LUT4 I0=common.pb.spirx_lencalc.byte_le[2] I1=common.pb.spirx_lencalc_byte[2] I2=common.pb.spirx_lencalc.byte_le[0] I3=common.pb.spirx_lencalc_byte[0] O=$abc$44715$new_n2739_
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:56"
.param LUT_INIT 1001000000001001
.gate SB_LUT4 I0=$abc$44715$new_n2708_ I1=$abc$44715$new_n2739_ I2=common.pb.spirx_lencalc_new I3=$abc$44715$auto$simplemap.cc:250:simplemap_eqne$20197[1]_new_ O=$abc$44715$new_n2740_
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:56"
.param LUT_INIT 0000000010000000
.gate SB_LUT4 I0=$abc$44715$new_n2738_ I1=$abc$44715$new_n2740_ I2=common.pb.spirx_lencalc.byte_le[7] I3=common.pb.spirx_lencalc_byte[7] O=$abc$44715$new_n2741_
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:56"
.param LUT_INIT 1000000000001000
.gate SB_LUT4 I0=$abc$44715$techmap\common.pb.uart.rx_mod.symclk.$sub$uart_mod.v:78$19_Y[16] I1=common.pb.uart.tx_mod.symclk.count[16] I2=$abc$44715$techmap\common.pb.uart.rx_mod.symclk.$sub$uart_mod.v:78$19_Y[20] I3=common.pb.uart.tx_mod.symclk.count[20] O=$abc$44715$new_n2742_
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:56"
.param LUT_INIT 1001100100001001
.gate SB_LUT4 I0=$abc$44715$new_n2742_ I1=common.pb.uart.tx_mod.symclk.count[11] I2=$abc$44715$techmap\common.pb.uart.rx_mod.symclk.$sub$uart_mod.v:78$19_Y[11] I3=$abc$44715$new_n2159_ O=$abc$44715$new_n2743_
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:56"
.param LUT_INIT 0000000010000010
.gate SB_LUT4 I0=$abc$44715$techmap\common.pb.uart.rx_mod.symclk.$sub$uart_mod.v:78$19_Y[6] I1=common.pb.uart.tx_mod.symclk.count[6] I2=$abc$44715$techmap\common.pb.uart.rx_mod.symclk.$sub$uart_mod.v:78$19_Y[10] I3=common.pb.uart.tx_mod.symclk.count[10] O=$abc$44715$new_n2746_
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:56"
.param LUT_INIT 1001100100001001
.gate SB_LUT4 I0=$abc$44715$techmap\common.pb.uart.rx_mod.symclk.$sub$uart_mod.v:78$19_Y[22] I1=common.pb.uart.tx_mod.symclk.count[22] I2=$abc$44715$techmap\common.pb.uart.rx_mod.symclk.$sub$uart_mod.v:78$19_Y[17] I3=common.pb.uart.tx_mod.symclk.count[17] O=$abc$44715$new_n2747_
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:56"
.param LUT_INIT 1001000000001001
.gate SB_LUT4 I0=$abc$44715$new_n2743_ I1=$abc$44715$new_n2721_ I2=$abc$44715$new_n2682_ I3=$abc$44715$new_n2164_ O=$abc$44715$new_n2748_
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:56"
.param LUT_INIT 1000000000000000
.gate SB_LUT4 I0=$abc$44715$new_n2748_ I1=$abc$44715$new_n2141_ I2=$abc$44715$new_n2747_ I3=$abc$44715$new_n2746_ O=$abc$44715$new_n2749_
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:56"
.param LUT_INIT 1000000000000000
.gate SB_LUT4 I0=$abc$44715$techmap\common.pb.uart.rx_mod.symclk.$sub$uart_mod.v:78$19_Y[14] I1=common.pb.uart.rx_mod.symclk.count[14] I2=common.pb.uart.rx_mod.symclk.count[11] I3=$abc$44715$techmap\common.pb.uart.rx_mod.symclk.$sub$uart_mod.v:78$19_Y[11] O=$abc$44715$new_n2750_
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:56"
.param LUT_INIT 1001100100001001
.gate SB_LUT4 I0=$abc$44715$new_n2697_ I1=$abc$44715$new_n2696_ I2=$abc$44715$new_n2232_ I3=$abc$44715$new_n2750_ O=$abc$44715$new_n2751_
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:56"
.param LUT_INIT 1000000000000000
.gate SB_LUT4 I0=$abc$44715$new_n2735_ I1=$abc$44715$new_n2704_ I2=$abc$44715$new_n2246_ I3=$abc$44715$new_n2751_ O=$abc$44715$new_n2752_
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:56"
.param LUT_INIT 1000000000000000
.gate SB_LUT4 I0=$abc$44715$new_n2703_ I1=$abc$44715$new_n2752_ I2=$abc$44715$techmap\common.pb.uart.rx_mod.symclk.$sub$uart_mod.v:78$19_Y[4] I3=common.pb.uart.rx_mod.symclk.count[4] O=$abc$44715$new_n2753_
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:56"
.param LUT_INIT 1000000000001000
.gate SB_CARRY CI=$true CO=$auto$alumacc.cc:474:replace_alu$15981.C[1] I0=common.pb.uart.tx_mod.symclk.count[0] I1=$abc$44715$auto$alumacc.cc:474:replace_alu$15981.BB[0]
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:395|uart_mod.v:561|uart_mod.v:300|uart_mod.v:83|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/arith_map.v:56"
.gate SB_CARRY CI=$auto$alumacc.cc:474:replace_alu$15981.C[10] CO=$auto$alumacc.cc:474:replace_alu$15981.C[11] I0=common.pb.uart.tx_mod.symclk.count[10] I1=$abc$44715$auto$alumacc.cc:474:replace_alu$15981.BB[10]
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:395|uart_mod.v:561|uart_mod.v:300|uart_mod.v:83|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/arith_map.v:56"
.gate SB_CARRY CI=$auto$alumacc.cc:474:replace_alu$15981.C[11] CO=$auto$alumacc.cc:474:replace_alu$15981.C[12] I0=common.pb.uart.tx_mod.symclk.count[11] I1=$abc$44715$auto$alumacc.cc:474:replace_alu$15981.BB[11]
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:395|uart_mod.v:561|uart_mod.v:300|uart_mod.v:83|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/arith_map.v:56"
.gate SB_CARRY CI=$auto$alumacc.cc:474:replace_alu$15981.C[12] CO=$auto$alumacc.cc:474:replace_alu$15981.C[13] I0=common.pb.uart.tx_mod.symclk.count[12] I1=$abc$44715$auto$alumacc.cc:474:replace_alu$15981.BB[12]
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:395|uart_mod.v:561|uart_mod.v:300|uart_mod.v:83|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/arith_map.v:56"
.gate SB_CARRY CI=$auto$alumacc.cc:474:replace_alu$15981.C[13] CO=$auto$alumacc.cc:474:replace_alu$15981.C[14] I0=common.pb.uart.tx_mod.symclk.count[13] I1=$abc$44715$auto$alumacc.cc:474:replace_alu$15981.BB[13]
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:395|uart_mod.v:561|uart_mod.v:300|uart_mod.v:83|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/arith_map.v:56"
.gate SB_CARRY CI=$auto$alumacc.cc:474:replace_alu$15981.C[14] CO=$auto$alumacc.cc:474:replace_alu$15981.C[15] I0=common.pb.uart.tx_mod.symclk.count[14] I1=$abc$44715$auto$alumacc.cc:474:replace_alu$15981.BB[14]
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:395|uart_mod.v:561|uart_mod.v:300|uart_mod.v:83|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/arith_map.v:56"
.gate SB_CARRY CI=$auto$alumacc.cc:474:replace_alu$15981.C[15] CO=$auto$alumacc.cc:474:replace_alu$15981.C[16] I0=common.pb.uart.tx_mod.symclk.count[15] I1=$abc$44715$auto$alumacc.cc:474:replace_alu$15981.BB[15]
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:395|uart_mod.v:561|uart_mod.v:300|uart_mod.v:83|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/arith_map.v:56"
.gate SB_CARRY CI=$auto$alumacc.cc:474:replace_alu$15981.C[16] CO=$auto$alumacc.cc:474:replace_alu$15981.C[17] I0=common.pb.uart.tx_mod.symclk.count[16] I1=$abc$44715$auto$alumacc.cc:474:replace_alu$15981.BB[16]
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:395|uart_mod.v:561|uart_mod.v:300|uart_mod.v:83|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/arith_map.v:56"
.gate SB_CARRY CI=$auto$alumacc.cc:474:replace_alu$15981.C[17] CO=$auto$alumacc.cc:474:replace_alu$15981.C[18] I0=common.pb.uart.tx_mod.symclk.count[17] I1=$abc$44715$auto$alumacc.cc:474:replace_alu$15981.BB[17]
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:395|uart_mod.v:561|uart_mod.v:300|uart_mod.v:83|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/arith_map.v:56"
.gate SB_CARRY CI=$auto$alumacc.cc:474:replace_alu$15981.C[18] CO=$auto$alumacc.cc:474:replace_alu$15981.C[19] I0=common.pb.uart.tx_mod.symclk.count[18] I1=$abc$44715$auto$alumacc.cc:474:replace_alu$15981.BB[18]
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:395|uart_mod.v:561|uart_mod.v:300|uart_mod.v:83|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/arith_map.v:56"
.gate SB_CARRY CI=$auto$alumacc.cc:474:replace_alu$15981.C[19] CO=$auto$alumacc.cc:474:replace_alu$15981.C[20] I0=common.pb.uart.tx_mod.symclk.count[19] I1=$abc$44715$auto$alumacc.cc:474:replace_alu$15981.BB[19]
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:395|uart_mod.v:561|uart_mod.v:300|uart_mod.v:83|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/arith_map.v:56"
.gate SB_CARRY CI=$auto$alumacc.cc:474:replace_alu$15981.C[1] CO=$auto$alumacc.cc:474:replace_alu$15981.C[2] I0=common.pb.uart.tx_mod.symclk.count[1] I1=$abc$44715$auto$alumacc.cc:474:replace_alu$15981.BB[1]
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:395|uart_mod.v:561|uart_mod.v:300|uart_mod.v:83|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/arith_map.v:56"
.gate SB_CARRY CI=$auto$alumacc.cc:474:replace_alu$15981.C[20] CO=$auto$alumacc.cc:474:replace_alu$15981.C[21] I0=common.pb.uart.tx_mod.symclk.count[20] I1=$abc$44715$auto$alumacc.cc:474:replace_alu$15981.BB[20]
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:395|uart_mod.v:561|uart_mod.v:300|uart_mod.v:83|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/arith_map.v:56"
.gate SB_CARRY CI=$auto$alumacc.cc:474:replace_alu$15981.C[21] CO=$auto$alumacc.cc:474:replace_alu$15981.C[22] I0=common.pb.uart.tx_mod.symclk.count[21] I1=$abc$44715$auto$alumacc.cc:474:replace_alu$15981.BB[21]
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:395|uart_mod.v:561|uart_mod.v:300|uart_mod.v:83|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/arith_map.v:56"
.gate SB_CARRY CI=$auto$alumacc.cc:474:replace_alu$15981.C[22] CO=$auto$alumacc.cc:474:replace_alu$15981.C[23] I0=common.pb.uart.tx_mod.symclk.count[22] I1=$abc$44715$auto$alumacc.cc:474:replace_alu$15981.BB[22]
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:395|uart_mod.v:561|uart_mod.v:300|uart_mod.v:83|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/arith_map.v:56"
.gate SB_CARRY CI=$auto$alumacc.cc:474:replace_alu$15981.C[23] CO=$auto$alumacc.cc:474:replace_alu$15981.C[24] I0=common.pb.uart.tx_mod.symclk.count[23] I1=$abc$44715$auto$alumacc.cc:474:replace_alu$15981.BB[23]
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:395|uart_mod.v:561|uart_mod.v:300|uart_mod.v:83|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/arith_map.v:56"
.gate SB_CARRY CI=$auto$alumacc.cc:474:replace_alu$15981.C[24] CO=$auto$alumacc.cc:474:replace_alu$15981.C[25] I0=$false I1=$abc$44715$auto$alumacc.cc:474:replace_alu$15981.BB[24]
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:395|uart_mod.v:561|uart_mod.v:300|uart_mod.v:83|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/arith_map.v:56"
.gate SB_CARRY CI=$auto$alumacc.cc:474:replace_alu$15981.C[25] CO=$auto$alumacc.cc:474:replace_alu$15981.C[26] I0=$false I1=$abc$44715$auto$alumacc.cc:474:replace_alu$15981.BB[31]
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:395|uart_mod.v:561|uart_mod.v:300|uart_mod.v:83|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/arith_map.v:56"
.gate SB_CARRY CI=$auto$alumacc.cc:474:replace_alu$15981.C[26] CO=$auto$alumacc.cc:474:replace_alu$15981.C[27] I0=$false I1=$abc$44715$auto$alumacc.cc:474:replace_alu$15981.BB[31]
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:395|uart_mod.v:561|uart_mod.v:300|uart_mod.v:83|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/arith_map.v:56"
.gate SB_CARRY CI=$auto$alumacc.cc:474:replace_alu$15981.C[27] CO=$auto$alumacc.cc:474:replace_alu$15981.C[28] I0=$false I1=$abc$44715$auto$alumacc.cc:474:replace_alu$15981.BB[31]
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:395|uart_mod.v:561|uart_mod.v:300|uart_mod.v:83|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/arith_map.v:56"
.gate SB_CARRY CI=$auto$alumacc.cc:474:replace_alu$15981.C[28] CO=$auto$alumacc.cc:474:replace_alu$15981.C[29] I0=$false I1=$abc$44715$auto$alumacc.cc:474:replace_alu$15981.BB[31]
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:395|uart_mod.v:561|uart_mod.v:300|uart_mod.v:83|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/arith_map.v:56"
.gate SB_CARRY CI=$auto$alumacc.cc:474:replace_alu$15981.C[29] CO=$auto$alumacc.cc:474:replace_alu$15981.C[30] I0=$false I1=$abc$44715$auto$alumacc.cc:474:replace_alu$15981.BB[31]
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:395|uart_mod.v:561|uart_mod.v:300|uart_mod.v:83|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/arith_map.v:56"
.gate SB_CARRY CI=$auto$alumacc.cc:474:replace_alu$15981.C[2] CO=$auto$alumacc.cc:474:replace_alu$15981.C[3] I0=common.pb.uart.tx_mod.symclk.count[2] I1=$abc$44715$auto$alumacc.cc:474:replace_alu$15981.BB[2]
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:395|uart_mod.v:561|uart_mod.v:300|uart_mod.v:83|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/arith_map.v:56"
.gate SB_CARRY CI=$auto$alumacc.cc:474:replace_alu$15981.C[30] CO=$auto$alumacc.cc:474:replace_alu$15981.C[31] I0=$false I1=$abc$44715$auto$alumacc.cc:474:replace_alu$15981.BB[31]
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:395|uart_mod.v:561|uart_mod.v:300|uart_mod.v:83|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/arith_map.v:56"
.gate SB_CARRY CI=$auto$alumacc.cc:474:replace_alu$15981.C[31] CO=$abc$44715$auto$alumacc.cc:491:replace_alu$15983[31] I0=$false I1=$abc$44715$auto$alumacc.cc:474:replace_alu$15981.BB[31]
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:395|uart_mod.v:561|uart_mod.v:300|uart_mod.v:83|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/arith_map.v:56"
.gate SB_CARRY CI=$auto$alumacc.cc:474:replace_alu$15981.C[3] CO=$auto$alumacc.cc:474:replace_alu$15981.C[4] I0=common.pb.uart.tx_mod.symclk.count[3] I1=$abc$44715$auto$alumacc.cc:474:replace_alu$15981.BB[3]
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:395|uart_mod.v:561|uart_mod.v:300|uart_mod.v:83|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/arith_map.v:56"
.gate SB_CARRY CI=$auto$alumacc.cc:474:replace_alu$15981.C[4] CO=$auto$alumacc.cc:474:replace_alu$15981.C[5] I0=common.pb.uart.tx_mod.symclk.count[4] I1=$abc$44715$auto$alumacc.cc:474:replace_alu$15981.BB[4]
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:395|uart_mod.v:561|uart_mod.v:300|uart_mod.v:83|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/arith_map.v:56"
.gate SB_CARRY CI=$auto$alumacc.cc:474:replace_alu$15981.C[5] CO=$auto$alumacc.cc:474:replace_alu$15981.C[6] I0=common.pb.uart.tx_mod.symclk.count[5] I1=$abc$44715$auto$alumacc.cc:474:replace_alu$15981.BB[5]
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:395|uart_mod.v:561|uart_mod.v:300|uart_mod.v:83|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/arith_map.v:56"
.gate SB_CARRY CI=$auto$alumacc.cc:474:replace_alu$15981.C[6] CO=$auto$alumacc.cc:474:replace_alu$15981.C[7] I0=common.pb.uart.tx_mod.symclk.count[6] I1=$abc$44715$auto$alumacc.cc:474:replace_alu$15981.BB[6]
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:395|uart_mod.v:561|uart_mod.v:300|uart_mod.v:83|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/arith_map.v:56"
.gate SB_CARRY CI=$auto$alumacc.cc:474:replace_alu$15981.C[7] CO=$auto$alumacc.cc:474:replace_alu$15981.C[8] I0=common.pb.uart.tx_mod.symclk.count[7] I1=$abc$44715$auto$alumacc.cc:474:replace_alu$15981.BB[7]
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:395|uart_mod.v:561|uart_mod.v:300|uart_mod.v:83|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/arith_map.v:56"
.gate SB_CARRY CI=$auto$alumacc.cc:474:replace_alu$15981.C[8] CO=$auto$alumacc.cc:474:replace_alu$15981.C[9] I0=common.pb.uart.tx_mod.symclk.count[8] I1=$abc$44715$auto$alumacc.cc:474:replace_alu$15981.BB[8]
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:395|uart_mod.v:561|uart_mod.v:300|uart_mod.v:83|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/arith_map.v:56"
.gate SB_CARRY CI=$auto$alumacc.cc:474:replace_alu$15981.C[9] CO=$auto$alumacc.cc:474:replace_alu$15981.C[10] I0=common.pb.uart.tx_mod.symclk.count[9] I1=$abc$44715$auto$alumacc.cc:474:replace_alu$15981.BB[9]
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:395|uart_mod.v:561|uart_mod.v:300|uart_mod.v:83|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/arith_map.v:56"
.gate SB_CARRY CI=$true CO=$auto$alumacc.cc:474:replace_alu$15994.C[1] I0=common.pb.uart.rx_mod.symclk.count[0] I1=$abc$44715$auto$alumacc.cc:474:replace_alu$15981.BB[0]
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:395|uart_mod.v:537|uart_mod.v:154|uart_mod.v:83|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/arith_map.v:56"
.gate SB_CARRY CI=$auto$alumacc.cc:474:replace_alu$15994.C[10] CO=$auto$alumacc.cc:474:replace_alu$15994.C[11] I0=common.pb.uart.rx_mod.symclk.count[10] I1=$abc$44715$auto$alumacc.cc:474:replace_alu$15981.BB[10]
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:395|uart_mod.v:537|uart_mod.v:154|uart_mod.v:83|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/arith_map.v:56"
.gate SB_CARRY CI=$auto$alumacc.cc:474:replace_alu$15994.C[11] CO=$auto$alumacc.cc:474:replace_alu$15994.C[12] I0=common.pb.uart.rx_mod.symclk.count[11] I1=$abc$44715$auto$alumacc.cc:474:replace_alu$15981.BB[11]
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:395|uart_mod.v:537|uart_mod.v:154|uart_mod.v:83|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/arith_map.v:56"
.gate SB_CARRY CI=$auto$alumacc.cc:474:replace_alu$15994.C[12] CO=$auto$alumacc.cc:474:replace_alu$15994.C[13] I0=common.pb.uart.rx_mod.symclk.count[12] I1=$abc$44715$auto$alumacc.cc:474:replace_alu$15981.BB[12]
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:395|uart_mod.v:537|uart_mod.v:154|uart_mod.v:83|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/arith_map.v:56"
.gate SB_CARRY CI=$auto$alumacc.cc:474:replace_alu$15994.C[13] CO=$auto$alumacc.cc:474:replace_alu$15994.C[14] I0=common.pb.uart.rx_mod.symclk.count[13] I1=$abc$44715$auto$alumacc.cc:474:replace_alu$15981.BB[13]
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:395|uart_mod.v:537|uart_mod.v:154|uart_mod.v:83|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/arith_map.v:56"
.gate SB_CARRY CI=$auto$alumacc.cc:474:replace_alu$15994.C[14] CO=$auto$alumacc.cc:474:replace_alu$15994.C[15] I0=common.pb.uart.rx_mod.symclk.count[14] I1=$abc$44715$auto$alumacc.cc:474:replace_alu$15981.BB[14]
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:395|uart_mod.v:537|uart_mod.v:154|uart_mod.v:83|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/arith_map.v:56"
.gate SB_CARRY CI=$auto$alumacc.cc:474:replace_alu$15994.C[15] CO=$auto$alumacc.cc:474:replace_alu$15994.C[16] I0=common.pb.uart.rx_mod.symclk.count[15] I1=$abc$44715$auto$alumacc.cc:474:replace_alu$15981.BB[15]
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:395|uart_mod.v:537|uart_mod.v:154|uart_mod.v:83|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/arith_map.v:56"
.gate SB_CARRY CI=$auto$alumacc.cc:474:replace_alu$15994.C[16] CO=$auto$alumacc.cc:474:replace_alu$15994.C[17] I0=common.pb.uart.rx_mod.symclk.count[16] I1=$abc$44715$auto$alumacc.cc:474:replace_alu$15981.BB[16]
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:395|uart_mod.v:537|uart_mod.v:154|uart_mod.v:83|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/arith_map.v:56"
.gate SB_CARRY CI=$auto$alumacc.cc:474:replace_alu$15994.C[17] CO=$auto$alumacc.cc:474:replace_alu$15994.C[18] I0=common.pb.uart.rx_mod.symclk.count[17] I1=$abc$44715$auto$alumacc.cc:474:replace_alu$15981.BB[17]
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:395|uart_mod.v:537|uart_mod.v:154|uart_mod.v:83|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/arith_map.v:56"
.gate SB_CARRY CI=$auto$alumacc.cc:474:replace_alu$15994.C[18] CO=$auto$alumacc.cc:474:replace_alu$15994.C[19] I0=common.pb.uart.rx_mod.symclk.count[18] I1=$abc$44715$auto$alumacc.cc:474:replace_alu$15981.BB[18]
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:395|uart_mod.v:537|uart_mod.v:154|uart_mod.v:83|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/arith_map.v:56"
.gate SB_CARRY CI=$auto$alumacc.cc:474:replace_alu$15994.C[19] CO=$auto$alumacc.cc:474:replace_alu$15994.C[20] I0=common.pb.uart.rx_mod.symclk.count[19] I1=$abc$44715$auto$alumacc.cc:474:replace_alu$15981.BB[19]
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:395|uart_mod.v:537|uart_mod.v:154|uart_mod.v:83|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/arith_map.v:56"
.gate SB_CARRY CI=$auto$alumacc.cc:474:replace_alu$15994.C[1] CO=$auto$alumacc.cc:474:replace_alu$15994.C[2] I0=common.pb.uart.rx_mod.symclk.count[1] I1=$abc$44715$auto$alumacc.cc:474:replace_alu$15981.BB[1]
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:395|uart_mod.v:537|uart_mod.v:154|uart_mod.v:83|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/arith_map.v:56"
.gate SB_CARRY CI=$auto$alumacc.cc:474:replace_alu$15994.C[20] CO=$auto$alumacc.cc:474:replace_alu$15994.C[21] I0=common.pb.uart.rx_mod.symclk.count[20] I1=$abc$44715$auto$alumacc.cc:474:replace_alu$15981.BB[20]
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:395|uart_mod.v:537|uart_mod.v:154|uart_mod.v:83|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/arith_map.v:56"
.gate SB_CARRY CI=$auto$alumacc.cc:474:replace_alu$15994.C[21] CO=$auto$alumacc.cc:474:replace_alu$15994.C[22] I0=common.pb.uart.rx_mod.symclk.count[21] I1=$abc$44715$auto$alumacc.cc:474:replace_alu$15981.BB[21]
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:395|uart_mod.v:537|uart_mod.v:154|uart_mod.v:83|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/arith_map.v:56"
.gate SB_CARRY CI=$auto$alumacc.cc:474:replace_alu$15994.C[22] CO=$auto$alumacc.cc:474:replace_alu$15994.C[23] I0=common.pb.uart.rx_mod.symclk.count[22] I1=$abc$44715$auto$alumacc.cc:474:replace_alu$15981.BB[22]
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:395|uart_mod.v:537|uart_mod.v:154|uart_mod.v:83|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/arith_map.v:56"
.gate SB_CARRY CI=$auto$alumacc.cc:474:replace_alu$15994.C[23] CO=$auto$alumacc.cc:474:replace_alu$15994.C[24] I0=common.pb.uart.rx_mod.symclk.count[23] I1=$abc$44715$auto$alumacc.cc:474:replace_alu$15981.BB[23]
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:395|uart_mod.v:537|uart_mod.v:154|uart_mod.v:83|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/arith_map.v:56"
.gate SB_CARRY CI=$auto$alumacc.cc:474:replace_alu$15994.C[24] CO=$auto$alumacc.cc:474:replace_alu$15994.C[25] I0=$false I1=$abc$44715$auto$alumacc.cc:474:replace_alu$15981.BB[24]
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:395|uart_mod.v:537|uart_mod.v:154|uart_mod.v:83|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/arith_map.v:56"
.gate SB_CARRY CI=$auto$alumacc.cc:474:replace_alu$15994.C[25] CO=$auto$alumacc.cc:474:replace_alu$15994.C[26] I0=$false I1=$abc$44715$auto$alumacc.cc:474:replace_alu$15981.BB[31]
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:395|uart_mod.v:537|uart_mod.v:154|uart_mod.v:83|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/arith_map.v:56"
.gate SB_CARRY CI=$auto$alumacc.cc:474:replace_alu$15994.C[26] CO=$auto$alumacc.cc:474:replace_alu$15994.C[27] I0=$false I1=$abc$44715$auto$alumacc.cc:474:replace_alu$15981.BB[31]
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:395|uart_mod.v:537|uart_mod.v:154|uart_mod.v:83|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/arith_map.v:56"
.gate SB_CARRY CI=$auto$alumacc.cc:474:replace_alu$15994.C[27] CO=$auto$alumacc.cc:474:replace_alu$15994.C[28] I0=$false I1=$abc$44715$auto$alumacc.cc:474:replace_alu$15981.BB[31]
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:395|uart_mod.v:537|uart_mod.v:154|uart_mod.v:83|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/arith_map.v:56"
.gate SB_CARRY CI=$auto$alumacc.cc:474:replace_alu$15994.C[28] CO=$auto$alumacc.cc:474:replace_alu$15994.C[29] I0=$false I1=$abc$44715$auto$alumacc.cc:474:replace_alu$15981.BB[31]
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:395|uart_mod.v:537|uart_mod.v:154|uart_mod.v:83|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/arith_map.v:56"
.gate SB_CARRY CI=$auto$alumacc.cc:474:replace_alu$15994.C[29] CO=$auto$alumacc.cc:474:replace_alu$15994.C[30] I0=$false I1=$abc$44715$auto$alumacc.cc:474:replace_alu$15981.BB[31]
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:395|uart_mod.v:537|uart_mod.v:154|uart_mod.v:83|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/arith_map.v:56"
.gate SB_CARRY CI=$auto$alumacc.cc:474:replace_alu$15994.C[2] CO=$auto$alumacc.cc:474:replace_alu$15994.C[3] I0=common.pb.uart.rx_mod.symclk.count[2] I1=$abc$44715$auto$alumacc.cc:474:replace_alu$15981.BB[2]
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:395|uart_mod.v:537|uart_mod.v:154|uart_mod.v:83|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/arith_map.v:56"
.gate SB_CARRY CI=$auto$alumacc.cc:474:replace_alu$15994.C[30] CO=$auto$alumacc.cc:474:replace_alu$15994.C[31] I0=$false I1=$abc$44715$auto$alumacc.cc:474:replace_alu$15981.BB[31]
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:395|uart_mod.v:537|uart_mod.v:154|uart_mod.v:83|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/arith_map.v:56"
.gate SB_CARRY CI=$auto$alumacc.cc:474:replace_alu$15994.C[31] CO=$abc$44715$auto$alumacc.cc:491:replace_alu$15996[31] I0=$false I1=$abc$44715$auto$alumacc.cc:474:replace_alu$15981.BB[31]
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:395|uart_mod.v:537|uart_mod.v:154|uart_mod.v:83|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/arith_map.v:56"
.gate SB_CARRY CI=$auto$alumacc.cc:474:replace_alu$15994.C[3] CO=$auto$alumacc.cc:474:replace_alu$15994.C[4] I0=common.pb.uart.rx_mod.symclk.count[3] I1=$abc$44715$auto$alumacc.cc:474:replace_alu$15981.BB[3]
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:395|uart_mod.v:537|uart_mod.v:154|uart_mod.v:83|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/arith_map.v:56"
.gate SB_CARRY CI=$auto$alumacc.cc:474:replace_alu$15994.C[4] CO=$auto$alumacc.cc:474:replace_alu$15994.C[5] I0=common.pb.uart.rx_mod.symclk.count[4] I1=$abc$44715$auto$alumacc.cc:474:replace_alu$15981.BB[4]
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:395|uart_mod.v:537|uart_mod.v:154|uart_mod.v:83|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/arith_map.v:56"
.gate SB_CARRY CI=$auto$alumacc.cc:474:replace_alu$15994.C[5] CO=$auto$alumacc.cc:474:replace_alu$15994.C[6] I0=common.pb.uart.rx_mod.symclk.count[5] I1=$abc$44715$auto$alumacc.cc:474:replace_alu$15981.BB[5]
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:395|uart_mod.v:537|uart_mod.v:154|uart_mod.v:83|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/arith_map.v:56"
.gate SB_CARRY CI=$auto$alumacc.cc:474:replace_alu$15994.C[6] CO=$auto$alumacc.cc:474:replace_alu$15994.C[7] I0=common.pb.uart.rx_mod.symclk.count[6] I1=$abc$44715$auto$alumacc.cc:474:replace_alu$15981.BB[6]
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:395|uart_mod.v:537|uart_mod.v:154|uart_mod.v:83|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/arith_map.v:56"
.gate SB_CARRY CI=$auto$alumacc.cc:474:replace_alu$15994.C[7] CO=$auto$alumacc.cc:474:replace_alu$15994.C[8] I0=common.pb.uart.rx_mod.symclk.count[7] I1=$abc$44715$auto$alumacc.cc:474:replace_alu$15981.BB[7]
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:395|uart_mod.v:537|uart_mod.v:154|uart_mod.v:83|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/arith_map.v:56"
.gate SB_CARRY CI=$auto$alumacc.cc:474:replace_alu$15994.C[8] CO=$auto$alumacc.cc:474:replace_alu$15994.C[9] I0=common.pb.uart.rx_mod.symclk.count[8] I1=$abc$44715$auto$alumacc.cc:474:replace_alu$15981.BB[8]
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:395|uart_mod.v:537|uart_mod.v:154|uart_mod.v:83|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/arith_map.v:56"
.gate SB_CARRY CI=$auto$alumacc.cc:474:replace_alu$15994.C[9] CO=$auto$alumacc.cc:474:replace_alu$15994.C[10] I0=common.pb.uart.rx_mod.symclk.count[9] I1=$abc$44715$auto$alumacc.cc:474:replace_alu$15981.BB[9]
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:395|uart_mod.v:537|uart_mod.v:154|uart_mod.v:83|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/arith_map.v:56"
.gate SB_CARRY CI=$auto$alumacc.cc:474:replace_alu$16007.C[10] CO=$auto$alumacc.cc:474:replace_alu$16007.C[11] I0=$false I1=$abc$44715$auto$alumacc.cc:474:replace_alu$16007.BB[10]
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:395|uart_mod.v:537|uart_mod.v:154|uart_mod.v:61|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/arith_map.v:56"
.gate SB_CARRY CI=$auto$alumacc.cc:474:replace_alu$16007.C[11] CO=$auto$alumacc.cc:474:replace_alu$16007.C[12] I0=$false I1=$abc$44715$auto$alumacc.cc:474:replace_alu$16007.BB[11]
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:395|uart_mod.v:537|uart_mod.v:154|uart_mod.v:61|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/arith_map.v:56"
.gate SB_CARRY CI=$auto$alumacc.cc:474:replace_alu$16007.C[12] CO=$auto$alumacc.cc:474:replace_alu$16007.C[13] I0=$false I1=$abc$44715$auto$alumacc.cc:474:replace_alu$16007.BB[12]
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:395|uart_mod.v:537|uart_mod.v:154|uart_mod.v:61|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/arith_map.v:56"
.gate SB_CARRY CI=$auto$alumacc.cc:474:replace_alu$16007.C[13] CO=$auto$alumacc.cc:474:replace_alu$16007.C[14] I0=$false I1=$abc$44715$auto$alumacc.cc:474:replace_alu$16007.BB[13]
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:395|uart_mod.v:537|uart_mod.v:154|uart_mod.v:61|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/arith_map.v:56"
.gate SB_CARRY CI=$auto$alumacc.cc:474:replace_alu$16007.C[14] CO=$auto$alumacc.cc:474:replace_alu$16007.C[15] I0=$false I1=$abc$44715$auto$alumacc.cc:474:replace_alu$16007.BB[14]
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:395|uart_mod.v:537|uart_mod.v:154|uart_mod.v:61|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/arith_map.v:56"
.gate SB_CARRY CI=$auto$alumacc.cc:474:replace_alu$16007.C[15] CO=$auto$alumacc.cc:474:replace_alu$16007.C[16] I0=$false I1=$abc$44715$auto$alumacc.cc:474:replace_alu$16007.BB[15]
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:395|uart_mod.v:537|uart_mod.v:154|uart_mod.v:61|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/arith_map.v:56"
.gate SB_CARRY CI=$auto$alumacc.cc:474:replace_alu$16007.C[16] CO=$auto$alumacc.cc:474:replace_alu$16007.C[17] I0=$false I1=$abc$44715$auto$alumacc.cc:474:replace_alu$16007.BB[16]
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:395|uart_mod.v:537|uart_mod.v:154|uart_mod.v:61|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/arith_map.v:56"
.gate SB_CARRY CI=$auto$alumacc.cc:474:replace_alu$16007.C[17] CO=$auto$alumacc.cc:474:replace_alu$16007.C[18] I0=$false I1=$abc$44715$auto$alumacc.cc:474:replace_alu$16007.BB[17]
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:395|uart_mod.v:537|uart_mod.v:154|uart_mod.v:61|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/arith_map.v:56"
.gate SB_CARRY CI=$auto$alumacc.cc:474:replace_alu$16007.C[18] CO=$auto$alumacc.cc:474:replace_alu$16007.C[19] I0=$false I1=$abc$44715$auto$alumacc.cc:474:replace_alu$16007.BB[18]
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:395|uart_mod.v:537|uart_mod.v:154|uart_mod.v:61|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/arith_map.v:56"
.gate SB_CARRY CI=$auto$alumacc.cc:474:replace_alu$16007.C[19] CO=$auto$alumacc.cc:474:replace_alu$16007.C[20] I0=$false I1=$abc$44715$auto$alumacc.cc:474:replace_alu$16007.BB[19]
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:395|uart_mod.v:537|uart_mod.v:154|uart_mod.v:61|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/arith_map.v:56"
.gate SB_CARRY CI=$abc$44715$auto$alumacc.cc:474:replace_alu$16007.BB[0] CO=$auto$alumacc.cc:474:replace_alu$16007.C[2] I0=$false I1=$abc$44715$auto$alumacc.cc:474:replace_alu$16007.BB[1]
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:395|uart_mod.v:537|uart_mod.v:154|uart_mod.v:61|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/arith_map.v:56"
.gate SB_CARRY CI=$auto$alumacc.cc:474:replace_alu$16007.C[20] CO=$auto$alumacc.cc:474:replace_alu$16007.C[21] I0=$false I1=$abc$44715$auto$alumacc.cc:474:replace_alu$16007.BB[20]
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:395|uart_mod.v:537|uart_mod.v:154|uart_mod.v:61|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/arith_map.v:56"
.gate SB_CARRY CI=$auto$alumacc.cc:474:replace_alu$16007.C[21] CO=$auto$alumacc.cc:474:replace_alu$16007.C[22] I0=$false I1=$abc$44715$auto$alumacc.cc:474:replace_alu$16007.BB[21]
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:395|uart_mod.v:537|uart_mod.v:154|uart_mod.v:61|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/arith_map.v:56"
.gate SB_CARRY CI=$auto$alumacc.cc:474:replace_alu$16007.C[22] CO=$auto$alumacc.cc:474:replace_alu$16007.C[23] I0=$false I1=$abc$44715$auto$alumacc.cc:474:replace_alu$16007.BB[22]
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:395|uart_mod.v:537|uart_mod.v:154|uart_mod.v:61|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/arith_map.v:56"
.gate SB_CARRY CI=$auto$alumacc.cc:474:replace_alu$16007.C[23] CO=$abc$44715$auto$alumacc.cc:491:replace_alu$16009[23] I0=$false I1=$abc$44715$auto$alumacc.cc:474:replace_alu$16007.BB[23]
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:395|uart_mod.v:537|uart_mod.v:154|uart_mod.v:61|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/arith_map.v:56"
.gate SB_CARRY CI=$auto$alumacc.cc:474:replace_alu$16007.C[2] CO=$auto$alumacc.cc:474:replace_alu$16007.C[3] I0=$true I1=$abc$44715$auto$alumacc.cc:474:replace_alu$16007.BB[2]
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:395|uart_mod.v:537|uart_mod.v:154|uart_mod.v:61|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/arith_map.v:56"
.gate SB_CARRY CI=$auto$alumacc.cc:474:replace_alu$16007.C[3] CO=$auto$alumacc.cc:474:replace_alu$16007.C[4] I0=$false I1=$abc$44715$auto$alumacc.cc:474:replace_alu$16007.BB[3]
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:395|uart_mod.v:537|uart_mod.v:154|uart_mod.v:61|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/arith_map.v:56"
.gate SB_CARRY CI=$auto$alumacc.cc:474:replace_alu$16007.C[4] CO=$auto$alumacc.cc:474:replace_alu$16007.C[5] I0=$false I1=$abc$44715$auto$alumacc.cc:474:replace_alu$16007.BB[4]
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:395|uart_mod.v:537|uart_mod.v:154|uart_mod.v:61|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/arith_map.v:56"
.gate SB_CARRY CI=$auto$alumacc.cc:474:replace_alu$16007.C[5] CO=$auto$alumacc.cc:474:replace_alu$16007.C[6] I0=$false I1=$abc$44715$auto$alumacc.cc:474:replace_alu$16007.BB[5]
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:395|uart_mod.v:537|uart_mod.v:154|uart_mod.v:61|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/arith_map.v:56"
.gate SB_CARRY CI=$auto$alumacc.cc:474:replace_alu$16007.C[6] CO=$auto$alumacc.cc:474:replace_alu$16007.C[7] I0=$false I1=$abc$44715$auto$alumacc.cc:474:replace_alu$16007.BB[6]
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:395|uart_mod.v:537|uart_mod.v:154|uart_mod.v:61|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/arith_map.v:56"
.gate SB_CARRY CI=$auto$alumacc.cc:474:replace_alu$16007.C[7] CO=$auto$alumacc.cc:474:replace_alu$16007.C[8] I0=$false I1=$abc$44715$auto$alumacc.cc:474:replace_alu$16007.BB[7]
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:395|uart_mod.v:537|uart_mod.v:154|uart_mod.v:61|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/arith_map.v:56"
.gate SB_CARRY CI=$auto$alumacc.cc:474:replace_alu$16007.C[8] CO=$auto$alumacc.cc:474:replace_alu$16007.C[9] I0=$false I1=$abc$44715$auto$alumacc.cc:474:replace_alu$16007.BB[8]
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:395|uart_mod.v:537|uart_mod.v:154|uart_mod.v:61|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/arith_map.v:56"
.gate SB_CARRY CI=$auto$alumacc.cc:474:replace_alu$16007.C[9] CO=$auto$alumacc.cc:474:replace_alu$16007.C[10] I0=$false I1=$abc$44715$auto$alumacc.cc:474:replace_alu$16007.BB[9]
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:395|uart_mod.v:537|uart_mod.v:154|uart_mod.v:61|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/arith_map.v:56"
.gate SB_CARRY CI=common.pb.spirx_lencalc_byte[0] CO=$auto$alumacc.cc:474:replace_alu$16016.C[2] I0=common.pb.spirx_lencalc_byte[1] I1=$true
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:566|profibus_phy_mod.v:144|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/arith_map.v:56"
.gate SB_CARRY CI=$auto$alumacc.cc:474:replace_alu$16016.C[2] CO=$auto$alumacc.cc:474:replace_alu$16016.C[3] I0=common.pb.spirx_lencalc_byte[2] I1=$true
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:566|profibus_phy_mod.v:144|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/arith_map.v:56"
.gate SB_CARRY CI=$auto$alumacc.cc:474:replace_alu$16016.C[3] CO=$auto$alumacc.cc:474:replace_alu$16016.C[4] I0=common.pb.spirx_lencalc_byte[3] I1=$false
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:566|profibus_phy_mod.v:144|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/arith_map.v:56"
.gate SB_CARRY CI=$auto$alumacc.cc:474:replace_alu$16016.C[4] CO=$auto$alumacc.cc:474:replace_alu$16016.C[5] I0=common.pb.spirx_lencalc_byte[4] I1=$false
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:566|profibus_phy_mod.v:144|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/arith_map.v:56"
.gate SB_CARRY CI=$auto$alumacc.cc:474:replace_alu$16016.C[5] CO=$auto$alumacc.cc:474:replace_alu$16016.C[6] I0=common.pb.spirx_lencalc_byte[5] I1=$false
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:566|profibus_phy_mod.v:144|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/arith_map.v:56"
.gate SB_CARRY CI=$auto$alumacc.cc:474:replace_alu$16016.C[6] CO=$auto$alumacc.cc:474:replace_alu$16016.C[7] I0=common.pb.spirx_lencalc_byte[6] I1=$false
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:566|profibus_phy_mod.v:144|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/arith_map.v:56"
.gate SB_CARRY CI=$auto$alumacc.cc:474:replace_alu$16016.C[7] CO=$abc$44715$auto$alumacc.cc:491:replace_alu$16018[7] I0=common.pb.spirx_lencalc_byte[7] I1=$false
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:566|profibus_phy_mod.v:144|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/arith_map.v:56"
.gate SB_CARRY CI=$abc$44715$auto$alumacc.cc:474:replace_alu$16025.BB[0] CO=$auto$alumacc.cc:474:replace_alu$16025.C[2] I0=$false I1=$abc$44715$auto$alumacc.cc:474:replace_alu$16025.BB[1]
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:566|profibus_phy_mod.v:144|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/arith_map.v:56"
.gate SB_CARRY CI=$auto$alumacc.cc:474:replace_alu$16025.C[2] CO=$auto$alumacc.cc:474:replace_alu$16025.C[3] I0=$true I1=$abc$44715$auto$alumacc.cc:474:replace_alu$16025.BB[2]
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:566|profibus_phy_mod.v:144|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/arith_map.v:56"
.gate SB_CARRY CI=$auto$alumacc.cc:474:replace_alu$16025.C[3] CO=$auto$alumacc.cc:474:replace_alu$16025.C[4] I0=$false I1=$abc$44715$auto$alumacc.cc:474:replace_alu$16025.BB[3]
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:566|profibus_phy_mod.v:144|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/arith_map.v:56"
.gate SB_CARRY CI=$auto$alumacc.cc:474:replace_alu$16025.C[4] CO=$auto$alumacc.cc:474:replace_alu$16025.C[5] I0=$false I1=$abc$44715$auto$alumacc.cc:474:replace_alu$16025.BB[4]
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:566|profibus_phy_mod.v:144|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/arith_map.v:56"
.gate SB_CARRY CI=$auto$alumacc.cc:474:replace_alu$16025.C[5] CO=$auto$alumacc.cc:474:replace_alu$16025.C[6] I0=$false I1=$abc$44715$auto$alumacc.cc:474:replace_alu$16025.BB[5]
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:566|profibus_phy_mod.v:144|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/arith_map.v:56"
.gate SB_CARRY CI=$auto$alumacc.cc:474:replace_alu$16025.C[6] CO=$auto$alumacc.cc:474:replace_alu$16025.C[7] I0=$false I1=$abc$44715$auto$alumacc.cc:474:replace_alu$16025.BB[6]
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:566|profibus_phy_mod.v:144|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/arith_map.v:56"
.gate SB_CARRY CI=$auto$alumacc.cc:474:replace_alu$16025.C[7] CO=$abc$44715$auto$alumacc.cc:491:replace_alu$16027[7] I0=$false I1=$abc$44715$auto$alumacc.cc:474:replace_alu$16025.BB[7]
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:566|profibus_phy_mod.v:144|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/arith_map.v:56"
.gate SB_CARRY CI=$abc$44715$auto$alumacc.cc:474:replace_alu$16034.BB[0] CO=$auto$alumacc.cc:474:replace_alu$16034.C[2] I0=$false I1=$abc$44715$auto$alumacc.cc:474:replace_alu$16034.BB[1]
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:438|spi_slave_mod.v:138|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/arith_map.v:56"
.gate SB_CARRY CI=$auto$alumacc.cc:474:replace_alu$16034.C[2] CO=$auto$alumacc.cc:474:replace_alu$16034.C[3] I0=$false I1=$abc$44715$auto$alumacc.cc:474:replace_alu$16034.BB[2]
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:438|spi_slave_mod.v:138|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/arith_map.v:56"
.gate SB_CARRY CI=$auto$alumacc.cc:474:replace_alu$16034.C[3] CO=$auto$alumacc.cc:474:replace_alu$16034.C[4] I0=$true I1=$abc$44715$auto$alumacc.cc:474:replace_alu$16034.BB[3]
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:438|spi_slave_mod.v:138|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/arith_map.v:56"
.gate SB_CARRY CI=$auto$alumacc.cc:474:replace_alu$16034.C[4] CO=$auto$alumacc.cc:474:replace_alu$16034.C[5] I0=$false I1=$abc$44715$auto$alumacc.cc:474:replace_alu$16034.BB[4]
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:438|spi_slave_mod.v:138|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/arith_map.v:56"
.gate SB_CARRY CI=$auto$alumacc.cc:474:replace_alu$16034.C[5] CO=$abc$44715$auto$alumacc.cc:491:replace_alu$16036[5] I0=$false I1=$abc$44715$auto$alumacc.cc:474:replace_alu$16034.BB[5]
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:438|spi_slave_mod.v:138|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/arith_map.v:56"
.gate SB_CARRY CI=$auto$alumacc.cc:474:replace_alu$16047.C[10] CO=$auto$alumacc.cc:474:replace_alu$16047.C[11] I0=common.pb.timer_idle[10] I1=$false
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:1058|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/arith_map.v:56"
.gate SB_CARRY CI=$auto$alumacc.cc:474:replace_alu$16047.C[11] CO=$auto$alumacc.cc:474:replace_alu$16047.C[12] I0=common.pb.timer_idle[11] I1=$false
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:1058|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/arith_map.v:56"
.gate SB_CARRY CI=$auto$alumacc.cc:474:replace_alu$16047.C[12] CO=$auto$alumacc.cc:474:replace_alu$16047.C[13] I0=common.pb.timer_idle[12] I1=$false
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:1058|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/arith_map.v:56"
.gate SB_CARRY CI=$auto$alumacc.cc:474:replace_alu$16047.C[13] CO=$auto$alumacc.cc:474:replace_alu$16047.C[14] I0=common.pb.timer_idle[13] I1=$false
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:1058|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/arith_map.v:56"
.gate SB_CARRY CI=$auto$alumacc.cc:474:replace_alu$16047.C[14] CO=$auto$alumacc.cc:474:replace_alu$16047.C[15] I0=common.pb.timer_idle[14] I1=$false
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:1058|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/arith_map.v:56"
.gate SB_CARRY CI=$auto$alumacc.cc:474:replace_alu$16047.C[15] CO=$auto$alumacc.cc:474:replace_alu$16047.C[16] I0=common.pb.timer_idle[15] I1=$false
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:1058|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/arith_map.v:56"
.gate SB_CARRY CI=$auto$alumacc.cc:474:replace_alu$16047.C[16] CO=$auto$alumacc.cc:474:replace_alu$16047.C[17] I0=common.pb.timer_idle[16] I1=$false
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:1058|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/arith_map.v:56"
.gate SB_CARRY CI=$auto$alumacc.cc:474:replace_alu$16047.C[17] CO=$auto$alumacc.cc:474:replace_alu$16047.C[18] I0=common.pb.timer_idle[17] I1=$false
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:1058|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/arith_map.v:56"
.gate SB_CARRY CI=$auto$alumacc.cc:474:replace_alu$16047.C[18] CO=$auto$alumacc.cc:474:replace_alu$16047.C[19] I0=common.pb.timer_idle[18] I1=$false
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:1058|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/arith_map.v:56"
.gate SB_CARRY CI=$auto$alumacc.cc:474:replace_alu$16047.C[19] CO=$auto$alumacc.cc:474:replace_alu$16047.C[20] I0=common.pb.timer_idle[19] I1=$false
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:1058|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/arith_map.v:56"
.gate SB_CARRY CI=common.pb.timer_idle[0] CO=$auto$alumacc.cc:474:replace_alu$16047.C[2] I0=common.pb.timer_idle[1] I1=$false
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:1058|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/arith_map.v:56"
.gate SB_CARRY CI=$auto$alumacc.cc:474:replace_alu$16047.C[20] CO=$auto$alumacc.cc:474:replace_alu$16047.C[21] I0=common.pb.timer_idle[20] I1=$false
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:1058|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/arith_map.v:56"
.gate SB_CARRY CI=$auto$alumacc.cc:474:replace_alu$16047.C[21] CO=$auto$alumacc.cc:474:replace_alu$16047.C[22] I0=common.pb.timer_idle[21] I1=$false
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:1058|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/arith_map.v:56"
.gate SB_CARRY CI=$auto$alumacc.cc:474:replace_alu$16047.C[22] CO=$auto$alumacc.cc:474:replace_alu$16047.C[23] I0=common.pb.timer_idle[22] I1=$false
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:1058|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/arith_map.v:56"
.gate SB_CARRY CI=$auto$alumacc.cc:474:replace_alu$16047.C[23] CO=$abc$44715$auto$alumacc.cc:491:replace_alu$16049[23] I0=common.pb.timer_idle[23] I1=$false
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:1058|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/arith_map.v:56"
.gate SB_CARRY CI=$auto$alumacc.cc:474:replace_alu$16047.C[2] CO=$auto$alumacc.cc:474:replace_alu$16047.C[3] I0=common.pb.timer_idle[2] I1=$false
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:1058|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/arith_map.v:56"
.gate SB_CARRY CI=$auto$alumacc.cc:474:replace_alu$16047.C[3] CO=$auto$alumacc.cc:474:replace_alu$16047.C[4] I0=common.pb.timer_idle[3] I1=$false
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:1058|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/arith_map.v:56"
.gate SB_CARRY CI=$auto$alumacc.cc:474:replace_alu$16047.C[4] CO=$auto$alumacc.cc:474:replace_alu$16047.C[5] I0=common.pb.timer_idle[4] I1=$false
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:1058|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/arith_map.v:56"
.gate SB_CARRY CI=$auto$alumacc.cc:474:replace_alu$16047.C[5] CO=$auto$alumacc.cc:474:replace_alu$16047.C[6] I0=common.pb.timer_idle[5] I1=$false
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:1058|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/arith_map.v:56"
.gate SB_CARRY CI=$auto$alumacc.cc:474:replace_alu$16047.C[6] CO=$auto$alumacc.cc:474:replace_alu$16047.C[7] I0=common.pb.timer_idle[6] I1=$false
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:1058|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/arith_map.v:56"
.gate SB_CARRY CI=$auto$alumacc.cc:474:replace_alu$16047.C[7] CO=$auto$alumacc.cc:474:replace_alu$16047.C[8] I0=common.pb.timer_idle[7] I1=$false
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:1058|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/arith_map.v:56"
.gate SB_CARRY CI=$auto$alumacc.cc:474:replace_alu$16047.C[8] CO=$auto$alumacc.cc:474:replace_alu$16047.C[9] I0=common.pb.timer_idle[8] I1=$false
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:1058|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/arith_map.v:56"
.gate SB_CARRY CI=$auto$alumacc.cc:474:replace_alu$16047.C[9] CO=$auto$alumacc.cc:474:replace_alu$16047.C[10] I0=common.pb.timer_idle[9] I1=$false
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:1058|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/arith_map.v:56"
.gate SB_CARRY CI=$abc$44715$auto$alumacc.cc:474:replace_alu$16052.BB[1] CO=$auto$alumacc.cc:474:replace_alu$16052.C[3] I0=$false I1=$abc$44715$auto$alumacc.cc:474:replace_alu$16052.BB[2]
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:988|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/arith_map.v:56"
.gate SB_CARRY CI=$auto$alumacc.cc:474:replace_alu$16052.C[3] CO=$auto$alumacc.cc:474:replace_alu$16052.C[4] I0=$true I1=$abc$44715$auto$alumacc.cc:474:replace_alu$16052.BB[3]
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:988|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/arith_map.v:56"
.gate SB_CARRY CI=$auto$alumacc.cc:474:replace_alu$16052.C[4] CO=$auto$alumacc.cc:474:replace_alu$16052.C[5] I0=$false I1=$abc$44715$auto$alumacc.cc:474:replace_alu$16052.BB[4]
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:988|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/arith_map.v:56"
.gate SB_CARRY CI=$auto$alumacc.cc:474:replace_alu$16052.C[5] CO=$auto$alumacc.cc:474:replace_alu$16052.C[6] I0=$false I1=$abc$44715$auto$alumacc.cc:474:replace_alu$16052.BB[5]
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:988|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/arith_map.v:56"
.gate SB_CARRY CI=$auto$alumacc.cc:474:replace_alu$16052.C[6] CO=$auto$alumacc.cc:474:replace_alu$16052.C[7] I0=$false I1=$abc$44715$auto$alumacc.cc:474:replace_alu$16052.BB[6]
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:988|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/arith_map.v:56"
.gate SB_CARRY CI=$auto$alumacc.cc:474:replace_alu$16052.C[7] CO=$abc$44715$auto$alumacc.cc:491:replace_alu$16054[7] I0=$false I1=$abc$44715$auto$alumacc.cc:474:replace_alu$16052.BB[7]
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:988|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/arith_map.v:56"
.gate SB_CARRY CI=$abc$44715$auto$alumacc.cc:474:replace_alu$16052.BB[2] CO=$auto$alumacc.cc:474:replace_alu$16065.C[4] I0=$false I1=$abc$44715$auto$alumacc.cc:474:replace_alu$16052.BB[3]
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:991|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/arith_map.v:56"
.gate SB_CARRY CI=$auto$alumacc.cc:474:replace_alu$16065.C[4] CO=$auto$alumacc.cc:474:replace_alu$16065.C[5] I0=$false I1=$abc$44715$auto$alumacc.cc:474:replace_alu$16052.BB[4]
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:991|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/arith_map.v:56"
.gate SB_CARRY CI=$auto$alumacc.cc:474:replace_alu$16065.C[5] CO=$auto$alumacc.cc:474:replace_alu$16065.C[6] I0=$false I1=$abc$44715$auto$alumacc.cc:474:replace_alu$16052.BB[5]
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:991|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/arith_map.v:56"
.gate SB_CARRY CI=$auto$alumacc.cc:474:replace_alu$16065.C[6] CO=$auto$alumacc.cc:474:replace_alu$16065.C[7] I0=$false I1=$abc$44715$auto$alumacc.cc:474:replace_alu$16052.BB[6]
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:991|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/arith_map.v:56"
.gate SB_CARRY CI=$auto$alumacc.cc:474:replace_alu$16065.C[7] CO=$abc$44715$auto$alumacc.cc:491:replace_alu$16067[7] I0=$false I1=$abc$44715$auto$alumacc.cc:474:replace_alu$16052.BB[7]
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:991|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/arith_map.v:56"
.gate SB_CARRY CI=$abc$44715$auto$alumacc.cc:474:replace_alu$16052.BB[0] CO=$auto$alumacc.cc:474:replace_alu$16074.C[2] I0=$true I1=$abc$44715$auto$alumacc.cc:474:replace_alu$16052.BB[1]
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:988|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/arith_map.v:56"
.gate SB_CARRY CI=$auto$alumacc.cc:474:replace_alu$16074.C[2] CO=$auto$alumacc.cc:474:replace_alu$16074.C[3] I0=$false I1=$abc$44715$auto$alumacc.cc:474:replace_alu$16052.BB[2]
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:988|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/arith_map.v:56"
.gate SB_CARRY CI=$auto$alumacc.cc:474:replace_alu$16074.C[3] CO=$auto$alumacc.cc:474:replace_alu$16074.C[4] I0=$false I1=$abc$44715$auto$alumacc.cc:474:replace_alu$16052.BB[3]
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:988|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/arith_map.v:56"
.gate SB_CARRY CI=$auto$alumacc.cc:474:replace_alu$16074.C[4] CO=$auto$alumacc.cc:474:replace_alu$16074.C[5] I0=$false I1=$abc$44715$auto$alumacc.cc:474:replace_alu$16052.BB[4]
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:988|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/arith_map.v:56"
.gate SB_CARRY CI=$auto$alumacc.cc:474:replace_alu$16074.C[5] CO=$auto$alumacc.cc:474:replace_alu$16074.C[6] I0=$false I1=$abc$44715$auto$alumacc.cc:474:replace_alu$16052.BB[5]
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:988|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/arith_map.v:56"
.gate SB_CARRY CI=$auto$alumacc.cc:474:replace_alu$16074.C[6] CO=$auto$alumacc.cc:474:replace_alu$16074.C[7] I0=$false I1=$abc$44715$auto$alumacc.cc:474:replace_alu$16052.BB[6]
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:988|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/arith_map.v:56"
.gate SB_CARRY CI=$auto$alumacc.cc:474:replace_alu$16074.C[7] CO=$abc$44715$auto$alumacc.cc:491:replace_alu$16076[7] I0=$false I1=$abc$44715$auto$alumacc.cc:474:replace_alu$16052.BB[7]
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:988|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/arith_map.v:56"
.gate SB_CARRY CI=$abc$44715$auto$alumacc.cc:474:replace_alu$16083.BB[2] CO=$auto$alumacc.cc:474:replace_alu$16083.C[4] I0=$false I1=$abc$44715$auto$alumacc.cc:474:replace_alu$16083.BB[3]
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:712|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/arith_map.v:56"
.gate SB_CARRY CI=$auto$alumacc.cc:474:replace_alu$16083.C[4] CO=$auto$alumacc.cc:474:replace_alu$16083.C[5] I0=$false I1=$abc$44715$auto$alumacc.cc:474:replace_alu$16083.BB[4]
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:712|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/arith_map.v:56"
.gate SB_CARRY CI=$auto$alumacc.cc:474:replace_alu$16083.C[5] CO=$auto$alumacc.cc:474:replace_alu$16083.C[6] I0=$false I1=$abc$44715$auto$alumacc.cc:474:replace_alu$16083.BB[5]
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:712|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/arith_map.v:56"
.gate SB_CARRY CI=$auto$alumacc.cc:474:replace_alu$16083.C[6] CO=$auto$alumacc.cc:474:replace_alu$16083.C[7] I0=$false I1=$abc$44715$auto$alumacc.cc:474:replace_alu$16083.BB[6]
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:712|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/arith_map.v:56"
.gate SB_CARRY CI=$auto$alumacc.cc:474:replace_alu$16083.C[7] CO=$abc$44715$auto$alumacc.cc:491:replace_alu$16085[7] I0=$false I1=$abc$44715$auto$alumacc.cc:474:replace_alu$16083.BB[7]
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:712|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/arith_map.v:56"
.gate SB_CARRY CI=$true CO=$auto$alumacc.cc:474:replace_alu$16092.C[1] I0=common.pb.spirx_bytecount[0] I1=$abc$44715$auto$alumacc.cc:474:replace_alu$16092.BB[0]
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:661|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/arith_map.v:56"
.gate SB_CARRY CI=$auto$alumacc.cc:474:replace_alu$16092.C[1] CO=$auto$alumacc.cc:474:replace_alu$16092.C[2] I0=common.pb.spirx_bytecount[1] I1=$abc$44715$auto$alumacc.cc:474:replace_alu$16092.BB[1]
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:661|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/arith_map.v:56"
.gate SB_CARRY CI=$auto$alumacc.cc:474:replace_alu$16092.C[2] CO=$auto$alumacc.cc:474:replace_alu$16092.C[3] I0=common.pb.spirx_bytecount[2] I1=$abc$44715$auto$alumacc.cc:474:replace_alu$16092.BB[2]
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:661|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/arith_map.v:56"
.gate SB_CARRY CI=$auto$alumacc.cc:474:replace_alu$16092.C[3] CO=$auto$alumacc.cc:474:replace_alu$16092.C[4] I0=common.pb.spirx_bytecount[3] I1=$abc$44715$auto$alumacc.cc:474:replace_alu$16092.BB[3]
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:661|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/arith_map.v:56"
.gate SB_CARRY CI=$auto$alumacc.cc:474:replace_alu$16092.C[4] CO=$auto$alumacc.cc:474:replace_alu$16092.C[5] I0=common.pb.spirx_bytecount[4] I1=$abc$44715$auto$alumacc.cc:474:replace_alu$16092.BB[4]
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:661|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/arith_map.v:56"
.gate SB_CARRY CI=$auto$alumacc.cc:474:replace_alu$16092.C[5] CO=$auto$alumacc.cc:474:replace_alu$16092.C[6] I0=common.pb.spirx_bytecount[5] I1=$abc$44715$auto$alumacc.cc:474:replace_alu$16092.BB[5]
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:661|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/arith_map.v:56"
.gate SB_CARRY CI=$auto$alumacc.cc:474:replace_alu$16092.C[6] CO=$auto$alumacc.cc:474:replace_alu$16092.C[7] I0=common.pb.spirx_bytecount[6] I1=$abc$44715$auto$alumacc.cc:474:replace_alu$16092.BB[6]
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:661|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/arith_map.v:56"
.gate SB_CARRY CI=$auto$alumacc.cc:474:replace_alu$16092.C[7] CO=$abc$44715$auto$alumacc.cc:491:replace_alu$16094[7] I0=common.pb.spirx_bytecount[7] I1=$abc$44715$auto$alumacc.cc:474:replace_alu$16092.BB[7]
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:661|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/arith_map.v:56"
.gate SB_CARRY CI=$true CO=$auto$alumacc.cc:474:replace_alu$16105.C[1] I0=common.pb.timer_idle_saved[0] I1=$abc$44715$auto$alumacc.cc:474:replace_alu$16105.BB[0]
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:483|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/arith_map.v:56"
.gate SB_CARRY CI=$auto$alumacc.cc:474:replace_alu$16105.C[10] CO=$auto$alumacc.cc:474:replace_alu$16105.C[11] I0=common.pb.timer_idle_saved[10] I1=$abc$44715$auto$alumacc.cc:474:replace_alu$16105.BB[10]
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:483|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/arith_map.v:56"
.gate SB_CARRY CI=$auto$alumacc.cc:474:replace_alu$16105.C[11] CO=$auto$alumacc.cc:474:replace_alu$16105.C[12] I0=common.pb.timer_idle_saved[11] I1=$abc$44715$auto$alumacc.cc:474:replace_alu$16105.BB[11]
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:483|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/arith_map.v:56"
.gate SB_CARRY CI=$auto$alumacc.cc:474:replace_alu$16105.C[12] CO=$auto$alumacc.cc:474:replace_alu$16105.C[13] I0=common.pb.timer_idle_saved[12] I1=$abc$44715$auto$alumacc.cc:474:replace_alu$16105.BB[12]
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:483|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/arith_map.v:56"
.gate SB_CARRY CI=$auto$alumacc.cc:474:replace_alu$16105.C[13] CO=$auto$alumacc.cc:474:replace_alu$16105.C[14] I0=common.pb.timer_idle_saved[13] I1=$abc$44715$auto$alumacc.cc:474:replace_alu$16105.BB[13]
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:483|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/arith_map.v:56"
.gate SB_CARRY CI=$auto$alumacc.cc:474:replace_alu$16105.C[14] CO=$auto$alumacc.cc:474:replace_alu$16105.C[15] I0=common.pb.timer_idle_saved[14] I1=$abc$44715$auto$alumacc.cc:474:replace_alu$16105.BB[14]
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:483|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/arith_map.v:56"
.gate SB_CARRY CI=$auto$alumacc.cc:474:replace_alu$16105.C[15] CO=$auto$alumacc.cc:474:replace_alu$16105.C[16] I0=common.pb.timer_idle_saved[15] I1=$abc$44715$auto$alumacc.cc:474:replace_alu$16105.BB[15]
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:483|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/arith_map.v:56"
.gate SB_CARRY CI=$auto$alumacc.cc:474:replace_alu$16105.C[16] CO=$auto$alumacc.cc:474:replace_alu$16105.C[17] I0=common.pb.timer_idle_saved[16] I1=$abc$44715$auto$alumacc.cc:474:replace_alu$16105.BB[16]
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:483|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/arith_map.v:56"
.gate SB_CARRY CI=$auto$alumacc.cc:474:replace_alu$16105.C[17] CO=$auto$alumacc.cc:474:replace_alu$16105.C[18] I0=common.pb.timer_idle_saved[17] I1=$abc$44715$auto$alumacc.cc:474:replace_alu$16105.BB[17]
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:483|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/arith_map.v:56"
.gate SB_CARRY CI=$auto$alumacc.cc:474:replace_alu$16105.C[18] CO=$auto$alumacc.cc:474:replace_alu$16105.C[19] I0=common.pb.timer_idle_saved[18] I1=$abc$44715$auto$alumacc.cc:474:replace_alu$16105.BB[18]
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:483|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/arith_map.v:56"
.gate SB_CARRY CI=$auto$alumacc.cc:474:replace_alu$16105.C[19] CO=$auto$alumacc.cc:474:replace_alu$16105.C[20] I0=common.pb.timer_idle_saved[19] I1=$abc$44715$auto$alumacc.cc:474:replace_alu$16105.BB[19]
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:483|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/arith_map.v:56"
.gate SB_CARRY CI=$auto$alumacc.cc:474:replace_alu$16105.C[1] CO=$auto$alumacc.cc:474:replace_alu$16105.C[2] I0=common.pb.timer_idle_saved[1] I1=$abc$44715$auto$alumacc.cc:474:replace_alu$16105.BB[1]
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:483|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/arith_map.v:56"
.gate SB_CARRY CI=$auto$alumacc.cc:474:replace_alu$16105.C[20] CO=$auto$alumacc.cc:474:replace_alu$16105.C[21] I0=common.pb.timer_idle_saved[20] I1=$abc$44715$auto$alumacc.cc:474:replace_alu$16105.BB[20]
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:483|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/arith_map.v:56"
.gate SB_CARRY CI=$auto$alumacc.cc:474:replace_alu$16105.C[21] CO=$auto$alumacc.cc:474:replace_alu$16105.C[22] I0=common.pb.timer_idle_saved[21] I1=$abc$44715$auto$alumacc.cc:474:replace_alu$16105.BB[21]
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:483|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/arith_map.v:56"
.gate SB_CARRY CI=$auto$alumacc.cc:474:replace_alu$16105.C[22] CO=$auto$alumacc.cc:474:replace_alu$16105.C[23] I0=common.pb.timer_idle_saved[22] I1=$abc$44715$auto$alumacc.cc:474:replace_alu$16105.BB[22]
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:483|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/arith_map.v:56"
.gate SB_CARRY CI=$auto$alumacc.cc:474:replace_alu$16105.C[23] CO=$abc$44715$auto$alumacc.cc:491:replace_alu$16107[23] I0=common.pb.timer_idle_saved[23] I1=$abc$44715$auto$alumacc.cc:474:replace_alu$16105.BB[23]
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:483|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/arith_map.v:56"
.gate SB_CARRY CI=$auto$alumacc.cc:474:replace_alu$16105.C[2] CO=$auto$alumacc.cc:474:replace_alu$16105.C[3] I0=common.pb.timer_idle_saved[2] I1=$abc$44715$auto$alumacc.cc:474:replace_alu$16105.BB[2]
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:483|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/arith_map.v:56"
.gate SB_CARRY CI=$auto$alumacc.cc:474:replace_alu$16105.C[3] CO=$auto$alumacc.cc:474:replace_alu$16105.C[4] I0=common.pb.timer_idle_saved[3] I1=$abc$44715$auto$alumacc.cc:474:replace_alu$16105.BB[3]
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:483|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/arith_map.v:56"
.gate SB_CARRY CI=$auto$alumacc.cc:474:replace_alu$16105.C[4] CO=$auto$alumacc.cc:474:replace_alu$16105.C[5] I0=common.pb.timer_idle_saved[4] I1=$abc$44715$auto$alumacc.cc:474:replace_alu$16105.BB[4]
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:483|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/arith_map.v:56"
.gate SB_CARRY CI=$auto$alumacc.cc:474:replace_alu$16105.C[5] CO=$auto$alumacc.cc:474:replace_alu$16105.C[6] I0=common.pb.timer_idle_saved[5] I1=$abc$44715$auto$alumacc.cc:474:replace_alu$16105.BB[5]
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:483|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/arith_map.v:56"
.gate SB_CARRY CI=$auto$alumacc.cc:474:replace_alu$16105.C[6] CO=$auto$alumacc.cc:474:replace_alu$16105.C[7] I0=common.pb.timer_idle_saved[6] I1=$abc$44715$auto$alumacc.cc:474:replace_alu$16105.BB[6]
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:483|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/arith_map.v:56"
.gate SB_CARRY CI=$auto$alumacc.cc:474:replace_alu$16105.C[7] CO=$auto$alumacc.cc:474:replace_alu$16105.C[8] I0=common.pb.timer_idle_saved[7] I1=$abc$44715$auto$alumacc.cc:474:replace_alu$16105.BB[7]
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:483|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/arith_map.v:56"
.gate SB_CARRY CI=$auto$alumacc.cc:474:replace_alu$16105.C[8] CO=$auto$alumacc.cc:474:replace_alu$16105.C[9] I0=common.pb.timer_idle_saved[8] I1=$abc$44715$auto$alumacc.cc:474:replace_alu$16105.BB[8]
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:483|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/arith_map.v:56"
.gate SB_CARRY CI=$auto$alumacc.cc:474:replace_alu$16105.C[9] CO=$auto$alumacc.cc:474:replace_alu$16105.C[10] I0=common.pb.timer_idle_saved[9] I1=$abc$44715$auto$alumacc.cc:474:replace_alu$16105.BB[9]
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:483|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/arith_map.v:56"
.gate SB_LUT4 I0=common.led_blink.led I1=common.led_blink.led_on_count[10] I2=$true I3=$auto$alumacc.cc:474:replace_alu$16118.C[10] O=$abc$44715$techmap\common.led_blink.$procmux$9274_Y[10]
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:109|led_blink_mod.v:51|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/arith_map.v:62|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:56"
.param LUT_INIT 1101011101111101
.gate SB_CARRY CI=$auto$alumacc.cc:474:replace_alu$16118.C[10] CO=$auto$alumacc.cc:474:replace_alu$16118.C[11] I0=common.led_blink.led_on_count[10] I1=$true
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:109|led_blink_mod.v:51|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/arith_map.v:56"
.gate SB_LUT4 I0=common.led_blink.led I1=common.led_blink.led_on_count[11] I2=$true I3=$auto$alumacc.cc:474:replace_alu$16118.C[11] O=$abc$44715$techmap\common.led_blink.$procmux$9274_Y[11]
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:109|led_blink_mod.v:51|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/arith_map.v:62|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:56"
.param LUT_INIT 1101011101111101
.gate SB_CARRY CI=$auto$alumacc.cc:474:replace_alu$16118.C[11] CO=$auto$alumacc.cc:474:replace_alu$16118.C[12] I0=common.led_blink.led_on_count[11] I1=$true
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:109|led_blink_mod.v:51|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/arith_map.v:56"
.gate SB_LUT4 I0=common.led_blink.led I1=common.led_blink.led_on_count[12] I2=$true I3=$auto$alumacc.cc:474:replace_alu$16118.C[12] O=$abc$44715$techmap\common.led_blink.$procmux$9274_Y[12]
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:109|led_blink_mod.v:51|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/arith_map.v:62|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:56"
.param LUT_INIT 1101011101111101
.gate SB_CARRY CI=$auto$alumacc.cc:474:replace_alu$16118.C[12] CO=$auto$alumacc.cc:474:replace_alu$16118.C[13] I0=common.led_blink.led_on_count[12] I1=$true
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:109|led_blink_mod.v:51|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/arith_map.v:56"
.gate SB_LUT4 I0=common.led_blink.led I1=common.led_blink.led_on_count[13] I2=$true I3=$auto$alumacc.cc:474:replace_alu$16118.C[13] O=$abc$44715$techmap\common.led_blink.$procmux$9274_Y[13]
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:109|led_blink_mod.v:51|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/arith_map.v:62|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:56"
.param LUT_INIT 1000001000101000
.gate SB_CARRY CI=$auto$alumacc.cc:474:replace_alu$16118.C[13] CO=$auto$alumacc.cc:474:replace_alu$16118.C[14] I0=common.led_blink.led_on_count[13] I1=$true
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:109|led_blink_mod.v:51|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/arith_map.v:56"
.gate SB_LUT4 I0=common.led_blink.led I1=common.led_blink.led_on_count[14] I2=$true I3=$auto$alumacc.cc:474:replace_alu$16118.C[14] O=$abc$44715$techmap\common.led_blink.$procmux$9274_Y[14]
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:109|led_blink_mod.v:51|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/arith_map.v:62|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:56"
.param LUT_INIT 1000001000101000
.gate SB_CARRY CI=$auto$alumacc.cc:474:replace_alu$16118.C[14] CO=$auto$alumacc.cc:474:replace_alu$16118.C[15] I0=common.led_blink.led_on_count[14] I1=$true
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:109|led_blink_mod.v:51|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/arith_map.v:56"
.gate SB_LUT4 I0=common.led_blink.led I1=common.led_blink.led_on_count[15] I2=$true I3=$auto$alumacc.cc:474:replace_alu$16118.C[15] O=$abc$44715$techmap\common.led_blink.$procmux$9274_Y[15]
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:109|led_blink_mod.v:51|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/arith_map.v:62|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:56"
.param LUT_INIT 1101011101111101
.gate SB_CARRY CI=$auto$alumacc.cc:474:replace_alu$16118.C[15] CO=$auto$alumacc.cc:474:replace_alu$16118.C[16] I0=common.led_blink.led_on_count[15] I1=$true
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:109|led_blink_mod.v:51|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/arith_map.v:56"
.gate SB_LUT4 I0=common.led_blink.led I1=common.led_blink.led_on_count[16] I2=$true I3=$auto$alumacc.cc:474:replace_alu$16118.C[16] O=$abc$44715$techmap\common.led_blink.$procmux$9274_Y[16]
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:109|led_blink_mod.v:51|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/arith_map.v:62|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:56"
.param LUT_INIT 1000001000101000
.gate SB_CARRY CI=$auto$alumacc.cc:474:replace_alu$16118.C[16] CO=$auto$alumacc.cc:474:replace_alu$16118.C[17] I0=common.led_blink.led_on_count[16] I1=$true
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:109|led_blink_mod.v:51|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/arith_map.v:56"
.gate SB_LUT4 I0=common.led_blink.led I1=common.led_blink.led_on_count[17] I2=$true I3=$auto$alumacc.cc:474:replace_alu$16118.C[17] O=$abc$44715$techmap\common.led_blink.$procmux$9274_Y[17]
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:109|led_blink_mod.v:51|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/arith_map.v:62|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:56"
.param LUT_INIT 1000001000101000
.gate SB_CARRY CI=$auto$alumacc.cc:474:replace_alu$16118.C[17] CO=$auto$alumacc.cc:474:replace_alu$16118.C[18] I0=common.led_blink.led_on_count[17] I1=$true
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:109|led_blink_mod.v:51|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/arith_map.v:56"
.gate SB_LUT4 I0=common.led_blink.led I1=common.led_blink.led_on_count[18] I2=$true I3=$auto$alumacc.cc:474:replace_alu$16118.C[18] O=$abc$44715$techmap\common.led_blink.$procmux$9274_Y[18]
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:109|led_blink_mod.v:51|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/arith_map.v:62|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:56"
.param LUT_INIT 1101011101111101
.gate SB_CARRY CI=$auto$alumacc.cc:474:replace_alu$16118.C[18] CO=$auto$alumacc.cc:474:replace_alu$16118.C[19] I0=common.led_blink.led_on_count[18] I1=$true
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:109|led_blink_mod.v:51|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/arith_map.v:56"
.gate SB_LUT4 I0=common.led_blink.led I1=common.led_blink.led_on_count[19] I2=$true I3=$auto$alumacc.cc:474:replace_alu$16118.C[19] O=$abc$44715$techmap\common.led_blink.$procmux$9274_Y[19]
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:109|led_blink_mod.v:51|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/arith_map.v:62|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:56"
.param LUT_INIT 1000001000101000
.gate SB_CARRY CI=$auto$alumacc.cc:474:replace_alu$16118.C[19] CO=$auto$alumacc.cc:474:replace_alu$16118.C[20] I0=common.led_blink.led_on_count[19] I1=$true
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:109|led_blink_mod.v:51|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/arith_map.v:56"
.gate SB_CARRY CI=common.led_blink.led_on_count[0] CO=$auto$alumacc.cc:474:replace_alu$16118.C[2] I0=common.led_blink.led_on_count[1] I1=$true
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:109|led_blink_mod.v:51|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/arith_map.v:56"
.gate SB_LUT4 I0=common.led_blink.led I1=common.led_blink.led_on_count[20] I2=$true I3=$auto$alumacc.cc:474:replace_alu$16118.C[20] O=$abc$44715$techmap\common.led_blink.$procmux$9274_Y[20]
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:109|led_blink_mod.v:51|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/arith_map.v:62|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:56"
.param LUT_INIT 1000001000101000
.gate SB_CARRY CI=$auto$alumacc.cc:474:replace_alu$16118.C[20] CO=$auto$alumacc.cc:474:replace_alu$16118.C[21] I0=common.led_blink.led_on_count[20] I1=$true
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:109|led_blink_mod.v:51|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/arith_map.v:56"
.gate SB_LUT4 I0=common.led_blink.led I1=common.led_blink.led_on_count[21] I2=$true I3=$auto$alumacc.cc:474:replace_alu$16118.C[21] O=$abc$44715$techmap\common.led_blink.$procmux$9274_Y[21]
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:109|led_blink_mod.v:51|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/arith_map.v:62|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:56"
.param LUT_INIT 1101011101111101
.gate SB_CARRY CI=$auto$alumacc.cc:474:replace_alu$16118.C[21] CO=$auto$alumacc.cc:474:replace_alu$16118.C[22] I0=common.led_blink.led_on_count[21] I1=$true
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:109|led_blink_mod.v:51|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/arith_map.v:56"
.gate SB_LUT4 I0=common.led_blink.led I1=common.led_blink.led_on_count[22] I2=$true I3=$auto$alumacc.cc:474:replace_alu$16118.C[22] O=$abc$44715$techmap\common.led_blink.$procmux$9274_Y[22]
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:109|led_blink_mod.v:51|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/arith_map.v:62|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:56"
.param LUT_INIT 1000001000101000
.gate SB_CARRY CI=$auto$alumacc.cc:474:replace_alu$16118.C[22] CO=$auto$alumacc.cc:474:replace_alu$16118.C[23] I0=common.led_blink.led_on_count[22] I1=$true
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:109|led_blink_mod.v:51|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/arith_map.v:56"
.gate SB_LUT4 I0=common.led_blink.led I1=common.led_blink.led_on_count[23] I2=$true I3=$auto$alumacc.cc:474:replace_alu$16118.C[23] O=$abc$44715$techmap\common.led_blink.$procmux$9274_Y[23]
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:109|led_blink_mod.v:51|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/arith_map.v:62|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:56"
.param LUT_INIT 1000001000101000
.gate SB_CARRY CI=$auto$alumacc.cc:474:replace_alu$16118.C[23] CO=$auto$alumacc.cc:474:replace_alu$16118.C[24] I0=common.led_blink.led_on_count[23] I1=$true
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:109|led_blink_mod.v:51|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/arith_map.v:56"
.gate SB_LUT4 I0=common.led_blink.led I1=common.led_blink.led_on_count[24] I2=$true I3=$auto$alumacc.cc:474:replace_alu$16118.C[24] O=$abc$44715$techmap\common.led_blink.$procmux$9274_Y[24]
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:109|led_blink_mod.v:51|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/arith_map.v:62|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:56"
.param LUT_INIT 1000001000101000
.gate SB_CARRY CI=$auto$alumacc.cc:474:replace_alu$16118.C[24] CO=$auto$alumacc.cc:474:replace_alu$16118.C[25] I0=common.led_blink.led_on_count[24] I1=$true
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:109|led_blink_mod.v:51|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/arith_map.v:56"
.gate SB_LUT4 I0=common.led_blink.led I1=common.led_blink.led_on_count[25] I2=$true I3=$auto$alumacc.cc:474:replace_alu$16118.C[25] O=$abc$44715$techmap\common.led_blink.$procmux$9274_Y[25]
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:109|led_blink_mod.v:51|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/arith_map.v:62|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:56"
.param LUT_INIT 1000001000101000
.gate SB_CARRY CI=$auto$alumacc.cc:474:replace_alu$16118.C[25] CO=$auto$alumacc.cc:474:replace_alu$16118.C[26] I0=common.led_blink.led_on_count[25] I1=$true
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:109|led_blink_mod.v:51|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/arith_map.v:56"
.gate SB_LUT4 I0=common.led_blink.led I1=common.led_blink.led_on_count[26] I2=$true I3=$auto$alumacc.cc:474:replace_alu$16118.C[26] O=$abc$44715$techmap\common.led_blink.$procmux$9274_Y[26]
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:109|led_blink_mod.v:51|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/arith_map.v:62|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:56"
.param LUT_INIT 1000001000101000
.gate SB_CARRY CI=$auto$alumacc.cc:474:replace_alu$16118.C[26] CO=$auto$alumacc.cc:474:replace_alu$16118.C[27] I0=common.led_blink.led_on_count[26] I1=$true
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:109|led_blink_mod.v:51|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/arith_map.v:56"
.gate SB_LUT4 I0=common.led_blink.led I1=common.led_blink.led_on_count[27] I2=$true I3=$auto$alumacc.cc:474:replace_alu$16118.C[27] O=$abc$44715$techmap\common.led_blink.$procmux$9274_Y[27]
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:109|led_blink_mod.v:51|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/arith_map.v:62|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:56"
.param LUT_INIT 1000001000101000
.gate SB_CARRY CI=$auto$alumacc.cc:474:replace_alu$16118.C[27] CO=$auto$alumacc.cc:474:replace_alu$16118.C[28] I0=common.led_blink.led_on_count[27] I1=$true
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:109|led_blink_mod.v:51|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/arith_map.v:56"
.gate SB_LUT4 I0=common.led_blink.led I1=common.led_blink.led_on_count[28] I2=$true I3=$auto$alumacc.cc:474:replace_alu$16118.C[28] O=$abc$44715$techmap\common.led_blink.$procmux$9274_Y[28]
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:109|led_blink_mod.v:51|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/arith_map.v:62|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:56"
.param LUT_INIT 1000001000101000
.gate SB_CARRY CI=$auto$alumacc.cc:474:replace_alu$16118.C[28] CO=$auto$alumacc.cc:474:replace_alu$16118.C[29] I0=common.led_blink.led_on_count[28] I1=$true
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:109|led_blink_mod.v:51|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/arith_map.v:56"
.gate SB_LUT4 I0=common.led_blink.led I1=common.led_blink.led_on_count[29] I2=$true I3=$auto$alumacc.cc:474:replace_alu$16118.C[29] O=$abc$44715$techmap\common.led_blink.$procmux$9274_Y[29]
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:109|led_blink_mod.v:51|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/arith_map.v:62|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:56"
.param LUT_INIT 1000001000101000
.gate SB_CARRY CI=$auto$alumacc.cc:474:replace_alu$16118.C[29] CO=$auto$alumacc.cc:474:replace_alu$16118.C[30] I0=common.led_blink.led_on_count[29] I1=$true
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:109|led_blink_mod.v:51|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/arith_map.v:56"
.gate SB_LUT4 I0=common.led_blink.led I1=common.led_blink.led_on_count[2] I2=$true I3=$auto$alumacc.cc:474:replace_alu$16118.C[2] O=$abc$44715$techmap\common.led_blink.$procmux$9274_Y[2]
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:109|led_blink_mod.v:51|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/arith_map.v:62|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:56"
.param LUT_INIT 1000001000101000
.gate SB_CARRY CI=$auto$alumacc.cc:474:replace_alu$16118.C[2] CO=$auto$alumacc.cc:474:replace_alu$16118.C[3] I0=common.led_blink.led_on_count[2] I1=$true
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:109|led_blink_mod.v:51|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/arith_map.v:56"
.gate SB_LUT4 I0=common.led_blink.led I1=common.led_blink.led_on_count[30] I2=$true I3=$auto$alumacc.cc:474:replace_alu$16118.C[30] O=$abc$44715$techmap\common.led_blink.$procmux$9274_Y[30]
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:109|led_blink_mod.v:51|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/arith_map.v:62|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:56"
.param LUT_INIT 1000001000101000
.gate SB_CARRY CI=$auto$alumacc.cc:474:replace_alu$16118.C[30] CO=$auto$alumacc.cc:474:replace_alu$16118.C[31] I0=common.led_blink.led_on_count[30] I1=$true
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:109|led_blink_mod.v:51|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/arith_map.v:56"
.gate SB_LUT4 I0=$false I1=common.led_blink.led_on_count[31] I2=common.led_blink.led I3=$auto$alumacc.cc:474:replace_alu$16118.C[31] O=$abc$44715$techmap\common.led_blink.$procmux$9274_Y[31]
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:109|led_blink_mod.v:51|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/arith_map.v:62|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:56"
.param LUT_INIT 0110000010010000
.gate SB_LUT4 I0=common.led_blink.led I1=common.led_blink.led_on_count[3] I2=$true I3=$auto$alumacc.cc:474:replace_alu$16118.C[3] O=$abc$44715$techmap\common.led_blink.$procmux$9274_Y[3]
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:109|led_blink_mod.v:51|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/arith_map.v:62|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:56"
.param LUT_INIT 1000001000101000
.gate SB_CARRY CI=$auto$alumacc.cc:474:replace_alu$16118.C[3] CO=$auto$alumacc.cc:474:replace_alu$16118.C[4] I0=common.led_blink.led_on_count[3] I1=$true
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:109|led_blink_mod.v:51|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/arith_map.v:56"
.gate SB_LUT4 I0=common.led_blink.led I1=common.led_blink.led_on_count[4] I2=$true I3=$auto$alumacc.cc:474:replace_alu$16118.C[4] O=$abc$44715$techmap\common.led_blink.$procmux$9274_Y[4]
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:109|led_blink_mod.v:51|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/arith_map.v:62|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:56"
.param LUT_INIT 1000001000101000
.gate SB_CARRY CI=$auto$alumacc.cc:474:replace_alu$16118.C[4] CO=$auto$alumacc.cc:474:replace_alu$16118.C[5] I0=common.led_blink.led_on_count[4] I1=$true
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:109|led_blink_mod.v:51|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/arith_map.v:56"
.gate SB_LUT4 I0=common.led_blink.led I1=common.led_blink.led_on_count[5] I2=$true I3=$auto$alumacc.cc:474:replace_alu$16118.C[5] O=$abc$44715$techmap\common.led_blink.$procmux$9274_Y[5]
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:109|led_blink_mod.v:51|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/arith_map.v:62|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:56"
.param LUT_INIT 1000001000101000
.gate SB_CARRY CI=$auto$alumacc.cc:474:replace_alu$16118.C[5] CO=$auto$alumacc.cc:474:replace_alu$16118.C[6] I0=common.led_blink.led_on_count[5] I1=$true
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:109|led_blink_mod.v:51|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/arith_map.v:56"
.gate SB_LUT4 I0=common.led_blink.led I1=common.led_blink.led_on_count[6] I2=$true I3=$auto$alumacc.cc:474:replace_alu$16118.C[6] O=$abc$44715$techmap\common.led_blink.$procmux$9274_Y[6]
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:109|led_blink_mod.v:51|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/arith_map.v:62|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:56"
.param LUT_INIT 1000001000101000
.gate SB_CARRY CI=$auto$alumacc.cc:474:replace_alu$16118.C[6] CO=$auto$alumacc.cc:474:replace_alu$16118.C[7] I0=common.led_blink.led_on_count[6] I1=$true
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:109|led_blink_mod.v:51|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/arith_map.v:56"
.gate SB_LUT4 I0=common.led_blink.led I1=common.led_blink.led_on_count[7] I2=$true I3=$auto$alumacc.cc:474:replace_alu$16118.C[7] O=$abc$44715$techmap\common.led_blink.$procmux$9274_Y[7]
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:109|led_blink_mod.v:51|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/arith_map.v:62|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:56"
.param LUT_INIT 1000001000101000
.gate SB_CARRY CI=$auto$alumacc.cc:474:replace_alu$16118.C[7] CO=$auto$alumacc.cc:474:replace_alu$16118.C[8] I0=common.led_blink.led_on_count[7] I1=$true
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:109|led_blink_mod.v:51|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/arith_map.v:56"
.gate SB_LUT4 I0=common.led_blink.led I1=common.led_blink.led_on_count[8] I2=$true I3=$auto$alumacc.cc:474:replace_alu$16118.C[8] O=$abc$44715$techmap\common.led_blink.$procmux$9274_Y[8]
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:109|led_blink_mod.v:51|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/arith_map.v:62|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:56"
.param LUT_INIT 1101011101111101
.gate SB_CARRY CI=$auto$alumacc.cc:474:replace_alu$16118.C[8] CO=$auto$alumacc.cc:474:replace_alu$16118.C[9] I0=common.led_blink.led_on_count[8] I1=$true
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:109|led_blink_mod.v:51|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/arith_map.v:56"
.gate SB_LUT4 I0=common.led_blink.led I1=common.led_blink.led_on_count[9] I2=$true I3=$auto$alumacc.cc:474:replace_alu$16118.C[9] O=$abc$44715$techmap\common.led_blink.$procmux$9274_Y[9]
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:109|led_blink_mod.v:51|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/arith_map.v:62|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:56"
.param LUT_INIT 1101011101111101
.gate SB_CARRY CI=$auto$alumacc.cc:474:replace_alu$16118.C[9] CO=$auto$alumacc.cc:474:replace_alu$16118.C[10] I0=common.led_blink.led_on_count[9] I1=$true
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:109|led_blink_mod.v:51|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/arith_map.v:56"
.gate SB_LUT4 I0=common.led_blink.led I1=common.led_blink.led_off_count[10] I2=$true I3=$auto$alumacc.cc:474:replace_alu$16121.C[10] O=$abc$44715$techmap\common.led_blink.$procmux$9260_Y[10]
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:109|led_blink_mod.v:60|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/arith_map.v:62|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:56"
.param LUT_INIT 1110101110111110
.gate SB_CARRY CI=$auto$alumacc.cc:474:replace_alu$16121.C[10] CO=$auto$alumacc.cc:474:replace_alu$16121.C[11] I0=common.led_blink.led_off_count[10] I1=$true
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:109|led_blink_mod.v:60|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/arith_map.v:56"
.gate SB_LUT4 I0=common.led_blink.led I1=common.led_blink.led_off_count[11] I2=$true I3=$auto$alumacc.cc:474:replace_alu$16121.C[11] O=$abc$44715$techmap\common.led_blink.$procmux$9260_Y[11]
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:109|led_blink_mod.v:60|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/arith_map.v:62|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:56"
.param LUT_INIT 0100000100010100
.gate SB_CARRY CI=$auto$alumacc.cc:474:replace_alu$16121.C[11] CO=$auto$alumacc.cc:474:replace_alu$16121.C[12] I0=common.led_blink.led_off_count[11] I1=$true
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:109|led_blink_mod.v:60|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/arith_map.v:56"
.gate SB_LUT4 I0=common.led_blink.led I1=common.led_blink.led_off_count[12] I2=$true I3=$auto$alumacc.cc:474:replace_alu$16121.C[12] O=$abc$44715$techmap\common.led_blink.$procmux$9260_Y[12]
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:109|led_blink_mod.v:60|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/arith_map.v:62|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:56"
.param LUT_INIT 1110101110111110
.gate SB_CARRY CI=$auto$alumacc.cc:474:replace_alu$16121.C[12] CO=$auto$alumacc.cc:474:replace_alu$16121.C[13] I0=common.led_blink.led_off_count[12] I1=$true
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:109|led_blink_mod.v:60|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/arith_map.v:56"
.gate SB_LUT4 I0=common.led_blink.led I1=common.led_blink.led_off_count[13] I2=$true I3=$auto$alumacc.cc:474:replace_alu$16121.C[13] O=$abc$44715$techmap\common.led_blink.$procmux$9260_Y[13]
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:109|led_blink_mod.v:60|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/arith_map.v:62|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:56"
.param LUT_INIT 1110101110111110
.gate SB_CARRY CI=$auto$alumacc.cc:474:replace_alu$16121.C[13] CO=$auto$alumacc.cc:474:replace_alu$16121.C[14] I0=common.led_blink.led_off_count[13] I1=$true
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:109|led_blink_mod.v:60|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/arith_map.v:56"
.gate SB_LUT4 I0=common.led_blink.led I1=common.led_blink.led_off_count[14] I2=$true I3=$auto$alumacc.cc:474:replace_alu$16121.C[14] O=$abc$44715$techmap\common.led_blink.$procmux$9260_Y[14]
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:109|led_blink_mod.v:60|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/arith_map.v:62|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:56"
.param LUT_INIT 1110101110111110
.gate SB_CARRY CI=$auto$alumacc.cc:474:replace_alu$16121.C[14] CO=$auto$alumacc.cc:474:replace_alu$16121.C[15] I0=common.led_blink.led_off_count[14] I1=$true
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:109|led_blink_mod.v:60|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/arith_map.v:56"
.gate SB_LUT4 I0=common.led_blink.led I1=common.led_blink.led_off_count[15] I2=$true I3=$auto$alumacc.cc:474:replace_alu$16121.C[15] O=$abc$44715$techmap\common.led_blink.$procmux$9260_Y[15]
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:109|led_blink_mod.v:60|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/arith_map.v:62|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:56"
.param LUT_INIT 0100000100010100
.gate SB_CARRY CI=$auto$alumacc.cc:474:replace_alu$16121.C[15] CO=$auto$alumacc.cc:474:replace_alu$16121.C[16] I0=common.led_blink.led_off_count[15] I1=$true
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:109|led_blink_mod.v:60|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/arith_map.v:56"
.gate SB_LUT4 I0=common.led_blink.led I1=common.led_blink.led_off_count[16] I2=$true I3=$auto$alumacc.cc:474:replace_alu$16121.C[16] O=$abc$44715$techmap\common.led_blink.$procmux$9260_Y[16]
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:109|led_blink_mod.v:60|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/arith_map.v:62|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:56"
.param LUT_INIT 0100000100010100
.gate SB_CARRY CI=$auto$alumacc.cc:474:replace_alu$16121.C[16] CO=$auto$alumacc.cc:474:replace_alu$16121.C[17] I0=common.led_blink.led_off_count[16] I1=$true
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:109|led_blink_mod.v:60|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/arith_map.v:56"
.gate SB_LUT4 I0=common.led_blink.led I1=common.led_blink.led_off_count[17] I2=$true I3=$auto$alumacc.cc:474:replace_alu$16121.C[17] O=$abc$44715$techmap\common.led_blink.$procmux$9260_Y[17]
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:109|led_blink_mod.v:60|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/arith_map.v:62|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:56"
.param LUT_INIT 1110101110111110
.gate SB_CARRY CI=$auto$alumacc.cc:474:replace_alu$16121.C[17] CO=$auto$alumacc.cc:474:replace_alu$16121.C[18] I0=common.led_blink.led_off_count[17] I1=$true
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:109|led_blink_mod.v:60|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/arith_map.v:56"
.gate SB_LUT4 I0=common.led_blink.led I1=common.led_blink.led_off_count[18] I2=$true I3=$auto$alumacc.cc:474:replace_alu$16121.C[18] O=$abc$44715$techmap\common.led_blink.$procmux$9260_Y[18]
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:109|led_blink_mod.v:60|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/arith_map.v:62|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:56"
.param LUT_INIT 0100000100010100
.gate SB_CARRY CI=$auto$alumacc.cc:474:replace_alu$16121.C[18] CO=$auto$alumacc.cc:474:replace_alu$16121.C[19] I0=common.led_blink.led_off_count[18] I1=$true
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:109|led_blink_mod.v:60|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/arith_map.v:56"
.gate SB_LUT4 I0=common.led_blink.led I1=common.led_blink.led_off_count[19] I2=$true I3=$auto$alumacc.cc:474:replace_alu$16121.C[19] O=$abc$44715$techmap\common.led_blink.$procmux$9260_Y[19]
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:109|led_blink_mod.v:60|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/arith_map.v:62|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:56"
.param LUT_INIT 1110101110111110
.gate SB_CARRY CI=$auto$alumacc.cc:474:replace_alu$16121.C[19] CO=$auto$alumacc.cc:474:replace_alu$16121.C[20] I0=common.led_blink.led_off_count[19] I1=$true
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:109|led_blink_mod.v:60|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/arith_map.v:56"
.gate SB_CARRY CI=common.led_blink.led_off_count[0] CO=$auto$alumacc.cc:474:replace_alu$16121.C[2] I0=common.led_blink.led_off_count[1] I1=$true
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:109|led_blink_mod.v:60|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/arith_map.v:56"
.gate SB_LUT4 I0=common.led_blink.led I1=common.led_blink.led_off_count[20] I2=$true I3=$auto$alumacc.cc:474:replace_alu$16121.C[20] O=$abc$44715$techmap\common.led_blink.$procmux$9260_Y[20]
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:109|led_blink_mod.v:60|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/arith_map.v:62|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:56"
.param LUT_INIT 0100000100010100
.gate SB_CARRY CI=$auto$alumacc.cc:474:replace_alu$16121.C[20] CO=$auto$alumacc.cc:474:replace_alu$16121.C[21] I0=common.led_blink.led_off_count[20] I1=$true
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:109|led_blink_mod.v:60|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/arith_map.v:56"
.gate SB_LUT4 I0=common.led_blink.led I1=common.led_blink.led_off_count[21] I2=$true I3=$auto$alumacc.cc:474:replace_alu$16121.C[21] O=$abc$44715$techmap\common.led_blink.$procmux$9260_Y[21]
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:109|led_blink_mod.v:60|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/arith_map.v:62|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:56"
.param LUT_INIT 0100000100010100
.gate SB_CARRY CI=$auto$alumacc.cc:474:replace_alu$16121.C[21] CO=$auto$alumacc.cc:474:replace_alu$16121.C[22] I0=common.led_blink.led_off_count[21] I1=$true
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:109|led_blink_mod.v:60|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/arith_map.v:56"
.gate SB_LUT4 I0=common.led_blink.led I1=common.led_blink.led_off_count[22] I2=$true I3=$auto$alumacc.cc:474:replace_alu$16121.C[22] O=$abc$44715$techmap\common.led_blink.$procmux$9260_Y[22]
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:109|led_blink_mod.v:60|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/arith_map.v:62|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:56"
.param LUT_INIT 0100000100010100
.gate SB_CARRY CI=$auto$alumacc.cc:474:replace_alu$16121.C[22] CO=$auto$alumacc.cc:474:replace_alu$16121.C[23] I0=common.led_blink.led_off_count[22] I1=$true
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:109|led_blink_mod.v:60|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/arith_map.v:56"
.gate SB_LUT4 I0=common.led_blink.led I1=common.led_blink.led_off_count[23] I2=$true I3=$auto$alumacc.cc:474:replace_alu$16121.C[23] O=$abc$44715$techmap\common.led_blink.$procmux$9260_Y[23]
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:109|led_blink_mod.v:60|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/arith_map.v:62|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:56"
.param LUT_INIT 0100000100010100
.gate SB_CARRY CI=$auto$alumacc.cc:474:replace_alu$16121.C[23] CO=$auto$alumacc.cc:474:replace_alu$16121.C[24] I0=common.led_blink.led_off_count[23] I1=$true
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:109|led_blink_mod.v:60|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/arith_map.v:56"
.gate SB_LUT4 I0=common.led_blink.led I1=common.led_blink.led_off_count[24] I2=$true I3=$auto$alumacc.cc:474:replace_alu$16121.C[24] O=$abc$44715$techmap\common.led_blink.$procmux$9260_Y[24]
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:109|led_blink_mod.v:60|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/arith_map.v:62|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:56"
.param LUT_INIT 0100000100010100
.gate SB_CARRY CI=$auto$alumacc.cc:474:replace_alu$16121.C[24] CO=$auto$alumacc.cc:474:replace_alu$16121.C[25] I0=common.led_blink.led_off_count[24] I1=$true
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:109|led_blink_mod.v:60|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/arith_map.v:56"
.gate SB_LUT4 I0=common.led_blink.led I1=common.led_blink.led_off_count[25] I2=$true I3=$auto$alumacc.cc:474:replace_alu$16121.C[25] O=$abc$44715$techmap\common.led_blink.$procmux$9260_Y[25]
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:109|led_blink_mod.v:60|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/arith_map.v:62|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:56"
.param LUT_INIT 0100000100010100
.gate SB_CARRY CI=$auto$alumacc.cc:474:replace_alu$16121.C[25] CO=$auto$alumacc.cc:474:replace_alu$16121.C[26] I0=common.led_blink.led_off_count[25] I1=$true
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:109|led_blink_mod.v:60|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/arith_map.v:56"
.gate SB_LUT4 I0=common.led_blink.led I1=common.led_blink.led_off_count[26] I2=$true I3=$auto$alumacc.cc:474:replace_alu$16121.C[26] O=$abc$44715$techmap\common.led_blink.$procmux$9260_Y[26]
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:109|led_blink_mod.v:60|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/arith_map.v:62|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:56"
.param LUT_INIT 0100000100010100
.gate SB_CARRY CI=$auto$alumacc.cc:474:replace_alu$16121.C[26] CO=$auto$alumacc.cc:474:replace_alu$16121.C[27] I0=common.led_blink.led_off_count[26] I1=$true
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:109|led_blink_mod.v:60|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/arith_map.v:56"
.gate SB_LUT4 I0=common.led_blink.led I1=common.led_blink.led_off_count[27] I2=$true I3=$auto$alumacc.cc:474:replace_alu$16121.C[27] O=$abc$44715$techmap\common.led_blink.$procmux$9260_Y[27]
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:109|led_blink_mod.v:60|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/arith_map.v:62|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:56"
.param LUT_INIT 0100000100010100
.gate SB_CARRY CI=$auto$alumacc.cc:474:replace_alu$16121.C[27] CO=$auto$alumacc.cc:474:replace_alu$16121.C[28] I0=common.led_blink.led_off_count[27] I1=$true
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:109|led_blink_mod.v:60|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/arith_map.v:56"
.gate SB_LUT4 I0=common.led_blink.led I1=common.led_blink.led_off_count[28] I2=$true I3=$auto$alumacc.cc:474:replace_alu$16121.C[28] O=$abc$44715$techmap\common.led_blink.$procmux$9260_Y[28]
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:109|led_blink_mod.v:60|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/arith_map.v:62|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:56"
.param LUT_INIT 0100000100010100
.gate SB_CARRY CI=$auto$alumacc.cc:474:replace_alu$16121.C[28] CO=$auto$alumacc.cc:474:replace_alu$16121.C[29] I0=common.led_blink.led_off_count[28] I1=$true
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:109|led_blink_mod.v:60|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/arith_map.v:56"
.gate SB_LUT4 I0=common.led_blink.led I1=common.led_blink.led_off_count[29] I2=$true I3=$auto$alumacc.cc:474:replace_alu$16121.C[29] O=$abc$44715$techmap\common.led_blink.$procmux$9260_Y[29]
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:109|led_blink_mod.v:60|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/arith_map.v:62|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:56"
.param LUT_INIT 0100000100010100
.gate SB_CARRY CI=$auto$alumacc.cc:474:replace_alu$16121.C[29] CO=$auto$alumacc.cc:474:replace_alu$16121.C[30] I0=common.led_blink.led_off_count[29] I1=$true
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:109|led_blink_mod.v:60|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/arith_map.v:56"
.gate SB_LUT4 I0=common.led_blink.led I1=common.led_blink.led_off_count[2] I2=$true I3=$auto$alumacc.cc:474:replace_alu$16121.C[2] O=$abc$44715$techmap\common.led_blink.$procmux$9260_Y[2]
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:109|led_blink_mod.v:60|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/arith_map.v:62|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:56"
.param LUT_INIT 0100000100010100
.gate SB_CARRY CI=$auto$alumacc.cc:474:replace_alu$16121.C[2] CO=$auto$alumacc.cc:474:replace_alu$16121.C[3] I0=common.led_blink.led_off_count[2] I1=$true
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:109|led_blink_mod.v:60|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/arith_map.v:56"
.gate SB_LUT4 I0=common.led_blink.led I1=common.led_blink.led_off_count[30] I2=$true I3=$auto$alumacc.cc:474:replace_alu$16121.C[30] O=$abc$44715$techmap\common.led_blink.$procmux$9260_Y[30]
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:109|led_blink_mod.v:60|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/arith_map.v:62|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:56"
.param LUT_INIT 0100000100010100
.gate SB_CARRY CI=$auto$alumacc.cc:474:replace_alu$16121.C[30] CO=$auto$alumacc.cc:474:replace_alu$16121.C[31] I0=common.led_blink.led_off_count[30] I1=$true
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:109|led_blink_mod.v:60|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/arith_map.v:56"
.gate SB_LUT4 I0=$false I1=common.led_blink.led_off_count[31] I2=common.led_blink.led I3=$auto$alumacc.cc:474:replace_alu$16121.C[31] O=$abc$44715$techmap\common.led_blink.$procmux$9260_Y[31]
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:109|led_blink_mod.v:60|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/arith_map.v:62|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:56"
.param LUT_INIT 0000011000001001
.gate SB_LUT4 I0=common.led_blink.led I1=common.led_blink.led_off_count[3] I2=$true I3=$auto$alumacc.cc:474:replace_alu$16121.C[3] O=$abc$44715$techmap\common.led_blink.$procmux$9260_Y[3]
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:109|led_blink_mod.v:60|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/arith_map.v:62|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:56"
.param LUT_INIT 0100000100010100
.gate SB_CARRY CI=$auto$alumacc.cc:474:replace_alu$16121.C[3] CO=$auto$alumacc.cc:474:replace_alu$16121.C[4] I0=common.led_blink.led_off_count[3] I1=$true
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:109|led_blink_mod.v:60|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/arith_map.v:56"
.gate SB_LUT4 I0=common.led_blink.led I1=common.led_blink.led_off_count[4] I2=$true I3=$auto$alumacc.cc:474:replace_alu$16121.C[4] O=$abc$44715$techmap\common.led_blink.$procmux$9260_Y[4]
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:109|led_blink_mod.v:60|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/arith_map.v:62|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:56"
.param LUT_INIT 1110101110111110
.gate SB_CARRY CI=$auto$alumacc.cc:474:replace_alu$16121.C[4] CO=$auto$alumacc.cc:474:replace_alu$16121.C[5] I0=common.led_blink.led_off_count[4] I1=$true
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:109|led_blink_mod.v:60|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/arith_map.v:56"
.gate SB_LUT4 I0=common.led_blink.led I1=common.led_blink.led_off_count[5] I2=$true I3=$auto$alumacc.cc:474:replace_alu$16121.C[5] O=$abc$44715$techmap\common.led_blink.$procmux$9260_Y[5]
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:109|led_blink_mod.v:60|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/arith_map.v:62|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:56"
.param LUT_INIT 0100000100010100
.gate SB_CARRY CI=$auto$alumacc.cc:474:replace_alu$16121.C[5] CO=$auto$alumacc.cc:474:replace_alu$16121.C[6] I0=common.led_blink.led_off_count[5] I1=$true
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:109|led_blink_mod.v:60|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/arith_map.v:56"
.gate SB_LUT4 I0=common.led_blink.led I1=common.led_blink.led_off_count[6] I2=$true I3=$auto$alumacc.cc:474:replace_alu$16121.C[6] O=$abc$44715$techmap\common.led_blink.$procmux$9260_Y[6]
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:109|led_blink_mod.v:60|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/arith_map.v:62|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:56"
.param LUT_INIT 0100000100010100
.gate SB_CARRY CI=$auto$alumacc.cc:474:replace_alu$16121.C[6] CO=$auto$alumacc.cc:474:replace_alu$16121.C[7] I0=common.led_blink.led_off_count[6] I1=$true
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:109|led_blink_mod.v:60|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/arith_map.v:56"
.gate SB_LUT4 I0=common.led_blink.led I1=common.led_blink.led_off_count[7] I2=$true I3=$auto$alumacc.cc:474:replace_alu$16121.C[7] O=$abc$44715$techmap\common.led_blink.$procmux$9260_Y[7]
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:109|led_blink_mod.v:60|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/arith_map.v:62|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:56"
.param LUT_INIT 1110101110111110
.gate SB_CARRY CI=$auto$alumacc.cc:474:replace_alu$16121.C[7] CO=$auto$alumacc.cc:474:replace_alu$16121.C[8] I0=common.led_blink.led_off_count[7] I1=$true
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:109|led_blink_mod.v:60|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/arith_map.v:56"
.gate SB_LUT4 I0=common.led_blink.led I1=common.led_blink.led_off_count[8] I2=$true I3=$auto$alumacc.cc:474:replace_alu$16121.C[8] O=$abc$44715$techmap\common.led_blink.$procmux$9260_Y[8]
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:109|led_blink_mod.v:60|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/arith_map.v:62|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:56"
.param LUT_INIT 0100000100010100
.gate SB_CARRY CI=$auto$alumacc.cc:474:replace_alu$16121.C[8] CO=$auto$alumacc.cc:474:replace_alu$16121.C[9] I0=common.led_blink.led_off_count[8] I1=$true
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:109|led_blink_mod.v:60|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/arith_map.v:56"
.gate SB_LUT4 I0=common.led_blink.led I1=common.led_blink.led_off_count[9] I2=$true I3=$auto$alumacc.cc:474:replace_alu$16121.C[9] O=$abc$44715$techmap\common.led_blink.$procmux$9260_Y[9]
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:109|led_blink_mod.v:60|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/arith_map.v:62|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:56"
.param LUT_INIT 1110101110111110
.gate SB_CARRY CI=$auto$alumacc.cc:474:replace_alu$16121.C[9] CO=$auto$alumacc.cc:474:replace_alu$16121.C[10] I0=common.led_blink.led_off_count[9] I1=$true
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:109|led_blink_mod.v:60|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/arith_map.v:56"
.gate SB_LUT4 I0=$abc$44715$techmap\common.pb.$procmux$9294_Y I1=$false I2=common.pb.timer_idle[10] I3=$auto$alumacc.cc:474:replace_alu$16124.C[10] O=$abc$44715$techmap\common.pb.$procmux$9310_Y[10]
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:1059|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/arith_map.v:62|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:56"
.param LUT_INIT 0000101010100000
.gate SB_CARRY CI=$auto$alumacc.cc:474:replace_alu$16124.C[10] CO=$auto$alumacc.cc:474:replace_alu$16124.C[11] I0=$false I1=common.pb.timer_idle[10]
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:1059|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/arith_map.v:56"
.gate SB_LUT4 I0=$abc$44715$techmap\common.pb.$procmux$9294_Y I1=$false I2=common.pb.timer_idle[11] I3=$auto$alumacc.cc:474:replace_alu$16124.C[11] O=$abc$44715$techmap\common.pb.$procmux$9310_Y[11]
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:1059|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/arith_map.v:62|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:56"
.param LUT_INIT 0000101010100000
.gate SB_CARRY CI=$auto$alumacc.cc:474:replace_alu$16124.C[11] CO=$auto$alumacc.cc:474:replace_alu$16124.C[12] I0=$false I1=common.pb.timer_idle[11]
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:1059|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/arith_map.v:56"
.gate SB_LUT4 I0=$abc$44715$techmap\common.pb.$procmux$9294_Y I1=$false I2=common.pb.timer_idle[12] I3=$auto$alumacc.cc:474:replace_alu$16124.C[12] O=$abc$44715$techmap\common.pb.$procmux$9310_Y[12]
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:1059|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/arith_map.v:62|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:56"
.param LUT_INIT 0000101010100000
.gate SB_CARRY CI=$auto$alumacc.cc:474:replace_alu$16124.C[12] CO=$auto$alumacc.cc:474:replace_alu$16124.C[13] I0=$false I1=common.pb.timer_idle[12]
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:1059|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/arith_map.v:56"
.gate SB_LUT4 I0=$abc$44715$techmap\common.pb.$procmux$9294_Y I1=$false I2=common.pb.timer_idle[13] I3=$auto$alumacc.cc:474:replace_alu$16124.C[13] O=$abc$44715$techmap\common.pb.$procmux$9310_Y[13]
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:1059|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/arith_map.v:62|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:56"
.param LUT_INIT 0000101010100000
.gate SB_CARRY CI=$auto$alumacc.cc:474:replace_alu$16124.C[13] CO=$auto$alumacc.cc:474:replace_alu$16124.C[14] I0=$false I1=common.pb.timer_idle[13]
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:1059|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/arith_map.v:56"
.gate SB_LUT4 I0=$abc$44715$techmap\common.pb.$procmux$9294_Y I1=$false I2=common.pb.timer_idle[14] I3=$auto$alumacc.cc:474:replace_alu$16124.C[14] O=$abc$44715$techmap\common.pb.$procmux$9310_Y[14]
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:1059|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/arith_map.v:62|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:56"
.param LUT_INIT 0000101010100000
.gate SB_CARRY CI=$auto$alumacc.cc:474:replace_alu$16124.C[14] CO=$auto$alumacc.cc:474:replace_alu$16124.C[15] I0=$false I1=common.pb.timer_idle[14]
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:1059|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/arith_map.v:56"
.gate SB_LUT4 I0=$abc$44715$techmap\common.pb.$procmux$9294_Y I1=$false I2=common.pb.timer_idle[15] I3=$auto$alumacc.cc:474:replace_alu$16124.C[15] O=$abc$44715$techmap\common.pb.$procmux$9310_Y[15]
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:1059|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/arith_map.v:62|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:56"
.param LUT_INIT 0000101010100000
.gate SB_CARRY CI=$auto$alumacc.cc:474:replace_alu$16124.C[15] CO=$auto$alumacc.cc:474:replace_alu$16124.C[16] I0=$false I1=common.pb.timer_idle[15]
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:1059|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/arith_map.v:56"
.gate SB_LUT4 I0=$abc$44715$techmap\common.pb.$procmux$9294_Y I1=$false I2=common.pb.timer_idle[16] I3=$auto$alumacc.cc:474:replace_alu$16124.C[16] O=$abc$44715$techmap\common.pb.$procmux$9310_Y[16]
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:1059|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/arith_map.v:62|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:56"
.param LUT_INIT 0000101010100000
.gate SB_CARRY CI=$auto$alumacc.cc:474:replace_alu$16124.C[16] CO=$auto$alumacc.cc:474:replace_alu$16124.C[17] I0=$false I1=common.pb.timer_idle[16]
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:1059|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/arith_map.v:56"
.gate SB_LUT4 I0=$abc$44715$techmap\common.pb.$procmux$9294_Y I1=$false I2=common.pb.timer_idle[17] I3=$auto$alumacc.cc:474:replace_alu$16124.C[17] O=$abc$44715$techmap\common.pb.$procmux$9310_Y[17]
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:1059|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/arith_map.v:62|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:56"
.param LUT_INIT 0000101010100000
.gate SB_CARRY CI=$auto$alumacc.cc:474:replace_alu$16124.C[17] CO=$auto$alumacc.cc:474:replace_alu$16124.C[18] I0=$false I1=common.pb.timer_idle[17]
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:1059|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/arith_map.v:56"
.gate SB_LUT4 I0=$abc$44715$techmap\common.pb.$procmux$9294_Y I1=$false I2=common.pb.timer_idle[18] I3=$auto$alumacc.cc:474:replace_alu$16124.C[18] O=$abc$44715$techmap\common.pb.$procmux$9310_Y[18]
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:1059|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/arith_map.v:62|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:56"
.param LUT_INIT 0000101010100000
.gate SB_CARRY CI=$auto$alumacc.cc:474:replace_alu$16124.C[18] CO=$auto$alumacc.cc:474:replace_alu$16124.C[19] I0=$false I1=common.pb.timer_idle[18]
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:1059|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/arith_map.v:56"
.gate SB_LUT4 I0=$abc$44715$techmap\common.pb.$procmux$9294_Y I1=$false I2=common.pb.timer_idle[19] I3=$auto$alumacc.cc:474:replace_alu$16124.C[19] O=$abc$44715$techmap\common.pb.$procmux$9310_Y[19]
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:1059|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/arith_map.v:62|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:56"
.param LUT_INIT 0000101010100000
.gate SB_CARRY CI=$auto$alumacc.cc:474:replace_alu$16124.C[19] CO=$auto$alumacc.cc:474:replace_alu$16124.C[20] I0=$false I1=common.pb.timer_idle[19]
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:1059|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/arith_map.v:56"
.gate SB_CARRY CI=common.pb.timer_idle[0] CO=$auto$alumacc.cc:474:replace_alu$16124.C[2] I0=$false I1=common.pb.timer_idle[1]
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:1059|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/arith_map.v:56"
.gate SB_LUT4 I0=$abc$44715$techmap\common.pb.$procmux$9294_Y I1=$false I2=common.pb.timer_idle[20] I3=$auto$alumacc.cc:474:replace_alu$16124.C[20] O=$abc$44715$techmap\common.pb.$procmux$9310_Y[20]
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:1059|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/arith_map.v:62|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:56"
.param LUT_INIT 0000101010100000
.gate SB_CARRY CI=$auto$alumacc.cc:474:replace_alu$16124.C[20] CO=$auto$alumacc.cc:474:replace_alu$16124.C[21] I0=$false I1=common.pb.timer_idle[20]
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:1059|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/arith_map.v:56"
.gate SB_LUT4 I0=$abc$44715$techmap\common.pb.$procmux$9294_Y I1=$false I2=common.pb.timer_idle[21] I3=$auto$alumacc.cc:474:replace_alu$16124.C[21] O=$abc$44715$techmap\common.pb.$procmux$9310_Y[21]
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:1059|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/arith_map.v:62|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:56"
.param LUT_INIT 0000101010100000
.gate SB_CARRY CI=$auto$alumacc.cc:474:replace_alu$16124.C[21] CO=$auto$alumacc.cc:474:replace_alu$16124.C[22] I0=$false I1=common.pb.timer_idle[21]
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:1059|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/arith_map.v:56"
.gate SB_LUT4 I0=$abc$44715$techmap\common.pb.$procmux$9294_Y I1=$false I2=common.pb.timer_idle[22] I3=$auto$alumacc.cc:474:replace_alu$16124.C[22] O=$abc$44715$techmap\common.pb.$procmux$9310_Y[22]
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:1059|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/arith_map.v:62|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:56"
.param LUT_INIT 0000101010100000
.gate SB_CARRY CI=$auto$alumacc.cc:474:replace_alu$16124.C[22] CO=$auto$alumacc.cc:474:replace_alu$16124.C[23] I0=$false I1=common.pb.timer_idle[22]
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:1059|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/arith_map.v:56"
.gate SB_LUT4 I0=$false I1=$abc$44715$techmap\common.pb.$procmux$9294_Y I2=common.pb.timer_idle[23] I3=$auto$alumacc.cc:474:replace_alu$16124.C[23] O=$abc$44715$techmap\common.pb.$procmux$9310_Y[23]
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:1059|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/arith_map.v:62|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:56"
.param LUT_INIT 0000110011000000
.gate SB_LUT4 I0=$abc$44715$techmap\common.pb.$procmux$9294_Y I1=$false I2=common.pb.timer_idle[2] I3=$auto$alumacc.cc:474:replace_alu$16124.C[2] O=$abc$44715$techmap\common.pb.$procmux$9310_Y[2]
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:1059|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/arith_map.v:62|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:56"
.param LUT_INIT 0000101010100000
.gate SB_CARRY CI=$auto$alumacc.cc:474:replace_alu$16124.C[2] CO=$auto$alumacc.cc:474:replace_alu$16124.C[3] I0=$false I1=common.pb.timer_idle[2]
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:1059|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/arith_map.v:56"
.gate SB_LUT4 I0=$abc$44715$techmap\common.pb.$procmux$9294_Y I1=$false I2=common.pb.timer_idle[3] I3=$auto$alumacc.cc:474:replace_alu$16124.C[3] O=$abc$44715$techmap\common.pb.$procmux$9310_Y[3]
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:1059|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/arith_map.v:62|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:56"
.param LUT_INIT 0000101010100000
.gate SB_CARRY CI=$auto$alumacc.cc:474:replace_alu$16124.C[3] CO=$auto$alumacc.cc:474:replace_alu$16124.C[4] I0=$false I1=common.pb.timer_idle[3]
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:1059|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/arith_map.v:56"
.gate SB_LUT4 I0=$abc$44715$techmap\common.pb.$procmux$9294_Y I1=$false I2=common.pb.timer_idle[4] I3=$auto$alumacc.cc:474:replace_alu$16124.C[4] O=$abc$44715$techmap\common.pb.$procmux$9310_Y[4]
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:1059|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/arith_map.v:62|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:56"
.param LUT_INIT 0000101010100000
.gate SB_CARRY CI=$auto$alumacc.cc:474:replace_alu$16124.C[4] CO=$auto$alumacc.cc:474:replace_alu$16124.C[5] I0=$false I1=common.pb.timer_idle[4]
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:1059|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/arith_map.v:56"
.gate SB_LUT4 I0=$abc$44715$techmap\common.pb.$procmux$9294_Y I1=$false I2=common.pb.timer_idle[5] I3=$auto$alumacc.cc:474:replace_alu$16124.C[5] O=$abc$44715$techmap\common.pb.$procmux$9310_Y[5]
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:1059|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/arith_map.v:62|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:56"
.param LUT_INIT 0000101010100000
.gate SB_CARRY CI=$auto$alumacc.cc:474:replace_alu$16124.C[5] CO=$auto$alumacc.cc:474:replace_alu$16124.C[6] I0=$false I1=common.pb.timer_idle[5]
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:1059|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/arith_map.v:56"
.gate SB_LUT4 I0=$abc$44715$techmap\common.pb.$procmux$9294_Y I1=$false I2=common.pb.timer_idle[6] I3=$auto$alumacc.cc:474:replace_alu$16124.C[6] O=$abc$44715$techmap\common.pb.$procmux$9310_Y[6]
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:1059|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/arith_map.v:62|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:56"
.param LUT_INIT 0000101010100000
.gate SB_CARRY CI=$auto$alumacc.cc:474:replace_alu$16124.C[6] CO=$auto$alumacc.cc:474:replace_alu$16124.C[7] I0=$false I1=common.pb.timer_idle[6]
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:1059|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/arith_map.v:56"
.gate SB_LUT4 I0=$abc$44715$techmap\common.pb.$procmux$9294_Y I1=$false I2=common.pb.timer_idle[7] I3=$auto$alumacc.cc:474:replace_alu$16124.C[7] O=$abc$44715$techmap\common.pb.$procmux$9310_Y[7]
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:1059|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/arith_map.v:62|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:56"
.param LUT_INIT 0000101010100000
.gate SB_CARRY CI=$auto$alumacc.cc:474:replace_alu$16124.C[7] CO=$auto$alumacc.cc:474:replace_alu$16124.C[8] I0=$false I1=common.pb.timer_idle[7]
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:1059|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/arith_map.v:56"
.gate SB_LUT4 I0=$abc$44715$techmap\common.pb.$procmux$9294_Y I1=$false I2=common.pb.timer_idle[8] I3=$auto$alumacc.cc:474:replace_alu$16124.C[8] O=$abc$44715$techmap\common.pb.$procmux$9310_Y[8]
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:1059|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/arith_map.v:62|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:56"
.param LUT_INIT 0000101010100000
.gate SB_CARRY CI=$auto$alumacc.cc:474:replace_alu$16124.C[8] CO=$auto$alumacc.cc:474:replace_alu$16124.C[9] I0=$false I1=common.pb.timer_idle[8]
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:1059|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/arith_map.v:56"
.gate SB_LUT4 I0=$abc$44715$techmap\common.pb.$procmux$9294_Y I1=$false I2=common.pb.timer_idle[9] I3=$auto$alumacc.cc:474:replace_alu$16124.C[9] O=$abc$44715$techmap\common.pb.$procmux$9310_Y[9]
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:1059|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/arith_map.v:62|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:56"
.param LUT_INIT 0000101010100000
.gate SB_CARRY CI=$auto$alumacc.cc:474:replace_alu$16124.C[9] CO=$auto$alumacc.cc:474:replace_alu$16124.C[10] I0=$false I1=common.pb.timer_idle[9]
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:1059|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/arith_map.v:56"
.gate SB_LUT4 I0=$false I1=$true I2=common.pb.tx_buf_wr_addr[0] I3=$false O=common.pb.tx_buf_wr_addr_next[0]
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:308|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/arith_map.v:62|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:56"
.param LUT_INIT 0110100110010110
.gate SB_CARRY CI=common.pb.tx_buf_wr_addr[0] CO=$auto$alumacc.cc:474:replace_alu$16127.C[2] I0=$false I1=common.pb.tx_buf_wr_addr[1]
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:308|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/arith_map.v:56"
.gate SB_LUT4 I0=$false I1=$false I2=common.pb.tx_buf_wr_addr[2] I3=$auto$alumacc.cc:474:replace_alu$16127.C[2] O=common.pb.tx_buf_wr_addr_next[2]
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:308|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/arith_map.v:62|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:56"
.param LUT_INIT 0110100110010110
.gate SB_CARRY CI=$auto$alumacc.cc:474:replace_alu$16127.C[2] CO=$auto$alumacc.cc:474:replace_alu$16127.C[3] I0=$false I1=common.pb.tx_buf_wr_addr[2]
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:308|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/arith_map.v:56"
.gate SB_LUT4 I0=$false I1=$false I2=common.pb.tx_buf_wr_addr[3] I3=$auto$alumacc.cc:474:replace_alu$16127.C[3] O=common.pb.tx_buf_wr_addr_next[3]
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:308|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/arith_map.v:62|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:56"
.param LUT_INIT 0110100110010110
.gate SB_CARRY CI=$auto$alumacc.cc:474:replace_alu$16127.C[3] CO=$auto$alumacc.cc:474:replace_alu$16127.C[4] I0=$false I1=common.pb.tx_buf_wr_addr[3]
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:308|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/arith_map.v:56"
.gate SB_LUT4 I0=$false I1=$false I2=common.pb.tx_buf_wr_addr[4] I3=$auto$alumacc.cc:474:replace_alu$16127.C[4] O=common.pb.tx_buf_wr_addr_next[4]
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:308|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/arith_map.v:62|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:56"
.param LUT_INIT 0110100110010110
.gate SB_CARRY CI=$auto$alumacc.cc:474:replace_alu$16127.C[4] CO=$auto$alumacc.cc:474:replace_alu$16127.C[5] I0=$false I1=common.pb.tx_buf_wr_addr[4]
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:308|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/arith_map.v:56"
.gate SB_LUT4 I0=$false I1=$false I2=common.pb.tx_buf_wr_addr[5] I3=$auto$alumacc.cc:474:replace_alu$16127.C[5] O=common.pb.tx_buf_wr_addr_next[5]
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:308|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/arith_map.v:62|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:56"
.param LUT_INIT 0110100110010110
.gate SB_CARRY CI=$auto$alumacc.cc:474:replace_alu$16127.C[5] CO=$auto$alumacc.cc:474:replace_alu$16127.C[6] I0=$false I1=common.pb.tx_buf_wr_addr[5]
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:308|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/arith_map.v:56"
.gate SB_LUT4 I0=$false I1=$false I2=common.pb.tx_buf_wr_addr[6] I3=$auto$alumacc.cc:474:replace_alu$16127.C[6] O=common.pb.tx_buf_wr_addr_next[6]
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:308|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/arith_map.v:62|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:56"
.param LUT_INIT 0110100110010110
.gate SB_CARRY CI=$auto$alumacc.cc:474:replace_alu$16127.C[6] CO=$auto$alumacc.cc:474:replace_alu$16127.C[7] I0=$false I1=common.pb.tx_buf_wr_addr[6]
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:308|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/arith_map.v:56"
.gate SB_LUT4 I0=$false I1=$false I2=common.pb.tx_buf_wr_addr[7] I3=$auto$alumacc.cc:474:replace_alu$16127.C[7] O=common.pb.tx_buf_wr_addr_next[7]
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:308|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/arith_map.v:62|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:56"
.param LUT_INIT 0110100110010110
.gate SB_LUT4 I0=$false I1=$true I2=common.pb.rx_buf_wr_addr[0] I3=$false O=common.pb.rx_buf_wr_addr_next[0]
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:356|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/arith_map.v:62|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:56"
.param LUT_INIT 0110100110010110
.gate SB_CARRY CI=common.pb.rx_buf_wr_addr[0] CO=$auto$alumacc.cc:474:replace_alu$16130.C[2] I0=$false I1=common.pb.rx_buf_wr_addr[1]
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:356|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/arith_map.v:56"
.gate SB_LUT4 I0=$false I1=$false I2=common.pb.rx_buf_wr_addr[2] I3=$auto$alumacc.cc:474:replace_alu$16130.C[2] O=common.pb.rx_buf_wr_addr_next[2]
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:356|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/arith_map.v:62|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:56"
.param LUT_INIT 0110100110010110
.gate SB_CARRY CI=$auto$alumacc.cc:474:replace_alu$16130.C[2] CO=$auto$alumacc.cc:474:replace_alu$16130.C[3] I0=$false I1=common.pb.rx_buf_wr_addr[2]
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:356|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/arith_map.v:56"
.gate SB_LUT4 I0=$false I1=$false I2=common.pb.rx_buf_wr_addr[3] I3=$auto$alumacc.cc:474:replace_alu$16130.C[3] O=common.pb.rx_buf_wr_addr_next[3]
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:356|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/arith_map.v:62|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:56"
.param LUT_INIT 0110100110010110
.gate SB_CARRY CI=$auto$alumacc.cc:474:replace_alu$16130.C[3] CO=$auto$alumacc.cc:474:replace_alu$16130.C[4] I0=$false I1=common.pb.rx_buf_wr_addr[3]
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:356|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/arith_map.v:56"
.gate SB_LUT4 I0=$false I1=$false I2=common.pb.rx_buf_wr_addr[4] I3=$auto$alumacc.cc:474:replace_alu$16130.C[4] O=common.pb.rx_buf_wr_addr_next[4]
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:356|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/arith_map.v:62|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:56"
.param LUT_INIT 0110100110010110
.gate SB_CARRY CI=$auto$alumacc.cc:474:replace_alu$16130.C[4] CO=$auto$alumacc.cc:474:replace_alu$16130.C[5] I0=$false I1=common.pb.rx_buf_wr_addr[4]
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:356|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/arith_map.v:56"
.gate SB_LUT4 I0=$false I1=$false I2=common.pb.rx_buf_wr_addr[5] I3=$auto$alumacc.cc:474:replace_alu$16130.C[5] O=common.pb.rx_buf_wr_addr_next[5]
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:356|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/arith_map.v:62|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:56"
.param LUT_INIT 0110100110010110
.gate SB_CARRY CI=$auto$alumacc.cc:474:replace_alu$16130.C[5] CO=$auto$alumacc.cc:474:replace_alu$16130.C[6] I0=$false I1=common.pb.rx_buf_wr_addr[5]
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:356|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/arith_map.v:56"
.gate SB_LUT4 I0=$false I1=$false I2=common.pb.rx_buf_wr_addr[6] I3=$auto$alumacc.cc:474:replace_alu$16130.C[6] O=common.pb.rx_buf_wr_addr_next[6]
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:356|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/arith_map.v:62|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:56"
.param LUT_INIT 0110100110010110
.gate SB_CARRY CI=$auto$alumacc.cc:474:replace_alu$16130.C[6] CO=$auto$alumacc.cc:474:replace_alu$16130.C[7] I0=$false I1=common.pb.rx_buf_wr_addr[6]
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:356|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/arith_map.v:56"
.gate SB_LUT4 I0=$false I1=$false I2=common.pb.rx_buf_wr_addr[7] I3=$auto$alumacc.cc:474:replace_alu$16130.C[7] O=common.pb.rx_buf_wr_addr_next[7]
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:356|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/arith_map.v:62|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:56"
.param LUT_INIT 0110100110010110
.gate SB_LUT4 I0=$false I1=$true I2=common.pb.tx_buf_rd_addr[0] I3=$false O=$auto$wreduce.cc:455:run$15906[0]
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:522|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/arith_map.v:62|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:56"
.param LUT_INIT 0110100110010110
.gate SB_CARRY CI=common.pb.tx_buf_rd_addr[0] CO=$auto$alumacc.cc:474:replace_alu$16133.C[2] I0=$false I1=common.pb.tx_buf_rd_addr[1]
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:522|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/arith_map.v:56"
.gate SB_LUT4 I0=$false I1=$false I2=common.pb.tx_buf_rd_addr[2] I3=$auto$alumacc.cc:474:replace_alu$16133.C[2] O=$auto$wreduce.cc:455:run$15906[2]
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:522|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/arith_map.v:62|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:56"
.param LUT_INIT 0110100110010110
.gate SB_CARRY CI=$auto$alumacc.cc:474:replace_alu$16133.C[2] CO=$auto$alumacc.cc:474:replace_alu$16133.C[3] I0=$false I1=common.pb.tx_buf_rd_addr[2]
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:522|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/arith_map.v:56"
.gate SB_LUT4 I0=$false I1=$false I2=common.pb.tx_buf_rd_addr[3] I3=$auto$alumacc.cc:474:replace_alu$16133.C[3] O=$auto$wreduce.cc:455:run$15906[3]
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:522|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/arith_map.v:62|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:56"
.param LUT_INIT 0110100110010110
.gate SB_CARRY CI=$auto$alumacc.cc:474:replace_alu$16133.C[3] CO=$auto$alumacc.cc:474:replace_alu$16133.C[4] I0=$false I1=common.pb.tx_buf_rd_addr[3]
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:522|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/arith_map.v:56"
.gate SB_LUT4 I0=$false I1=$false I2=common.pb.tx_buf_rd_addr[4] I3=$auto$alumacc.cc:474:replace_alu$16133.C[4] O=$auto$wreduce.cc:455:run$15906[4]
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:522|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/arith_map.v:62|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:56"
.param LUT_INIT 0110100110010110
.gate SB_CARRY CI=$auto$alumacc.cc:474:replace_alu$16133.C[4] CO=$auto$alumacc.cc:474:replace_alu$16133.C[5] I0=$false I1=common.pb.tx_buf_rd_addr[4]
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:522|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/arith_map.v:56"
.gate SB_LUT4 I0=$false I1=$false I2=common.pb.tx_buf_rd_addr[5] I3=$auto$alumacc.cc:474:replace_alu$16133.C[5] O=$auto$wreduce.cc:455:run$15906[5]
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:522|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/arith_map.v:62|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:56"
.param LUT_INIT 0110100110010110
.gate SB_CARRY CI=$auto$alumacc.cc:474:replace_alu$16133.C[5] CO=$auto$alumacc.cc:474:replace_alu$16133.C[6] I0=$false I1=common.pb.tx_buf_rd_addr[5]
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:522|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/arith_map.v:56"
.gate SB_LUT4 I0=$false I1=$false I2=common.pb.tx_buf_rd_addr[6] I3=$auto$alumacc.cc:474:replace_alu$16133.C[6] O=$auto$wreduce.cc:455:run$15906[6]
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:522|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/arith_map.v:62|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:56"
.param LUT_INIT 0110100110010110
.gate SB_CARRY CI=$auto$alumacc.cc:474:replace_alu$16133.C[6] CO=$auto$alumacc.cc:474:replace_alu$16133.C[7] I0=$false I1=common.pb.tx_buf_rd_addr[6]
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:522|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/arith_map.v:56"
.gate SB_LUT4 I0=$false I1=$false I2=common.pb.tx_buf_rd_addr[7] I3=$auto$alumacc.cc:474:replace_alu$16133.C[7] O=$auto$wreduce.cc:455:run$15906[7]
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:522|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/arith_map.v:62|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:56"
.param LUT_INIT 0110100110010110
.gate SB_CARRY CI=common.pb.spirx_bytecount[0] CO=$auto$alumacc.cc:474:replace_alu$16136.C[2] I0=$false I1=common.pb.spirx_bytecount[1]
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:690|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/arith_map.v:56"
.gate SB_LUT4 I0=$false I1=$false I2=common.pb.spirx_bytecount[2] I3=$auto$alumacc.cc:474:replace_alu$16136.C[2] O=$abc$44715$auto$wreduce.cc:455:run$15907[2]
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:690|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/arith_map.v:62|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:56"
.param LUT_INIT 0110100110010110
.gate SB_CARRY CI=$auto$alumacc.cc:474:replace_alu$16136.C[2] CO=$auto$alumacc.cc:474:replace_alu$16136.C[3] I0=$false I1=common.pb.spirx_bytecount[2]
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:690|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/arith_map.v:56"
.gate SB_LUT4 I0=$false I1=$false I2=common.pb.spirx_bytecount[3] I3=$auto$alumacc.cc:474:replace_alu$16136.C[3] O=$abc$44715$auto$wreduce.cc:455:run$15907[3]
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:690|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/arith_map.v:62|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:56"
.param LUT_INIT 0110100110010110
.gate SB_CARRY CI=$auto$alumacc.cc:474:replace_alu$16136.C[3] CO=$auto$alumacc.cc:474:replace_alu$16136.C[4] I0=$false I1=common.pb.spirx_bytecount[3]
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:690|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/arith_map.v:56"
.gate SB_LUT4 I0=$false I1=$false I2=common.pb.spirx_bytecount[4] I3=$auto$alumacc.cc:474:replace_alu$16136.C[4] O=$abc$44715$auto$wreduce.cc:455:run$15907[4]
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:690|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/arith_map.v:62|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:56"
.param LUT_INIT 0110100110010110
.gate SB_CARRY CI=$auto$alumacc.cc:474:replace_alu$16136.C[4] CO=$auto$alumacc.cc:474:replace_alu$16136.C[5] I0=$false I1=common.pb.spirx_bytecount[4]
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:690|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/arith_map.v:56"
.gate SB_LUT4 I0=$false I1=$false I2=common.pb.spirx_bytecount[5] I3=$auto$alumacc.cc:474:replace_alu$16136.C[5] O=$abc$44715$auto$wreduce.cc:455:run$15907[5]
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:690|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/arith_map.v:62|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:56"
.param LUT_INIT 0110100110010110
.gate SB_CARRY CI=$auto$alumacc.cc:474:replace_alu$16136.C[5] CO=$auto$alumacc.cc:474:replace_alu$16136.C[6] I0=$false I1=common.pb.spirx_bytecount[5]
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:690|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/arith_map.v:56"
.gate SB_LUT4 I0=$false I1=$false I2=common.pb.spirx_bytecount[6] I3=$auto$alumacc.cc:474:replace_alu$16136.C[6] O=$abc$44715$auto$wreduce.cc:455:run$15907[6]
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:690|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/arith_map.v:62|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:56"
.param LUT_INIT 0110100110010110
.gate SB_CARRY CI=$auto$alumacc.cc:474:replace_alu$16136.C[6] CO=$auto$alumacc.cc:474:replace_alu$16136.C[7] I0=$false I1=common.pb.spirx_bytecount[6]
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:690|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/arith_map.v:56"
.gate SB_LUT4 I0=$abc$44715$new_n1671_ I1=$abc$44715$new_n1680_ I2=common.pb.spirx_bytecount[7] I3=$auto$alumacc.cc:474:replace_alu$16136.C[7] O=$abc$44715$techmap$techmap\common.pb.$procmux$14359.$reduce_or$/home/mb/fpga-toolchain/yosys/bin/../share/yosys/techmap.v:441$18302_Y
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:690|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/arith_map.v:62|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:56"
.param LUT_INIT 0101001101110000
.gate SB_LUT4 I0=$false I1=common.pb.spirx_ctrl_data[10] I2=common.pb.spirx_ctrl_data[5] I3=$auto$alumacc.cc:474:replace_alu$16139.C[10] O=$techmap\common.pb.$0\tsyn_clks[23:0][10]
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:809|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/arith_map.v:62|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:56"
.param LUT_INIT 0110100110010110
.gate SB_CARRY CI=$auto$alumacc.cc:474:replace_alu$16139.C[10] CO=$auto$alumacc.cc:474:replace_alu$16139.C[11] I0=common.pb.spirx_ctrl_data[10] I1=common.pb.spirx_ctrl_data[5]
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:809|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/arith_map.v:56"
.gate SB_LUT4 I0=$false I1=common.pb.spirx_ctrl_data[11] I2=common.pb.spirx_ctrl_data[6] I3=$auto$alumacc.cc:474:replace_alu$16139.C[11] O=$techmap\common.pb.$0\tsyn_clks[23:0][11]
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:809|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/arith_map.v:62|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:56"
.param LUT_INIT 0110100110010110
.gate SB_CARRY CI=$auto$alumacc.cc:474:replace_alu$16139.C[11] CO=$auto$alumacc.cc:474:replace_alu$16139.C[12] I0=common.pb.spirx_ctrl_data[11] I1=common.pb.spirx_ctrl_data[6]
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:809|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/arith_map.v:56"
.gate SB_LUT4 I0=$false I1=common.pb.spirx_ctrl_data[12] I2=common.pb.spirx_ctrl_data[7] I3=$auto$alumacc.cc:474:replace_alu$16139.C[12] O=$techmap\common.pb.$0\tsyn_clks[23:0][12]
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:809|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/arith_map.v:62|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:56"
.param LUT_INIT 0110100110010110
.gate SB_CARRY CI=$auto$alumacc.cc:474:replace_alu$16139.C[12] CO=$auto$alumacc.cc:474:replace_alu$16139.C[13] I0=common.pb.spirx_ctrl_data[12] I1=common.pb.spirx_ctrl_data[7]
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:809|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/arith_map.v:56"
.gate SB_LUT4 I0=$false I1=common.pb.spirx_ctrl_data[13] I2=common.pb.spirx_ctrl_data[8] I3=$auto$alumacc.cc:474:replace_alu$16139.C[13] O=$techmap\common.pb.$0\tsyn_clks[23:0][13]
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:809|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/arith_map.v:62|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:56"
.param LUT_INIT 0110100110010110
.gate SB_CARRY CI=$auto$alumacc.cc:474:replace_alu$16139.C[13] CO=$auto$alumacc.cc:474:replace_alu$16139.C[14] I0=common.pb.spirx_ctrl_data[13] I1=common.pb.spirx_ctrl_data[8]
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:809|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/arith_map.v:56"
.gate SB_LUT4 I0=$false I1=common.pb.spirx_ctrl_data[14] I2=common.pb.spirx_ctrl_data[9] I3=$auto$alumacc.cc:474:replace_alu$16139.C[14] O=$techmap\common.pb.$0\tsyn_clks[23:0][14]
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:809|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/arith_map.v:62|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:56"
.param LUT_INIT 0110100110010110
.gate SB_CARRY CI=$auto$alumacc.cc:474:replace_alu$16139.C[14] CO=$auto$alumacc.cc:474:replace_alu$16139.C[15] I0=common.pb.spirx_ctrl_data[14] I1=common.pb.spirx_ctrl_data[9]
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:809|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/arith_map.v:56"
.gate SB_LUT4 I0=$false I1=common.pb.spirx_ctrl_data[15] I2=common.pb.spirx_ctrl_data[10] I3=$auto$alumacc.cc:474:replace_alu$16139.C[15] O=$techmap\common.pb.$0\tsyn_clks[23:0][15]
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:809|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/arith_map.v:62|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:56"
.param LUT_INIT 0110100110010110
.gate SB_CARRY CI=$auto$alumacc.cc:474:replace_alu$16139.C[15] CO=$auto$alumacc.cc:474:replace_alu$16139.C[16] I0=common.pb.spirx_ctrl_data[15] I1=common.pb.spirx_ctrl_data[10]
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:809|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/arith_map.v:56"
.gate SB_LUT4 I0=$false I1=common.pb.spirx_ctrl_data[16] I2=common.pb.spirx_ctrl_data[11] I3=$auto$alumacc.cc:474:replace_alu$16139.C[16] O=$techmap\common.pb.$0\tsyn_clks[23:0][16]
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:809|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/arith_map.v:62|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:56"
.param LUT_INIT 0110100110010110
.gate SB_CARRY CI=$auto$alumacc.cc:474:replace_alu$16139.C[16] CO=$auto$alumacc.cc:474:replace_alu$16139.C[17] I0=common.pb.spirx_ctrl_data[16] I1=common.pb.spirx_ctrl_data[11]
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:809|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/arith_map.v:56"
.gate SB_LUT4 I0=$false I1=common.pb.spirx_ctrl_data[17] I2=common.pb.spirx_ctrl_data[12] I3=$auto$alumacc.cc:474:replace_alu$16139.C[17] O=$techmap\common.pb.$0\tsyn_clks[23:0][17]
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:809|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/arith_map.v:62|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:56"
.param LUT_INIT 0110100110010110
.gate SB_CARRY CI=$auto$alumacc.cc:474:replace_alu$16139.C[17] CO=$auto$alumacc.cc:474:replace_alu$16139.C[18] I0=common.pb.spirx_ctrl_data[17] I1=common.pb.spirx_ctrl_data[12]
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:809|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/arith_map.v:56"
.gate SB_LUT4 I0=$false I1=common.pb.spirx_ctrl_data[18] I2=common.pb.spirx_ctrl_data[13] I3=$auto$alumacc.cc:474:replace_alu$16139.C[18] O=$techmap\common.pb.$0\tsyn_clks[23:0][18]
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:809|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/arith_map.v:62|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:56"
.param LUT_INIT 0110100110010110
.gate SB_CARRY CI=$auto$alumacc.cc:474:replace_alu$16139.C[18] CO=$auto$alumacc.cc:474:replace_alu$16139.C[19] I0=common.pb.spirx_ctrl_data[18] I1=common.pb.spirx_ctrl_data[13]
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:809|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/arith_map.v:56"
.gate SB_LUT4 I0=$false I1=common.pb.spirx_ctrl_data[19] I2=common.pb.spirx_ctrl_data[14] I3=$auto$alumacc.cc:474:replace_alu$16139.C[19] O=$techmap\common.pb.$0\tsyn_clks[23:0][19]
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:809|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/arith_map.v:62|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:56"
.param LUT_INIT 0110100110010110
.gate SB_CARRY CI=$auto$alumacc.cc:474:replace_alu$16139.C[19] CO=$auto$alumacc.cc:474:replace_alu$16139.C[20] I0=common.pb.spirx_ctrl_data[19] I1=common.pb.spirx_ctrl_data[14]
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:809|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/arith_map.v:56"
.gate SB_LUT4 I0=$false I1=common.pb.spirx_ctrl_data[20] I2=common.pb.spirx_ctrl_data[15] I3=$auto$alumacc.cc:474:replace_alu$16139.C[20] O=$techmap\common.pb.$0\tsyn_clks[23:0][20]
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:809|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/arith_map.v:62|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:56"
.param LUT_INIT 0110100110010110
.gate SB_CARRY CI=$auto$alumacc.cc:474:replace_alu$16139.C[20] CO=$auto$alumacc.cc:474:replace_alu$16139.C[21] I0=common.pb.spirx_ctrl_data[20] I1=common.pb.spirx_ctrl_data[15]
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:809|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/arith_map.v:56"
.gate SB_LUT4 I0=$false I1=common.pb.spirx_ctrl_data[21] I2=common.pb.spirx_ctrl_data[16] I3=$auto$alumacc.cc:474:replace_alu$16139.C[21] O=$techmap\common.pb.$0\tsyn_clks[23:0][21]
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:809|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/arith_map.v:62|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:56"
.param LUT_INIT 0110100110010110
.gate SB_CARRY CI=$auto$alumacc.cc:474:replace_alu$16139.C[21] CO=$auto$alumacc.cc:474:replace_alu$16139.C[22] I0=common.pb.spirx_ctrl_data[21] I1=common.pb.spirx_ctrl_data[16]
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:809|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/arith_map.v:56"
.gate SB_LUT4 I0=$false I1=common.pb.spirx_ctrl_data[22] I2=common.pb.spirx_ctrl_data[17] I3=$auto$alumacc.cc:474:replace_alu$16139.C[22] O=$techmap\common.pb.$0\tsyn_clks[23:0][22]
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:809|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/arith_map.v:62|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:56"
.param LUT_INIT 0110100110010110
.gate SB_CARRY CI=$auto$alumacc.cc:474:replace_alu$16139.C[22] CO=$auto$alumacc.cc:474:replace_alu$16139.C[23] I0=common.pb.spirx_ctrl_data[22] I1=common.pb.spirx_ctrl_data[17]
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:809|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/arith_map.v:56"
.gate SB_LUT4 I0=$false I1=common.pb.spirx_ctrl_data[23] I2=common.pb.spirx_ctrl_data[18] I3=$auto$alumacc.cc:474:replace_alu$16139.C[23] O=$techmap\common.pb.$0\tsyn_clks[23:0][23]
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:809|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/arith_map.v:62|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:56"
.param LUT_INIT 0110100110010110
.gate SB_CARRY CI=$false CO=$auto$alumacc.cc:474:replace_alu$16139.C[6] I0=common.pb.spirx_ctrl_data[5] I1=common.pb.spirx_ctrl_data[0]
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:809|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/arith_map.v:56"
.gate SB_LUT4 I0=$false I1=common.pb.spirx_ctrl_data[6] I2=common.pb.spirx_ctrl_data[1] I3=$auto$alumacc.cc:474:replace_alu$16139.C[6] O=$techmap\common.pb.$0\tsyn_clks[23:0][6]
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:809|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/arith_map.v:62|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:56"
.param LUT_INIT 0110100110010110
.gate SB_CARRY CI=$auto$alumacc.cc:474:replace_alu$16139.C[6] CO=$auto$alumacc.cc:474:replace_alu$16139.C[7] I0=common.pb.spirx_ctrl_data[6] I1=common.pb.spirx_ctrl_data[1]
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:809|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/arith_map.v:56"
.gate SB_LUT4 I0=$false I1=common.pb.spirx_ctrl_data[7] I2=common.pb.spirx_ctrl_data[2] I3=$auto$alumacc.cc:474:replace_alu$16139.C[7] O=$techmap\common.pb.$0\tsyn_clks[23:0][7]
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:809|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/arith_map.v:62|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:56"
.param LUT_INIT 0110100110010110
.gate SB_CARRY CI=$auto$alumacc.cc:474:replace_alu$16139.C[7] CO=$auto$alumacc.cc:474:replace_alu$16139.C[8] I0=common.pb.spirx_ctrl_data[7] I1=common.pb.spirx_ctrl_data[2]
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:809|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/arith_map.v:56"
.gate SB_LUT4 I0=$false I1=common.pb.spirx_ctrl_data[8] I2=common.pb.spirx_ctrl_data[3] I3=$auto$alumacc.cc:474:replace_alu$16139.C[8] O=$techmap\common.pb.$0\tsyn_clks[23:0][8]
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:809|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/arith_map.v:62|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:56"
.param LUT_INIT 0110100110010110
.gate SB_CARRY CI=$auto$alumacc.cc:474:replace_alu$16139.C[8] CO=$auto$alumacc.cc:474:replace_alu$16139.C[9] I0=common.pb.spirx_ctrl_data[8] I1=common.pb.spirx_ctrl_data[3]
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:809|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/arith_map.v:56"
.gate SB_LUT4 I0=$false I1=common.pb.spirx_ctrl_data[9] I2=common.pb.spirx_ctrl_data[4] I3=$auto$alumacc.cc:474:replace_alu$16139.C[9] O=$techmap\common.pb.$0\tsyn_clks[23:0][9]
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:809|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/arith_map.v:62|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:56"
.param LUT_INIT 0110100110010110
.gate SB_CARRY CI=$auto$alumacc.cc:474:replace_alu$16139.C[9] CO=$auto$alumacc.cc:474:replace_alu$16139.C[10] I0=common.pb.spirx_ctrl_data[9] I1=common.pb.spirx_ctrl_data[4]
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:809|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/arith_map.v:56"
.gate SB_CARRY CI=common.pb.spitx_bytecount[0] CO=$auto$alumacc.cc:474:replace_alu$16142.C[2] I0=$false I1=common.pb.spitx_bytecount[1]
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:891|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/arith_map.v:56"
.gate SB_LUT4 I0=$abc$44715$new_n1952_ I1=$false I2=common.pb.spitx_bytecount[2] I3=$auto$alumacc.cc:474:replace_alu$16142.C[2] O=$abc$44715$techmap\common.pb.$procmux$12940_Y[2]
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:891|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/arith_map.v:62|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:56"
.param LUT_INIT 0000010101010000
.gate SB_CARRY CI=$auto$alumacc.cc:474:replace_alu$16142.C[2] CO=$auto$alumacc.cc:474:replace_alu$16142.C[3] I0=$false I1=common.pb.spitx_bytecount[2]
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:891|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/arith_map.v:56"
.gate SB_LUT4 I0=$abc$44715$new_n1952_ I1=$false I2=common.pb.spitx_bytecount[3] I3=$auto$alumacc.cc:474:replace_alu$16142.C[3] O=$abc$44715$techmap\common.pb.$procmux$12940_Y[3]
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:891|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/arith_map.v:62|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:56"
.param LUT_INIT 0000010101010000
.gate SB_CARRY CI=$auto$alumacc.cc:474:replace_alu$16142.C[3] CO=$auto$alumacc.cc:474:replace_alu$16142.C[4] I0=$false I1=common.pb.spitx_bytecount[3]
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:891|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/arith_map.v:56"
.gate SB_LUT4 I0=$abc$44715$new_n1952_ I1=$false I2=common.pb.spitx_bytecount[4] I3=$auto$alumacc.cc:474:replace_alu$16142.C[4] O=$abc$44715$techmap\common.pb.$procmux$12940_Y[4]
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:891|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/arith_map.v:62|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:56"
.param LUT_INIT 0000010101010000
.gate SB_CARRY CI=$auto$alumacc.cc:474:replace_alu$16142.C[4] CO=$auto$alumacc.cc:474:replace_alu$16142.C[5] I0=$false I1=common.pb.spitx_bytecount[4]
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:891|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/arith_map.v:56"
.gate SB_LUT4 I0=$abc$44715$new_n1952_ I1=$false I2=common.pb.spitx_bytecount[5] I3=$auto$alumacc.cc:474:replace_alu$16142.C[5] O=$abc$44715$techmap\common.pb.$procmux$12940_Y[5]
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:891|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/arith_map.v:62|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:56"
.param LUT_INIT 0000010101010000
.gate SB_CARRY CI=$auto$alumacc.cc:474:replace_alu$16142.C[5] CO=$auto$alumacc.cc:474:replace_alu$16142.C[6] I0=$false I1=common.pb.spitx_bytecount[5]
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:891|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/arith_map.v:56"
.gate SB_LUT4 I0=$abc$44715$new_n1952_ I1=$false I2=common.pb.spitx_bytecount[6] I3=$auto$alumacc.cc:474:replace_alu$16142.C[6] O=$abc$44715$techmap\common.pb.$procmux$12940_Y[6]
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:891|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/arith_map.v:62|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:56"
.param LUT_INIT 0000010101010000
.gate SB_CARRY CI=$auto$alumacc.cc:474:replace_alu$16142.C[6] CO=$auto$alumacc.cc:474:replace_alu$16142.C[7] I0=$false I1=common.pb.spitx_bytecount[6]
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:891|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/arith_map.v:56"
.gate SB_LUT4 I0=$false I1=$abc$44715$new_n1952_ I2=common.pb.spitx_bytecount[7] I3=$auto$alumacc.cc:474:replace_alu$16142.C[7] O=$abc$44715$techmap\common.pb.$procmux$12940_Y[7]
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:891|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/arith_map.v:62|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:56"
.param LUT_INIT 0000001100110000
.gate SB_LUT4 I0=$false I1=$true I2=common.pb.rx_buf_rd_addr[0] I3=$false O=$techmap\common.pb.$0\rx_buf_rd_addr[7:0][0]
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:997|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/arith_map.v:62|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:56"
.param LUT_INIT 0110100110010110
.gate SB_CARRY CI=common.pb.rx_buf_rd_addr[0] CO=$auto$alumacc.cc:474:replace_alu$16145.C[2] I0=$false I1=common.pb.rx_buf_rd_addr[1]
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:997|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/arith_map.v:56"
.gate SB_LUT4 I0=$false I1=$false I2=common.pb.rx_buf_rd_addr[2] I3=$auto$alumacc.cc:474:replace_alu$16145.C[2] O=$techmap\common.pb.$0\rx_buf_rd_addr[7:0][2]
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:997|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/arith_map.v:62|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:56"
.param LUT_INIT 0110100110010110
.gate SB_CARRY CI=$auto$alumacc.cc:474:replace_alu$16145.C[2] CO=$auto$alumacc.cc:474:replace_alu$16145.C[3] I0=$false I1=common.pb.rx_buf_rd_addr[2]
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:997|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/arith_map.v:56"
.gate SB_LUT4 I0=$false I1=$false I2=common.pb.rx_buf_rd_addr[3] I3=$auto$alumacc.cc:474:replace_alu$16145.C[3] O=$techmap\common.pb.$0\rx_buf_rd_addr[7:0][3]
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:997|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/arith_map.v:62|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:56"
.param LUT_INIT 0110100110010110
.gate SB_CARRY CI=$auto$alumacc.cc:474:replace_alu$16145.C[3] CO=$auto$alumacc.cc:474:replace_alu$16145.C[4] I0=$false I1=common.pb.rx_buf_rd_addr[3]
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:997|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/arith_map.v:56"
.gate SB_LUT4 I0=$false I1=$false I2=common.pb.rx_buf_rd_addr[4] I3=$auto$alumacc.cc:474:replace_alu$16145.C[4] O=$techmap\common.pb.$0\rx_buf_rd_addr[7:0][4]
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:997|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/arith_map.v:62|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:56"
.param LUT_INIT 0110100110010110
.gate SB_CARRY CI=$auto$alumacc.cc:474:replace_alu$16145.C[4] CO=$auto$alumacc.cc:474:replace_alu$16145.C[5] I0=$false I1=common.pb.rx_buf_rd_addr[4]
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:997|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/arith_map.v:56"
.gate SB_LUT4 I0=$false I1=$false I2=common.pb.rx_buf_rd_addr[5] I3=$auto$alumacc.cc:474:replace_alu$16145.C[5] O=$techmap\common.pb.$0\rx_buf_rd_addr[7:0][5]
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:997|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/arith_map.v:62|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:56"
.param LUT_INIT 0110100110010110
.gate SB_CARRY CI=$auto$alumacc.cc:474:replace_alu$16145.C[5] CO=$auto$alumacc.cc:474:replace_alu$16145.C[6] I0=$false I1=common.pb.rx_buf_rd_addr[5]
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:997|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/arith_map.v:56"
.gate SB_LUT4 I0=$false I1=$false I2=common.pb.rx_buf_rd_addr[6] I3=$auto$alumacc.cc:474:replace_alu$16145.C[6] O=$techmap\common.pb.$0\rx_buf_rd_addr[7:0][6]
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:997|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/arith_map.v:62|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:56"
.param LUT_INIT 0110100110010110
.gate SB_CARRY CI=$auto$alumacc.cc:474:replace_alu$16145.C[6] CO=$auto$alumacc.cc:474:replace_alu$16145.C[7] I0=$false I1=common.pb.rx_buf_rd_addr[6]
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:997|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/arith_map.v:56"
.gate SB_LUT4 I0=$false I1=$false I2=common.pb.rx_buf_rd_addr[7] I3=$auto$alumacc.cc:474:replace_alu$16145.C[7] O=$techmap\common.pb.$0\rx_buf_rd_addr[7:0][7]
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:997|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/arith_map.v:62|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:56"
.param LUT_INIT 0110100110010110
.gate SB_CARRY CI=common.pb.spitx_len[0] CO=$auto$alumacc.cc:474:replace_alu$16148.C[2] I0=$false I1=common.pb.spitx_len[1]
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:999|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/arith_map.v:56"
.gate SB_LUT4 I0=$abc$44715$auto$simplemap.cc:168:logic_reduce$19575 I1=$false I2=common.pb.spitx_len[2] I3=$auto$alumacc.cc:474:replace_alu$16148.C[2] O=$abc$44715$techmap\common.pb.$procmux$12896_Y[2]
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:999|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/arith_map.v:62|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:56"
.param LUT_INIT 0000101010100000
.gate SB_CARRY CI=$auto$alumacc.cc:474:replace_alu$16148.C[2] CO=$auto$alumacc.cc:474:replace_alu$16148.C[3] I0=$false I1=common.pb.spitx_len[2]
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:999|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/arith_map.v:56"
.gate SB_LUT4 I0=$abc$44715$auto$simplemap.cc:168:logic_reduce$19575 I1=$false I2=common.pb.spitx_len[3] I3=$auto$alumacc.cc:474:replace_alu$16148.C[3] O=$abc$44715$techmap\common.pb.$procmux$12896_Y[3]
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:999|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/arith_map.v:62|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:56"
.param LUT_INIT 0000101010100000
.gate SB_CARRY CI=$auto$alumacc.cc:474:replace_alu$16148.C[3] CO=$auto$alumacc.cc:474:replace_alu$16148.C[4] I0=$false I1=common.pb.spitx_len[3]
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:999|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/arith_map.v:56"
.gate SB_LUT4 I0=$abc$44715$auto$simplemap.cc:168:logic_reduce$19575 I1=$false I2=common.pb.spitx_len[4] I3=$auto$alumacc.cc:474:replace_alu$16148.C[4] O=$abc$44715$techmap\common.pb.$procmux$12896_Y[4]
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:999|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/arith_map.v:62|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:56"
.param LUT_INIT 0000101010100000
.gate SB_CARRY CI=$auto$alumacc.cc:474:replace_alu$16148.C[4] CO=$auto$alumacc.cc:474:replace_alu$16148.C[5] I0=$false I1=common.pb.spitx_len[4]
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:999|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/arith_map.v:56"
.gate SB_LUT4 I0=$abc$44715$auto$simplemap.cc:168:logic_reduce$19575 I1=$false I2=common.pb.spitx_len[5] I3=$auto$alumacc.cc:474:replace_alu$16148.C[5] O=$abc$44715$techmap\common.pb.$procmux$12896_Y[5]
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:999|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/arith_map.v:62|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:56"
.param LUT_INIT 0000101010100000
.gate SB_CARRY CI=$auto$alumacc.cc:474:replace_alu$16148.C[5] CO=$auto$alumacc.cc:474:replace_alu$16148.C[6] I0=$false I1=common.pb.spitx_len[5]
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:999|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/arith_map.v:56"
.gate SB_LUT4 I0=$abc$44715$auto$simplemap.cc:168:logic_reduce$19575 I1=$false I2=common.pb.spitx_len[6] I3=$auto$alumacc.cc:474:replace_alu$16148.C[6] O=$abc$44715$techmap\common.pb.$procmux$12896_Y[6]
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:999|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/arith_map.v:62|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:56"
.param LUT_INIT 0000101010100000
.gate SB_CARRY CI=$auto$alumacc.cc:474:replace_alu$16148.C[6] CO=$auto$alumacc.cc:474:replace_alu$16148.C[7] I0=$false I1=common.pb.spitx_len[6]
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:999|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/arith_map.v:56"
.gate SB_LUT4 I0=$false I1=$abc$44715$auto$simplemap.cc:168:logic_reduce$19575 I2=common.pb.spitx_len[7] I3=$auto$alumacc.cc:474:replace_alu$16148.C[7] O=$abc$44715$techmap\common.pb.$procmux$12896_Y[7]
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:999|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/arith_map.v:62|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:56"
.param LUT_INIT 0000110011000000
.gate SB_CARRY CI=common.pb.spi.bit_count[0] CO=$auto$alumacc.cc:474:replace_alu$16151.C[2] I0=$false I1=common.pb.spi.bit_count[1]
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:438|spi_slave_mod.v:134|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/arith_map.v:56"
.gate SB_LUT4 I0=$abc$44715$auto$rtlil.cc:1836:ReduceOr$16042 I1=$false I2=common.pb.spi.bit_count[2] I3=$auto$alumacc.cc:474:replace_alu$16151.C[2] O=$abc$44715$techmap\common.pb.spi.$procmux$14923_Y[2]
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:438|spi_slave_mod.v:134|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/arith_map.v:62|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:56"
.param LUT_INIT 0000010101010000
.gate SB_CARRY CI=$auto$alumacc.cc:474:replace_alu$16151.C[2] CO=$auto$alumacc.cc:474:replace_alu$16151.C[3] I0=$false I1=common.pb.spi.bit_count[2]
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:438|spi_slave_mod.v:134|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/arith_map.v:56"
.gate SB_LUT4 I0=$abc$44715$auto$rtlil.cc:1836:ReduceOr$16042 I1=$false I2=common.pb.spi.bit_count[3] I3=$auto$alumacc.cc:474:replace_alu$16151.C[3] O=$abc$44715$techmap\common.pb.spi.$procmux$14923_Y[3]
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:438|spi_slave_mod.v:134|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/arith_map.v:62|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:56"
.param LUT_INIT 0000010101010000
.gate SB_CARRY CI=$auto$alumacc.cc:474:replace_alu$16151.C[3] CO=$auto$alumacc.cc:474:replace_alu$16151.C[4] I0=$false I1=common.pb.spi.bit_count[3]
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:438|spi_slave_mod.v:134|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/arith_map.v:56"
.gate SB_LUT4 I0=$abc$44715$auto$rtlil.cc:1836:ReduceOr$16042 I1=$false I2=common.pb.spi.bit_count[4] I3=$auto$alumacc.cc:474:replace_alu$16151.C[4] O=$abc$44715$techmap\common.pb.spi.$procmux$14923_Y[4]
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:438|spi_slave_mod.v:134|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/arith_map.v:62|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:56"
.param LUT_INIT 0000010101010000
.gate SB_CARRY CI=$auto$alumacc.cc:474:replace_alu$16151.C[4] CO=$auto$alumacc.cc:474:replace_alu$16151.C[5] I0=$false I1=common.pb.spi.bit_count[4]
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:438|spi_slave_mod.v:134|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/arith_map.v:56"
.gate SB_LUT4 I0=$false I1=$abc$44715$auto$rtlil.cc:1836:ReduceOr$16042 I2=common.pb.spi.bit_count[5] I3=$auto$alumacc.cc:474:replace_alu$16151.C[5] O=$abc$44715$techmap\common.pb.spi.$procmux$14923_Y[5]
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:438|spi_slave_mod.v:134|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/arith_map.v:62|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:56"
.param LUT_INIT 0000001100110000
.gate SB_CARRY CI=common.pb.spirx_lencalc.byte_le[1] CO=$auto$alumacc.cc:474:replace_alu$16154.C[3] I0=$true I1=common.pb.spirx_lencalc.byte_le[2]
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:566|profibus_phy_mod.v:157|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/arith_map.v:56"
.gate SB_LUT4 I0=$false I1=$false I2=common.pb.spirx_lencalc.byte_le[3] I3=$auto$alumacc.cc:474:replace_alu$16154.C[3] O=$abc$44715$auto$wreduce.cc:455:run$15910[3]
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:566|profibus_phy_mod.v:157|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/arith_map.v:62|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:56"
.param LUT_INIT 0110100110010110
.gate SB_CARRY CI=$auto$alumacc.cc:474:replace_alu$16154.C[3] CO=$auto$alumacc.cc:474:replace_alu$16154.C[4] I0=$false I1=common.pb.spirx_lencalc.byte_le[3]
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:566|profibus_phy_mod.v:157|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/arith_map.v:56"
.gate SB_LUT4 I0=$false I1=$false I2=common.pb.spirx_lencalc.byte_le[4] I3=$auto$alumacc.cc:474:replace_alu$16154.C[4] O=$abc$44715$auto$wreduce.cc:455:run$15910[4]
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:566|profibus_phy_mod.v:157|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/arith_map.v:62|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:56"
.param LUT_INIT 0110100110010110
.gate SB_CARRY CI=$auto$alumacc.cc:474:replace_alu$16154.C[4] CO=$auto$alumacc.cc:474:replace_alu$16154.C[5] I0=$false I1=common.pb.spirx_lencalc.byte_le[4]
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:566|profibus_phy_mod.v:157|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/arith_map.v:56"
.gate SB_LUT4 I0=$false I1=$false I2=common.pb.spirx_lencalc.byte_le[5] I3=$auto$alumacc.cc:474:replace_alu$16154.C[5] O=$abc$44715$auto$wreduce.cc:455:run$15910[5]
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:566|profibus_phy_mod.v:157|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/arith_map.v:62|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:56"
.param LUT_INIT 0110100110010110
.gate SB_CARRY CI=$auto$alumacc.cc:474:replace_alu$16154.C[5] CO=$auto$alumacc.cc:474:replace_alu$16154.C[6] I0=$false I1=common.pb.spirx_lencalc.byte_le[5]
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:566|profibus_phy_mod.v:157|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/arith_map.v:56"
.gate SB_LUT4 I0=$false I1=$false I2=common.pb.spirx_lencalc.byte_le[6] I3=$auto$alumacc.cc:474:replace_alu$16154.C[6] O=$abc$44715$auto$wreduce.cc:455:run$15910[6]
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:566|profibus_phy_mod.v:157|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/arith_map.v:62|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:56"
.param LUT_INIT 0110100110010110
.gate SB_CARRY CI=$auto$alumacc.cc:474:replace_alu$16154.C[6] CO=$auto$alumacc.cc:474:replace_alu$16154.C[7] I0=$false I1=common.pb.spirx_lencalc.byte_le[6]
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:566|profibus_phy_mod.v:157|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/arith_map.v:56"
.gate SB_LUT4 I0=$false I1=$false I2=common.pb.spirx_lencalc.byte_le[7] I3=$auto$alumacc.cc:474:replace_alu$16154.C[7] O=$abc$44715$auto$wreduce.cc:455:run$15910[7]
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:566|profibus_phy_mod.v:157|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/arith_map.v:62|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:56"
.param LUT_INIT 0110100110010110
.gate SB_CARRY CI=common.pb.uart.rx_mod.sym_count[0] CO=$auto$alumacc.cc:474:replace_alu$16157.C[2] I0=$false I1=common.pb.uart.rx_mod.sym_count[1]
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:395|uart_mod.v:537|uart_mod.v:195|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/arith_map.v:56"
.gate SB_LUT4 I0=$false I1=$false I2=common.pb.uart.rx_mod.sym_count[2] I3=$auto$alumacc.cc:474:replace_alu$16157.C[2] O=$abc$44715$auto$wreduce.cc:455:run$15911[2]
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:395|uart_mod.v:537|uart_mod.v:195|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/arith_map.v:62|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:56"
.param LUT_INIT 0110100110010110
.gate SB_CARRY CI=$auto$alumacc.cc:474:replace_alu$16157.C[2] CO=$auto$alumacc.cc:474:replace_alu$16157.C[3] I0=$false I1=common.pb.uart.rx_mod.sym_count[2]
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:395|uart_mod.v:537|uart_mod.v:195|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/arith_map.v:56"
.gate SB_LUT4 I0=$abc$44715$new_n2105_ I1=$abc$44715$new_n2098_ I2=common.pb.uart.rx_mod.sym_count[3] I3=$auto$alumacc.cc:474:replace_alu$16157.C[3] O=$abc$44715$techmap\common.pb.uart.rx_mod.$procmux$15305_Y[3]
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:395|uart_mod.v:537|uart_mod.v:195|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/arith_map.v:62|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:56"
.param LUT_INIT 1010101110111010
.gate SB_CARRY CI=common.pb.uart.rx_mod.sym_count[1] CO=$auto$alumacc.cc:474:replace_alu$16160.C[3] I0=common.pb.uart.rx_mod.sym_count[2] I1=$true
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:395|uart_mod.v:537|uart_mod.v:216|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/arith_map.v:56"
.gate SB_LUT4 I0=$false I1=common.pb.uart.rx_mod.sym_count[3] I2=$true I3=$auto$alumacc.cc:474:replace_alu$16160.C[3] O=$abc$44715$auto$simplemap.cc:250:simplemap_eqne$21196[3]
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:395|uart_mod.v:537|uart_mod.v:216|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/arith_map.v:62|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:56"
.param LUT_INIT 0110100110010110
.gate SB_CARRY CI=$auto$alumacc.cc:474:replace_alu$16160.C[3] CO=$abc$44715$auto$alumacc.cc:474:replace_alu$16160.C[31] I0=common.pb.uart.rx_mod.sym_count[3] I1=$true
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:395|uart_mod.v:537|uart_mod.v:216|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/arith_map.v:56"
.gate SB_LUT4 I0=$false I1=$false I2=$true I3=$abc$44715$auto$alumacc.cc:474:replace_alu$16160.C[31] O=$abc$44715$auto$simplemap.cc:250:simplemap_eqne$21196[4]
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:395|uart_mod.v:537|uart_mod.v:216|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/arith_map.v:62|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:56"
.param LUT_INIT 0110100110010110
.gate SB_LUT4 I0=$false I1=$false I2=common.pb.uart.rx_mod.symclk.count[10] I3=$auto$alumacc.cc:474:replace_alu$16163.C[10] O=$abc$44715$auto$wreduce.cc:455:run$15912[10]
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:395|uart_mod.v:537|uart_mod.v:154|uart_mod.v:74|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/arith_map.v:62|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:56"
.param LUT_INIT 0110100110010110
.gate SB_CARRY CI=$auto$alumacc.cc:474:replace_alu$16163.C[10] CO=$auto$alumacc.cc:474:replace_alu$16163.C[11] I0=$false I1=common.pb.uart.rx_mod.symclk.count[10]
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:395|uart_mod.v:537|uart_mod.v:154|uart_mod.v:74|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/arith_map.v:56"
.gate SB_LUT4 I0=$false I1=$false I2=common.pb.uart.rx_mod.symclk.count[11] I3=$auto$alumacc.cc:474:replace_alu$16163.C[11] O=$abc$44715$auto$wreduce.cc:455:run$15912[11]
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:395|uart_mod.v:537|uart_mod.v:154|uart_mod.v:74|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/arith_map.v:62|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:56"
.param LUT_INIT 0110100110010110
.gate SB_CARRY CI=$auto$alumacc.cc:474:replace_alu$16163.C[11] CO=$auto$alumacc.cc:474:replace_alu$16163.C[12] I0=$false I1=common.pb.uart.rx_mod.symclk.count[11]
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:395|uart_mod.v:537|uart_mod.v:154|uart_mod.v:74|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/arith_map.v:56"
.gate SB_LUT4 I0=$false I1=$false I2=common.pb.uart.rx_mod.symclk.count[12] I3=$auto$alumacc.cc:474:replace_alu$16163.C[12] O=$abc$44715$auto$wreduce.cc:455:run$15912[12]
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:395|uart_mod.v:537|uart_mod.v:154|uart_mod.v:74|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/arith_map.v:62|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:56"
.param LUT_INIT 0110100110010110
.gate SB_CARRY CI=$auto$alumacc.cc:474:replace_alu$16163.C[12] CO=$auto$alumacc.cc:474:replace_alu$16163.C[13] I0=$false I1=common.pb.uart.rx_mod.symclk.count[12]
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:395|uart_mod.v:537|uart_mod.v:154|uart_mod.v:74|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/arith_map.v:56"
.gate SB_LUT4 I0=$false I1=$false I2=common.pb.uart.rx_mod.symclk.count[13] I3=$auto$alumacc.cc:474:replace_alu$16163.C[13] O=$abc$44715$auto$wreduce.cc:455:run$15912[13]
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:395|uart_mod.v:537|uart_mod.v:154|uart_mod.v:74|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/arith_map.v:62|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:56"
.param LUT_INIT 0110100110010110
.gate SB_CARRY CI=$auto$alumacc.cc:474:replace_alu$16163.C[13] CO=$auto$alumacc.cc:474:replace_alu$16163.C[14] I0=$false I1=common.pb.uart.rx_mod.symclk.count[13]
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:395|uart_mod.v:537|uart_mod.v:154|uart_mod.v:74|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/arith_map.v:56"
.gate SB_LUT4 I0=$false I1=$false I2=common.pb.uart.rx_mod.symclk.count[14] I3=$auto$alumacc.cc:474:replace_alu$16163.C[14] O=$abc$44715$auto$wreduce.cc:455:run$15912[14]
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:395|uart_mod.v:537|uart_mod.v:154|uart_mod.v:74|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/arith_map.v:62|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:56"
.param LUT_INIT 0110100110010110
.gate SB_CARRY CI=$auto$alumacc.cc:474:replace_alu$16163.C[14] CO=$auto$alumacc.cc:474:replace_alu$16163.C[15] I0=$false I1=common.pb.uart.rx_mod.symclk.count[14]
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:395|uart_mod.v:537|uart_mod.v:154|uart_mod.v:74|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/arith_map.v:56"
.gate SB_LUT4 I0=$false I1=$false I2=common.pb.uart.rx_mod.symclk.count[15] I3=$auto$alumacc.cc:474:replace_alu$16163.C[15] O=$abc$44715$auto$wreduce.cc:455:run$15912[15]
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:395|uart_mod.v:537|uart_mod.v:154|uart_mod.v:74|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/arith_map.v:62|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:56"
.param LUT_INIT 0110100110010110
.gate SB_CARRY CI=$auto$alumacc.cc:474:replace_alu$16163.C[15] CO=$auto$alumacc.cc:474:replace_alu$16163.C[16] I0=$false I1=common.pb.uart.rx_mod.symclk.count[15]
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:395|uart_mod.v:537|uart_mod.v:154|uart_mod.v:74|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/arith_map.v:56"
.gate SB_LUT4 I0=$false I1=$false I2=common.pb.uart.rx_mod.symclk.count[16] I3=$auto$alumacc.cc:474:replace_alu$16163.C[16] O=$abc$44715$auto$wreduce.cc:455:run$15912[16]
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:395|uart_mod.v:537|uart_mod.v:154|uart_mod.v:74|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/arith_map.v:62|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:56"
.param LUT_INIT 0110100110010110
.gate SB_CARRY CI=$auto$alumacc.cc:474:replace_alu$16163.C[16] CO=$auto$alumacc.cc:474:replace_alu$16163.C[17] I0=$false I1=common.pb.uart.rx_mod.symclk.count[16]
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:395|uart_mod.v:537|uart_mod.v:154|uart_mod.v:74|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/arith_map.v:56"
.gate SB_LUT4 I0=$false I1=$false I2=common.pb.uart.rx_mod.symclk.count[17] I3=$auto$alumacc.cc:474:replace_alu$16163.C[17] O=$abc$44715$auto$wreduce.cc:455:run$15912[17]
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:395|uart_mod.v:537|uart_mod.v:154|uart_mod.v:74|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/arith_map.v:62|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:56"
.param LUT_INIT 0110100110010110
.gate SB_CARRY CI=$auto$alumacc.cc:474:replace_alu$16163.C[17] CO=$auto$alumacc.cc:474:replace_alu$16163.C[18] I0=$false I1=common.pb.uart.rx_mod.symclk.count[17]
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:395|uart_mod.v:537|uart_mod.v:154|uart_mod.v:74|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/arith_map.v:56"
.gate SB_LUT4 I0=$false I1=$false I2=common.pb.uart.rx_mod.symclk.count[18] I3=$auto$alumacc.cc:474:replace_alu$16163.C[18] O=$abc$44715$auto$wreduce.cc:455:run$15912[18]
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:395|uart_mod.v:537|uart_mod.v:154|uart_mod.v:74|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/arith_map.v:62|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:56"
.param LUT_INIT 0110100110010110
.gate SB_CARRY CI=$auto$alumacc.cc:474:replace_alu$16163.C[18] CO=$auto$alumacc.cc:474:replace_alu$16163.C[19] I0=$false I1=common.pb.uart.rx_mod.symclk.count[18]
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:395|uart_mod.v:537|uart_mod.v:154|uart_mod.v:74|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/arith_map.v:56"
.gate SB_LUT4 I0=$false I1=$false I2=common.pb.uart.rx_mod.symclk.count[19] I3=$auto$alumacc.cc:474:replace_alu$16163.C[19] O=$abc$44715$auto$wreduce.cc:455:run$15912[19]
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:395|uart_mod.v:537|uart_mod.v:154|uart_mod.v:74|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/arith_map.v:62|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:56"
.param LUT_INIT 0110100110010110
.gate SB_CARRY CI=$auto$alumacc.cc:474:replace_alu$16163.C[19] CO=$auto$alumacc.cc:474:replace_alu$16163.C[20] I0=$false I1=common.pb.uart.rx_mod.symclk.count[19]
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:395|uart_mod.v:537|uart_mod.v:154|uart_mod.v:74|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/arith_map.v:56"
.gate SB_CARRY CI=common.pb.uart.rx_mod.symclk.count[0] CO=$auto$alumacc.cc:474:replace_alu$16163.C[2] I0=$false I1=common.pb.uart.rx_mod.symclk.count[1]
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:395|uart_mod.v:537|uart_mod.v:154|uart_mod.v:74|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/arith_map.v:56"
.gate SB_LUT4 I0=$false I1=$false I2=common.pb.uart.rx_mod.symclk.count[20] I3=$auto$alumacc.cc:474:replace_alu$16163.C[20] O=$abc$44715$auto$wreduce.cc:455:run$15912[20]
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:395|uart_mod.v:537|uart_mod.v:154|uart_mod.v:74|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/arith_map.v:62|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:56"
.param LUT_INIT 0110100110010110
.gate SB_CARRY CI=$auto$alumacc.cc:474:replace_alu$16163.C[20] CO=$auto$alumacc.cc:474:replace_alu$16163.C[21] I0=$false I1=common.pb.uart.rx_mod.symclk.count[20]
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:395|uart_mod.v:537|uart_mod.v:154|uart_mod.v:74|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/arith_map.v:56"
.gate SB_LUT4 I0=$false I1=$false I2=common.pb.uart.rx_mod.symclk.count[21] I3=$auto$alumacc.cc:474:replace_alu$16163.C[21] O=$abc$44715$auto$wreduce.cc:455:run$15912[21]
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:395|uart_mod.v:537|uart_mod.v:154|uart_mod.v:74|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/arith_map.v:62|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:56"
.param LUT_INIT 0110100110010110
.gate SB_CARRY CI=$auto$alumacc.cc:474:replace_alu$16163.C[21] CO=$auto$alumacc.cc:474:replace_alu$16163.C[22] I0=$false I1=common.pb.uart.rx_mod.symclk.count[21]
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:395|uart_mod.v:537|uart_mod.v:154|uart_mod.v:74|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/arith_map.v:56"
.gate SB_LUT4 I0=$false I1=$false I2=common.pb.uart.rx_mod.symclk.count[22] I3=$auto$alumacc.cc:474:replace_alu$16163.C[22] O=$abc$44715$auto$wreduce.cc:455:run$15912[22]
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:395|uart_mod.v:537|uart_mod.v:154|uart_mod.v:74|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/arith_map.v:62|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:56"
.param LUT_INIT 0110100110010110
.gate SB_CARRY CI=$auto$alumacc.cc:474:replace_alu$16163.C[22] CO=$auto$alumacc.cc:474:replace_alu$16163.C[23] I0=$false I1=common.pb.uart.rx_mod.symclk.count[22]
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:395|uart_mod.v:537|uart_mod.v:154|uart_mod.v:74|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/arith_map.v:56"
.gate SB_LUT4 I0=$false I1=$false I2=common.pb.uart.rx_mod.symclk.count[23] I3=$auto$alumacc.cc:474:replace_alu$16163.C[23] O=$abc$44715$auto$wreduce.cc:455:run$15912[23]
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:395|uart_mod.v:537|uart_mod.v:154|uart_mod.v:74|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/arith_map.v:62|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:56"
.param LUT_INIT 0110100110010110
.gate SB_LUT4 I0=$false I1=$false I2=common.pb.uart.rx_mod.symclk.count[2] I3=$auto$alumacc.cc:474:replace_alu$16163.C[2] O=$abc$44715$auto$wreduce.cc:455:run$15912[2]
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:395|uart_mod.v:537|uart_mod.v:154|uart_mod.v:74|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/arith_map.v:62|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:56"
.param LUT_INIT 0110100110010110
.gate SB_CARRY CI=$auto$alumacc.cc:474:replace_alu$16163.C[2] CO=$auto$alumacc.cc:474:replace_alu$16163.C[3] I0=$false I1=common.pb.uart.rx_mod.symclk.count[2]
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:395|uart_mod.v:537|uart_mod.v:154|uart_mod.v:74|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/arith_map.v:56"
.gate SB_LUT4 I0=$false I1=$false I2=common.pb.uart.rx_mod.symclk.count[3] I3=$auto$alumacc.cc:474:replace_alu$16163.C[3] O=$abc$44715$auto$wreduce.cc:455:run$15912[3]
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:395|uart_mod.v:537|uart_mod.v:154|uart_mod.v:74|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/arith_map.v:62|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:56"
.param LUT_INIT 0110100110010110
.gate SB_CARRY CI=$auto$alumacc.cc:474:replace_alu$16163.C[3] CO=$auto$alumacc.cc:474:replace_alu$16163.C[4] I0=$false I1=common.pb.uart.rx_mod.symclk.count[3]
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:395|uart_mod.v:537|uart_mod.v:154|uart_mod.v:74|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/arith_map.v:56"
.gate SB_LUT4 I0=$false I1=$false I2=common.pb.uart.rx_mod.symclk.count[4] I3=$auto$alumacc.cc:474:replace_alu$16163.C[4] O=$abc$44715$auto$wreduce.cc:455:run$15912[4]
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:395|uart_mod.v:537|uart_mod.v:154|uart_mod.v:74|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/arith_map.v:62|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:56"
.param LUT_INIT 0110100110010110
.gate SB_CARRY CI=$auto$alumacc.cc:474:replace_alu$16163.C[4] CO=$auto$alumacc.cc:474:replace_alu$16163.C[5] I0=$false I1=common.pb.uart.rx_mod.symclk.count[4]
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:395|uart_mod.v:537|uart_mod.v:154|uart_mod.v:74|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/arith_map.v:56"
.gate SB_LUT4 I0=$false I1=$false I2=common.pb.uart.rx_mod.symclk.count[5] I3=$auto$alumacc.cc:474:replace_alu$16163.C[5] O=$abc$44715$auto$wreduce.cc:455:run$15912[5]
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:395|uart_mod.v:537|uart_mod.v:154|uart_mod.v:74|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/arith_map.v:62|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:56"
.param LUT_INIT 0110100110010110
.gate SB_CARRY CI=$auto$alumacc.cc:474:replace_alu$16163.C[5] CO=$auto$alumacc.cc:474:replace_alu$16163.C[6] I0=$false I1=common.pb.uart.rx_mod.symclk.count[5]
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:395|uart_mod.v:537|uart_mod.v:154|uart_mod.v:74|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/arith_map.v:56"
.gate SB_LUT4 I0=$false I1=$false I2=common.pb.uart.rx_mod.symclk.count[6] I3=$auto$alumacc.cc:474:replace_alu$16163.C[6] O=$abc$44715$auto$wreduce.cc:455:run$15912[6]
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:395|uart_mod.v:537|uart_mod.v:154|uart_mod.v:74|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/arith_map.v:62|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:56"
.param LUT_INIT 0110100110010110
.gate SB_CARRY CI=$auto$alumacc.cc:474:replace_alu$16163.C[6] CO=$auto$alumacc.cc:474:replace_alu$16163.C[7] I0=$false I1=common.pb.uart.rx_mod.symclk.count[6]
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:395|uart_mod.v:537|uart_mod.v:154|uart_mod.v:74|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/arith_map.v:56"
.gate SB_LUT4 I0=$false I1=$false I2=common.pb.uart.rx_mod.symclk.count[7] I3=$auto$alumacc.cc:474:replace_alu$16163.C[7] O=$abc$44715$auto$wreduce.cc:455:run$15912[7]
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:395|uart_mod.v:537|uart_mod.v:154|uart_mod.v:74|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/arith_map.v:62|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:56"
.param LUT_INIT 0110100110010110
.gate SB_CARRY CI=$auto$alumacc.cc:474:replace_alu$16163.C[7] CO=$auto$alumacc.cc:474:replace_alu$16163.C[8] I0=$false I1=common.pb.uart.rx_mod.symclk.count[7]
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:395|uart_mod.v:537|uart_mod.v:154|uart_mod.v:74|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/arith_map.v:56"
.gate SB_LUT4 I0=$false I1=$false I2=common.pb.uart.rx_mod.symclk.count[8] I3=$auto$alumacc.cc:474:replace_alu$16163.C[8] O=$abc$44715$auto$wreduce.cc:455:run$15912[8]
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:395|uart_mod.v:537|uart_mod.v:154|uart_mod.v:74|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/arith_map.v:62|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:56"
.param LUT_INIT 0110100110010110
.gate SB_CARRY CI=$auto$alumacc.cc:474:replace_alu$16163.C[8] CO=$auto$alumacc.cc:474:replace_alu$16163.C[9] I0=$false I1=common.pb.uart.rx_mod.symclk.count[8]
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:395|uart_mod.v:537|uart_mod.v:154|uart_mod.v:74|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/arith_map.v:56"
.gate SB_LUT4 I0=$false I1=$false I2=common.pb.uart.rx_mod.symclk.count[9] I3=$auto$alumacc.cc:474:replace_alu$16163.C[9] O=$abc$44715$auto$wreduce.cc:455:run$15912[9]
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:395|uart_mod.v:537|uart_mod.v:154|uart_mod.v:74|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/arith_map.v:62|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:56"
.param LUT_INIT 0110100110010110
.gate SB_CARRY CI=$auto$alumacc.cc:474:replace_alu$16163.C[9] CO=$auto$alumacc.cc:474:replace_alu$16163.C[10] I0=$false I1=common.pb.uart.rx_mod.symclk.count[9]
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:395|uart_mod.v:537|uart_mod.v:154|uart_mod.v:74|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/arith_map.v:56"
.gate SB_LUT4 I0=$false I1=common.pb.uart.tx_mod.symclk.clks_per_sym_limited[1] I2=$false I3=$true O=$abc$44715$techmap\common.pb.uart.rx_mod.symclk.$sub$uart_mod.v:78$19_Y[0]
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:395|uart_mod.v:537|uart_mod.v:154|uart_mod.v:78|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/arith_map.v:62|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:56"
.param LUT_INIT 0110100110010110
.gate SB_LUT4 I0=$false I1=common.pb.uart.tx_mod.symclk.clks_per_sym_limited[11] I2=$true I3=$auto$alumacc.cc:474:replace_alu$16166.C[10] O=$abc$44715$techmap\common.pb.uart.rx_mod.symclk.$sub$uart_mod.v:78$19_Y[10]
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:395|uart_mod.v:537|uart_mod.v:154|uart_mod.v:78|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/arith_map.v:62|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:56"
.param LUT_INIT 0110100110010110
.gate SB_CARRY CI=$auto$alumacc.cc:474:replace_alu$16166.C[10] CO=$auto$alumacc.cc:474:replace_alu$16166.C[11] I0=common.pb.uart.tx_mod.symclk.clks_per_sym_limited[11] I1=$true
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:395|uart_mod.v:537|uart_mod.v:154|uart_mod.v:78|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/arith_map.v:56"
.gate SB_LUT4 I0=$false I1=common.pb.uart.tx_mod.symclk.clks_per_sym_limited[12] I2=$true I3=$auto$alumacc.cc:474:replace_alu$16166.C[11] O=$abc$44715$techmap\common.pb.uart.rx_mod.symclk.$sub$uart_mod.v:78$19_Y[11]
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:395|uart_mod.v:537|uart_mod.v:154|uart_mod.v:78|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/arith_map.v:62|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:56"
.param LUT_INIT 0110100110010110
.gate SB_CARRY CI=$auto$alumacc.cc:474:replace_alu$16166.C[11] CO=$auto$alumacc.cc:474:replace_alu$16166.C[12] I0=common.pb.uart.tx_mod.symclk.clks_per_sym_limited[12] I1=$true
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:395|uart_mod.v:537|uart_mod.v:154|uart_mod.v:78|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/arith_map.v:56"
.gate SB_LUT4 I0=$false I1=common.pb.uart.tx_mod.symclk.clks_per_sym_limited[13] I2=$true I3=$auto$alumacc.cc:474:replace_alu$16166.C[12] O=$abc$44715$techmap\common.pb.uart.rx_mod.symclk.$sub$uart_mod.v:78$19_Y[12]
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:395|uart_mod.v:537|uart_mod.v:154|uart_mod.v:78|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/arith_map.v:62|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:56"
.param LUT_INIT 0110100110010110
.gate SB_CARRY CI=$auto$alumacc.cc:474:replace_alu$16166.C[12] CO=$auto$alumacc.cc:474:replace_alu$16166.C[13] I0=common.pb.uart.tx_mod.symclk.clks_per_sym_limited[13] I1=$true
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:395|uart_mod.v:537|uart_mod.v:154|uart_mod.v:78|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/arith_map.v:56"
.gate SB_LUT4 I0=$false I1=common.pb.uart.tx_mod.symclk.clks_per_sym_limited[14] I2=$true I3=$auto$alumacc.cc:474:replace_alu$16166.C[13] O=$abc$44715$techmap\common.pb.uart.rx_mod.symclk.$sub$uart_mod.v:78$19_Y[13]
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:395|uart_mod.v:537|uart_mod.v:154|uart_mod.v:78|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/arith_map.v:62|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:56"
.param LUT_INIT 0110100110010110
.gate SB_CARRY CI=$auto$alumacc.cc:474:replace_alu$16166.C[13] CO=$auto$alumacc.cc:474:replace_alu$16166.C[14] I0=common.pb.uart.tx_mod.symclk.clks_per_sym_limited[14] I1=$true
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:395|uart_mod.v:537|uart_mod.v:154|uart_mod.v:78|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/arith_map.v:56"
.gate SB_LUT4 I0=$false I1=common.pb.uart.tx_mod.symclk.clks_per_sym_limited[15] I2=$true I3=$auto$alumacc.cc:474:replace_alu$16166.C[14] O=$abc$44715$techmap\common.pb.uart.rx_mod.symclk.$sub$uart_mod.v:78$19_Y[14]
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:395|uart_mod.v:537|uart_mod.v:154|uart_mod.v:78|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/arith_map.v:62|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:56"
.param LUT_INIT 0110100110010110
.gate SB_CARRY CI=$auto$alumacc.cc:474:replace_alu$16166.C[14] CO=$auto$alumacc.cc:474:replace_alu$16166.C[15] I0=common.pb.uart.tx_mod.symclk.clks_per_sym_limited[15] I1=$true
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:395|uart_mod.v:537|uart_mod.v:154|uart_mod.v:78|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/arith_map.v:56"
.gate SB_LUT4 I0=$false I1=common.pb.uart.tx_mod.symclk.clks_per_sym_limited[16] I2=$true I3=$auto$alumacc.cc:474:replace_alu$16166.C[15] O=$abc$44715$techmap\common.pb.uart.rx_mod.symclk.$sub$uart_mod.v:78$19_Y[15]
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:395|uart_mod.v:537|uart_mod.v:154|uart_mod.v:78|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/arith_map.v:62|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:56"
.param LUT_INIT 0110100110010110
.gate SB_CARRY CI=$auto$alumacc.cc:474:replace_alu$16166.C[15] CO=$auto$alumacc.cc:474:replace_alu$16166.C[16] I0=common.pb.uart.tx_mod.symclk.clks_per_sym_limited[16] I1=$true
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:395|uart_mod.v:537|uart_mod.v:154|uart_mod.v:78|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/arith_map.v:56"
.gate SB_LUT4 I0=$false I1=common.pb.uart.tx_mod.symclk.clks_per_sym_limited[17] I2=$true I3=$auto$alumacc.cc:474:replace_alu$16166.C[16] O=$abc$44715$techmap\common.pb.uart.rx_mod.symclk.$sub$uart_mod.v:78$19_Y[16]
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:395|uart_mod.v:537|uart_mod.v:154|uart_mod.v:78|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/arith_map.v:62|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:56"
.param LUT_INIT 0110100110010110
.gate SB_CARRY CI=$auto$alumacc.cc:474:replace_alu$16166.C[16] CO=$auto$alumacc.cc:474:replace_alu$16166.C[17] I0=common.pb.uart.tx_mod.symclk.clks_per_sym_limited[17] I1=$true
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:395|uart_mod.v:537|uart_mod.v:154|uart_mod.v:78|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/arith_map.v:56"
.gate SB_LUT4 I0=$false I1=common.pb.uart.tx_mod.symclk.clks_per_sym_limited[18] I2=$true I3=$auto$alumacc.cc:474:replace_alu$16166.C[17] O=$abc$44715$techmap\common.pb.uart.rx_mod.symclk.$sub$uart_mod.v:78$19_Y[17]
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:395|uart_mod.v:537|uart_mod.v:154|uart_mod.v:78|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/arith_map.v:62|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:56"
.param LUT_INIT 0110100110010110
.gate SB_CARRY CI=$auto$alumacc.cc:474:replace_alu$16166.C[17] CO=$auto$alumacc.cc:474:replace_alu$16166.C[18] I0=common.pb.uart.tx_mod.symclk.clks_per_sym_limited[18] I1=$true
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:395|uart_mod.v:537|uart_mod.v:154|uart_mod.v:78|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/arith_map.v:56"
.gate SB_LUT4 I0=$false I1=common.pb.uart.tx_mod.symclk.clks_per_sym_limited[19] I2=$true I3=$auto$alumacc.cc:474:replace_alu$16166.C[18] O=$abc$44715$techmap\common.pb.uart.rx_mod.symclk.$sub$uart_mod.v:78$19_Y[18]
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:395|uart_mod.v:537|uart_mod.v:154|uart_mod.v:78|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/arith_map.v:62|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:56"
.param LUT_INIT 0110100110010110
.gate SB_CARRY CI=$auto$alumacc.cc:474:replace_alu$16166.C[18] CO=$auto$alumacc.cc:474:replace_alu$16166.C[19] I0=common.pb.uart.tx_mod.symclk.clks_per_sym_limited[19] I1=$true
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:395|uart_mod.v:537|uart_mod.v:154|uart_mod.v:78|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/arith_map.v:56"
.gate SB_LUT4 I0=$false I1=common.pb.uart.tx_mod.symclk.clks_per_sym_limited[20] I2=$true I3=$auto$alumacc.cc:474:replace_alu$16166.C[19] O=$abc$44715$techmap\common.pb.uart.rx_mod.symclk.$sub$uart_mod.v:78$19_Y[19]
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:395|uart_mod.v:537|uart_mod.v:154|uart_mod.v:78|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/arith_map.v:62|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:56"
.param LUT_INIT 0110100110010110
.gate SB_CARRY CI=$auto$alumacc.cc:474:replace_alu$16166.C[19] CO=$auto$alumacc.cc:474:replace_alu$16166.C[20] I0=common.pb.uart.tx_mod.symclk.clks_per_sym_limited[20] I1=$true
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:395|uart_mod.v:537|uart_mod.v:154|uart_mod.v:78|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/arith_map.v:56"
.gate SB_CARRY CI=common.pb.uart.tx_mod.symclk.clks_per_sym_limited[1] CO=$auto$alumacc.cc:474:replace_alu$16166.C[2] I0=common.pb.uart.tx_mod.symclk.clks_per_sym_limited[2] I1=$true
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:395|uart_mod.v:537|uart_mod.v:154|uart_mod.v:78|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/arith_map.v:56"
.gate SB_LUT4 I0=$false I1=common.pb.uart.tx_mod.symclk.clks_per_sym_limited[21] I2=$true I3=$auto$alumacc.cc:474:replace_alu$16166.C[20] O=$abc$44715$techmap\common.pb.uart.rx_mod.symclk.$sub$uart_mod.v:78$19_Y[20]
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:395|uart_mod.v:537|uart_mod.v:154|uart_mod.v:78|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/arith_map.v:62|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:56"
.param LUT_INIT 0110100110010110
.gate SB_CARRY CI=$auto$alumacc.cc:474:replace_alu$16166.C[20] CO=$auto$alumacc.cc:474:replace_alu$16166.C[21] I0=common.pb.uart.tx_mod.symclk.clks_per_sym_limited[21] I1=$true
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:395|uart_mod.v:537|uart_mod.v:154|uart_mod.v:78|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/arith_map.v:56"
.gate SB_LUT4 I0=$false I1=common.pb.uart.tx_mod.symclk.clks_per_sym_limited[22] I2=$true I3=$auto$alumacc.cc:474:replace_alu$16166.C[21] O=$abc$44715$techmap\common.pb.uart.rx_mod.symclk.$sub$uart_mod.v:78$19_Y[21]
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:395|uart_mod.v:537|uart_mod.v:154|uart_mod.v:78|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/arith_map.v:62|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:56"
.param LUT_INIT 0110100110010110
.gate SB_CARRY CI=$auto$alumacc.cc:474:replace_alu$16166.C[21] CO=$auto$alumacc.cc:474:replace_alu$16166.C[22] I0=common.pb.uart.tx_mod.symclk.clks_per_sym_limited[22] I1=$true
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:395|uart_mod.v:537|uart_mod.v:154|uart_mod.v:78|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/arith_map.v:56"
.gate SB_LUT4 I0=$false I1=common.pb.uart.tx_mod.symclk.clks_per_sym_limited[23] I2=$true I3=$auto$alumacc.cc:474:replace_alu$16166.C[22] O=$abc$44715$techmap\common.pb.uart.rx_mod.symclk.$sub$uart_mod.v:78$19_Y[22]
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:395|uart_mod.v:537|uart_mod.v:154|uart_mod.v:78|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/arith_map.v:62|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:56"
.param LUT_INIT 0110100110010110
.gate SB_CARRY CI=$auto$alumacc.cc:474:replace_alu$16166.C[22] CO=$abc$44715$auto$alumacc.cc:474:replace_alu$16166.C[31] I0=common.pb.uart.tx_mod.symclk.clks_per_sym_limited[23] I1=$true
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:395|uart_mod.v:537|uart_mod.v:154|uart_mod.v:78|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/arith_map.v:56"
.gate SB_LUT4 I0=$false I1=$false I2=$true I3=$abc$44715$auto$alumacc.cc:474:replace_alu$16166.C[31] O=$abc$44715$techmap\common.pb.uart.rx_mod.symclk.$sub$uart_mod.v:78$19_Y[23]
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:395|uart_mod.v:537|uart_mod.v:154|uart_mod.v:78|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/arith_map.v:62|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:56"
.param LUT_INIT 0110100110010110
.gate SB_LUT4 I0=$false I1=common.pb.uart.tx_mod.symclk.clks_per_sym_limited[3] I2=$true I3=$auto$alumacc.cc:474:replace_alu$16166.C[2] O=$abc$44715$techmap\common.pb.uart.rx_mod.symclk.$sub$uart_mod.v:78$19_Y[2]
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:395|uart_mod.v:537|uart_mod.v:154|uart_mod.v:78|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/arith_map.v:62|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:56"
.param LUT_INIT 0110100110010110
.gate SB_CARRY CI=$auto$alumacc.cc:474:replace_alu$16166.C[2] CO=$auto$alumacc.cc:474:replace_alu$16166.C[3] I0=common.pb.uart.tx_mod.symclk.clks_per_sym_limited[3] I1=$true
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:395|uart_mod.v:537|uart_mod.v:154|uart_mod.v:78|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/arith_map.v:56"
.gate SB_LUT4 I0=$false I1=common.pb.uart.tx_mod.symclk.clks_per_sym_limited[4] I2=$true I3=$auto$alumacc.cc:474:replace_alu$16166.C[3] O=$abc$44715$techmap\common.pb.uart.rx_mod.symclk.$sub$uart_mod.v:78$19_Y[3]
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:395|uart_mod.v:537|uart_mod.v:154|uart_mod.v:78|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/arith_map.v:62|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:56"
.param LUT_INIT 0110100110010110
.gate SB_CARRY CI=$auto$alumacc.cc:474:replace_alu$16166.C[3] CO=$auto$alumacc.cc:474:replace_alu$16166.C[4] I0=common.pb.uart.tx_mod.symclk.clks_per_sym_limited[4] I1=$true
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:395|uart_mod.v:537|uart_mod.v:154|uart_mod.v:78|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/arith_map.v:56"
.gate SB_LUT4 I0=$false I1=common.pb.uart.tx_mod.symclk.clks_per_sym_limited[5] I2=$true I3=$auto$alumacc.cc:474:replace_alu$16166.C[4] O=$abc$44715$techmap\common.pb.uart.rx_mod.symclk.$sub$uart_mod.v:78$19_Y[4]
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:395|uart_mod.v:537|uart_mod.v:154|uart_mod.v:78|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/arith_map.v:62|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:56"
.param LUT_INIT 0110100110010110
.gate SB_CARRY CI=$auto$alumacc.cc:474:replace_alu$16166.C[4] CO=$auto$alumacc.cc:474:replace_alu$16166.C[5] I0=common.pb.uart.tx_mod.symclk.clks_per_sym_limited[5] I1=$true
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:395|uart_mod.v:537|uart_mod.v:154|uart_mod.v:78|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/arith_map.v:56"
.gate SB_LUT4 I0=$false I1=common.pb.uart.tx_mod.symclk.clks_per_sym_limited[6] I2=$true I3=$auto$alumacc.cc:474:replace_alu$16166.C[5] O=$abc$44715$techmap\common.pb.uart.rx_mod.symclk.$sub$uart_mod.v:78$19_Y[5]
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:395|uart_mod.v:537|uart_mod.v:154|uart_mod.v:78|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/arith_map.v:62|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:56"
.param LUT_INIT 0110100110010110
.gate SB_CARRY CI=$auto$alumacc.cc:474:replace_alu$16166.C[5] CO=$auto$alumacc.cc:474:replace_alu$16166.C[6] I0=common.pb.uart.tx_mod.symclk.clks_per_sym_limited[6] I1=$true
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:395|uart_mod.v:537|uart_mod.v:154|uart_mod.v:78|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/arith_map.v:56"
.gate SB_LUT4 I0=$false I1=common.pb.uart.tx_mod.symclk.clks_per_sym_limited[7] I2=$true I3=$auto$alumacc.cc:474:replace_alu$16166.C[6] O=$abc$44715$techmap\common.pb.uart.rx_mod.symclk.$sub$uart_mod.v:78$19_Y[6]
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:395|uart_mod.v:537|uart_mod.v:154|uart_mod.v:78|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/arith_map.v:62|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:56"
.param LUT_INIT 0110100110010110
.gate SB_CARRY CI=$auto$alumacc.cc:474:replace_alu$16166.C[6] CO=$auto$alumacc.cc:474:replace_alu$16166.C[7] I0=common.pb.uart.tx_mod.symclk.clks_per_sym_limited[7] I1=$true
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:395|uart_mod.v:537|uart_mod.v:154|uart_mod.v:78|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/arith_map.v:56"
.gate SB_LUT4 I0=$false I1=common.pb.uart.tx_mod.symclk.clks_per_sym_limited[8] I2=$true I3=$auto$alumacc.cc:474:replace_alu$16166.C[7] O=$abc$44715$techmap\common.pb.uart.rx_mod.symclk.$sub$uart_mod.v:78$19_Y[7]
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:395|uart_mod.v:537|uart_mod.v:154|uart_mod.v:78|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/arith_map.v:62|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:56"
.param LUT_INIT 0110100110010110
.gate SB_CARRY CI=$auto$alumacc.cc:474:replace_alu$16166.C[7] CO=$auto$alumacc.cc:474:replace_alu$16166.C[8] I0=common.pb.uart.tx_mod.symclk.clks_per_sym_limited[8] I1=$true
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:395|uart_mod.v:537|uart_mod.v:154|uart_mod.v:78|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/arith_map.v:56"
.gate SB_LUT4 I0=$false I1=common.pb.uart.tx_mod.symclk.clks_per_sym_limited[9] I2=$true I3=$auto$alumacc.cc:474:replace_alu$16166.C[8] O=$abc$44715$techmap\common.pb.uart.rx_mod.symclk.$sub$uart_mod.v:78$19_Y[8]
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:395|uart_mod.v:537|uart_mod.v:154|uart_mod.v:78|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/arith_map.v:62|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:56"
.param LUT_INIT 0110100110010110
.gate SB_CARRY CI=$auto$alumacc.cc:474:replace_alu$16166.C[8] CO=$auto$alumacc.cc:474:replace_alu$16166.C[9] I0=common.pb.uart.tx_mod.symclk.clks_per_sym_limited[9] I1=$true
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:395|uart_mod.v:537|uart_mod.v:154|uart_mod.v:78|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/arith_map.v:56"
.gate SB_LUT4 I0=$false I1=common.pb.uart.tx_mod.symclk.clks_per_sym_limited[10] I2=$true I3=$auto$alumacc.cc:474:replace_alu$16166.C[9] O=$abc$44715$techmap\common.pb.uart.rx_mod.symclk.$sub$uart_mod.v:78$19_Y[9]
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:395|uart_mod.v:537|uart_mod.v:154|uart_mod.v:78|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/arith_map.v:62|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:56"
.param LUT_INIT 0110100110010110
.gate SB_CARRY CI=$auto$alumacc.cc:474:replace_alu$16166.C[9] CO=$auto$alumacc.cc:474:replace_alu$16166.C[10] I0=common.pb.uart.tx_mod.symclk.clks_per_sym_limited[10] I1=$true
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:395|uart_mod.v:537|uart_mod.v:154|uart_mod.v:78|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/arith_map.v:56"
.gate SB_LUT4 I0=$false I1=common.pb.uart.rx_mod.symclk.clks_per_sym_limited I2=$false I3=$true O=$abc$44715$auto$alumacc.cc:474:replace_alu$15981.B_buf[0]
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:395|uart_mod.v:537|uart_mod.v:154|uart_mod.v:83|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/arith_map.v:62|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:56"
.param LUT_INIT 0110100110010110
.gate SB_LUT4 I0=$false I1=common.pb.uart.tx_mod.symclk.clks_per_sym_limited[10] I2=$true I3=$auto$alumacc.cc:474:replace_alu$16169.C[10] O=$abc$44715$auto$alumacc.cc:474:replace_alu$15981.B_buf[10]
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:395|uart_mod.v:537|uart_mod.v:154|uart_mod.v:83|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/arith_map.v:62|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:56"
.param LUT_INIT 0110100110010110
.gate SB_CARRY CI=$auto$alumacc.cc:474:replace_alu$16169.C[10] CO=$auto$alumacc.cc:474:replace_alu$16169.C[11] I0=common.pb.uart.tx_mod.symclk.clks_per_sym_limited[10] I1=$true
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:395|uart_mod.v:537|uart_mod.v:154|uart_mod.v:83|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/arith_map.v:56"
.gate SB_LUT4 I0=$false I1=common.pb.uart.tx_mod.symclk.clks_per_sym_limited[11] I2=$true I3=$auto$alumacc.cc:474:replace_alu$16169.C[11] O=$abc$44715$auto$alumacc.cc:474:replace_alu$15981.B_buf[11]
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:395|uart_mod.v:537|uart_mod.v:154|uart_mod.v:83|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/arith_map.v:62|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:56"
.param LUT_INIT 0110100110010110
.gate SB_CARRY CI=$auto$alumacc.cc:474:replace_alu$16169.C[11] CO=$auto$alumacc.cc:474:replace_alu$16169.C[12] I0=common.pb.uart.tx_mod.symclk.clks_per_sym_limited[11] I1=$true
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:395|uart_mod.v:537|uart_mod.v:154|uart_mod.v:83|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/arith_map.v:56"
.gate SB_LUT4 I0=$false I1=common.pb.uart.tx_mod.symclk.clks_per_sym_limited[12] I2=$true I3=$auto$alumacc.cc:474:replace_alu$16169.C[12] O=$abc$44715$auto$alumacc.cc:474:replace_alu$15981.B_buf[12]
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:395|uart_mod.v:537|uart_mod.v:154|uart_mod.v:83|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/arith_map.v:62|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:56"
.param LUT_INIT 0110100110010110
.gate SB_CARRY CI=$auto$alumacc.cc:474:replace_alu$16169.C[12] CO=$auto$alumacc.cc:474:replace_alu$16169.C[13] I0=common.pb.uart.tx_mod.symclk.clks_per_sym_limited[12] I1=$true
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:395|uart_mod.v:537|uart_mod.v:154|uart_mod.v:83|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/arith_map.v:56"
.gate SB_LUT4 I0=$false I1=common.pb.uart.tx_mod.symclk.clks_per_sym_limited[13] I2=$true I3=$auto$alumacc.cc:474:replace_alu$16169.C[13] O=$abc$44715$auto$alumacc.cc:474:replace_alu$15981.B_buf[13]
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:395|uart_mod.v:537|uart_mod.v:154|uart_mod.v:83|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/arith_map.v:62|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:56"
.param LUT_INIT 0110100110010110
.gate SB_CARRY CI=$auto$alumacc.cc:474:replace_alu$16169.C[13] CO=$auto$alumacc.cc:474:replace_alu$16169.C[14] I0=common.pb.uart.tx_mod.symclk.clks_per_sym_limited[13] I1=$true
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:395|uart_mod.v:537|uart_mod.v:154|uart_mod.v:83|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/arith_map.v:56"
.gate SB_LUT4 I0=$false I1=common.pb.uart.tx_mod.symclk.clks_per_sym_limited[14] I2=$true I3=$auto$alumacc.cc:474:replace_alu$16169.C[14] O=$abc$44715$auto$alumacc.cc:474:replace_alu$15981.B_buf[14]
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:395|uart_mod.v:537|uart_mod.v:154|uart_mod.v:83|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/arith_map.v:62|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:56"
.param LUT_INIT 0110100110010110
.gate SB_CARRY CI=$auto$alumacc.cc:474:replace_alu$16169.C[14] CO=$auto$alumacc.cc:474:replace_alu$16169.C[15] I0=common.pb.uart.tx_mod.symclk.clks_per_sym_limited[14] I1=$true
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:395|uart_mod.v:537|uart_mod.v:154|uart_mod.v:83|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/arith_map.v:56"
.gate SB_LUT4 I0=$false I1=common.pb.uart.tx_mod.symclk.clks_per_sym_limited[15] I2=$true I3=$auto$alumacc.cc:474:replace_alu$16169.C[15] O=$abc$44715$auto$alumacc.cc:474:replace_alu$15981.B_buf[15]
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:395|uart_mod.v:537|uart_mod.v:154|uart_mod.v:83|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/arith_map.v:62|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:56"
.param LUT_INIT 0110100110010110
.gate SB_CARRY CI=$auto$alumacc.cc:474:replace_alu$16169.C[15] CO=$auto$alumacc.cc:474:replace_alu$16169.C[16] I0=common.pb.uart.tx_mod.symclk.clks_per_sym_limited[15] I1=$true
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:395|uart_mod.v:537|uart_mod.v:154|uart_mod.v:83|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/arith_map.v:56"
.gate SB_LUT4 I0=$false I1=common.pb.uart.tx_mod.symclk.clks_per_sym_limited[16] I2=$true I3=$auto$alumacc.cc:474:replace_alu$16169.C[16] O=$abc$44715$auto$alumacc.cc:474:replace_alu$15981.B_buf[16]
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:395|uart_mod.v:537|uart_mod.v:154|uart_mod.v:83|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/arith_map.v:62|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:56"
.param LUT_INIT 0110100110010110
.gate SB_CARRY CI=$auto$alumacc.cc:474:replace_alu$16169.C[16] CO=$auto$alumacc.cc:474:replace_alu$16169.C[17] I0=common.pb.uart.tx_mod.symclk.clks_per_sym_limited[16] I1=$true
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:395|uart_mod.v:537|uart_mod.v:154|uart_mod.v:83|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/arith_map.v:56"
.gate SB_LUT4 I0=$false I1=common.pb.uart.tx_mod.symclk.clks_per_sym_limited[17] I2=$true I3=$auto$alumacc.cc:474:replace_alu$16169.C[17] O=$abc$44715$auto$alumacc.cc:474:replace_alu$15981.B_buf[17]
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:395|uart_mod.v:537|uart_mod.v:154|uart_mod.v:83|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/arith_map.v:62|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:56"
.param LUT_INIT 0110100110010110
.gate SB_CARRY CI=$auto$alumacc.cc:474:replace_alu$16169.C[17] CO=$auto$alumacc.cc:474:replace_alu$16169.C[18] I0=common.pb.uart.tx_mod.symclk.clks_per_sym_limited[17] I1=$true
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:395|uart_mod.v:537|uart_mod.v:154|uart_mod.v:83|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/arith_map.v:56"
.gate SB_LUT4 I0=$false I1=common.pb.uart.tx_mod.symclk.clks_per_sym_limited[18] I2=$true I3=$auto$alumacc.cc:474:replace_alu$16169.C[18] O=$abc$44715$auto$alumacc.cc:474:replace_alu$15981.B_buf[18]
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:395|uart_mod.v:537|uart_mod.v:154|uart_mod.v:83|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/arith_map.v:62|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:56"
.param LUT_INIT 0110100110010110
.gate SB_CARRY CI=$auto$alumacc.cc:474:replace_alu$16169.C[18] CO=$auto$alumacc.cc:474:replace_alu$16169.C[19] I0=common.pb.uart.tx_mod.symclk.clks_per_sym_limited[18] I1=$true
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:395|uart_mod.v:537|uart_mod.v:154|uart_mod.v:83|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/arith_map.v:56"
.gate SB_LUT4 I0=$false I1=common.pb.uart.tx_mod.symclk.clks_per_sym_limited[19] I2=$true I3=$auto$alumacc.cc:474:replace_alu$16169.C[19] O=$abc$44715$auto$alumacc.cc:474:replace_alu$15981.B_buf[19]
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:395|uart_mod.v:537|uart_mod.v:154|uart_mod.v:83|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/arith_map.v:62|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:56"
.param LUT_INIT 0110100110010110
.gate SB_CARRY CI=$auto$alumacc.cc:474:replace_alu$16169.C[19] CO=$auto$alumacc.cc:474:replace_alu$16169.C[20] I0=common.pb.uart.tx_mod.symclk.clks_per_sym_limited[19] I1=$true
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:395|uart_mod.v:537|uart_mod.v:154|uart_mod.v:83|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/arith_map.v:56"
.gate SB_CARRY CI=common.pb.uart.rx_mod.symclk.clks_per_sym_limited CO=$auto$alumacc.cc:474:replace_alu$16169.C[2] I0=common.pb.uart.tx_mod.symclk.clks_per_sym_limited[1] I1=$true
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:395|uart_mod.v:537|uart_mod.v:154|uart_mod.v:83|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/arith_map.v:56"
.gate SB_LUT4 I0=$false I1=common.pb.uart.tx_mod.symclk.clks_per_sym_limited[20] I2=$true I3=$auto$alumacc.cc:474:replace_alu$16169.C[20] O=$abc$44715$auto$alumacc.cc:474:replace_alu$15981.B_buf[20]
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:395|uart_mod.v:537|uart_mod.v:154|uart_mod.v:83|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/arith_map.v:62|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:56"
.param LUT_INIT 0110100110010110
.gate SB_CARRY CI=$auto$alumacc.cc:474:replace_alu$16169.C[20] CO=$auto$alumacc.cc:474:replace_alu$16169.C[21] I0=common.pb.uart.tx_mod.symclk.clks_per_sym_limited[20] I1=$true
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:395|uart_mod.v:537|uart_mod.v:154|uart_mod.v:83|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/arith_map.v:56"
.gate SB_LUT4 I0=$false I1=common.pb.uart.tx_mod.symclk.clks_per_sym_limited[21] I2=$true I3=$auto$alumacc.cc:474:replace_alu$16169.C[21] O=$abc$44715$auto$alumacc.cc:474:replace_alu$15981.B_buf[21]
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:395|uart_mod.v:537|uart_mod.v:154|uart_mod.v:83|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/arith_map.v:62|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:56"
.param LUT_INIT 0110100110010110
.gate SB_CARRY CI=$auto$alumacc.cc:474:replace_alu$16169.C[21] CO=$auto$alumacc.cc:474:replace_alu$16169.C[22] I0=common.pb.uart.tx_mod.symclk.clks_per_sym_limited[21] I1=$true
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:395|uart_mod.v:537|uart_mod.v:154|uart_mod.v:83|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/arith_map.v:56"
.gate SB_LUT4 I0=$false I1=common.pb.uart.tx_mod.symclk.clks_per_sym_limited[22] I2=$true I3=$auto$alumacc.cc:474:replace_alu$16169.C[22] O=$abc$44715$auto$alumacc.cc:474:replace_alu$15981.B_buf[22]
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:395|uart_mod.v:537|uart_mod.v:154|uart_mod.v:83|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/arith_map.v:62|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:56"
.param LUT_INIT 0110100110010110
.gate SB_CARRY CI=$auto$alumacc.cc:474:replace_alu$16169.C[22] CO=$auto$alumacc.cc:474:replace_alu$16169.C[23] I0=common.pb.uart.tx_mod.symclk.clks_per_sym_limited[22] I1=$true
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:395|uart_mod.v:537|uart_mod.v:154|uart_mod.v:83|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/arith_map.v:56"
.gate SB_LUT4 I0=$false I1=common.pb.uart.tx_mod.symclk.clks_per_sym_limited[23] I2=$true I3=$auto$alumacc.cc:474:replace_alu$16169.C[23] O=$abc$44715$auto$alumacc.cc:474:replace_alu$15981.B_buf[23]
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:395|uart_mod.v:537|uart_mod.v:154|uart_mod.v:83|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/arith_map.v:62|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:56"
.param LUT_INIT 0110100110010110
.gate SB_CARRY CI=$auto$alumacc.cc:474:replace_alu$16169.C[23] CO=$abc$44715$auto$alumacc.cc:474:replace_alu$15981.BB[31] I0=common.pb.uart.tx_mod.symclk.clks_per_sym_limited[23] I1=$true
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:395|uart_mod.v:537|uart_mod.v:154|uart_mod.v:83|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/arith_map.v:56"
.gate SB_LUT4 I0=$false I1=$false I2=$true I3=$abc$44715$auto$alumacc.cc:474:replace_alu$15981.BB[31] O=$abc$44715$auto$alumacc.cc:474:replace_alu$15981.B_buf[24]
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:395|uart_mod.v:537|uart_mod.v:154|uart_mod.v:83|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/arith_map.v:62|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:56"
.param LUT_INIT 0110100110010110
.gate SB_LUT4 I0=$false I1=common.pb.uart.tx_mod.symclk.clks_per_sym_limited[2] I2=$true I3=$auto$alumacc.cc:474:replace_alu$16169.C[2] O=$abc$44715$auto$alumacc.cc:474:replace_alu$15981.B_buf[2]
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:395|uart_mod.v:537|uart_mod.v:154|uart_mod.v:83|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/arith_map.v:62|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:56"
.param LUT_INIT 0110100110010110
.gate SB_CARRY CI=$auto$alumacc.cc:474:replace_alu$16169.C[2] CO=$auto$alumacc.cc:474:replace_alu$16169.C[3] I0=common.pb.uart.tx_mod.symclk.clks_per_sym_limited[2] I1=$true
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:395|uart_mod.v:537|uart_mod.v:154|uart_mod.v:83|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/arith_map.v:56"
.gate SB_LUT4 I0=$false I1=common.pb.uart.tx_mod.symclk.clks_per_sym_limited[3] I2=$true I3=$auto$alumacc.cc:474:replace_alu$16169.C[3] O=$abc$44715$auto$alumacc.cc:474:replace_alu$15981.B_buf[3]
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:395|uart_mod.v:537|uart_mod.v:154|uart_mod.v:83|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/arith_map.v:62|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:56"
.param LUT_INIT 0110100110010110
.gate SB_CARRY CI=$auto$alumacc.cc:474:replace_alu$16169.C[3] CO=$auto$alumacc.cc:474:replace_alu$16169.C[4] I0=common.pb.uart.tx_mod.symclk.clks_per_sym_limited[3] I1=$true
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:395|uart_mod.v:537|uart_mod.v:154|uart_mod.v:83|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/arith_map.v:56"
.gate SB_LUT4 I0=$false I1=common.pb.uart.tx_mod.symclk.clks_per_sym_limited[4] I2=$true I3=$auto$alumacc.cc:474:replace_alu$16169.C[4] O=$abc$44715$auto$alumacc.cc:474:replace_alu$15981.B_buf[4]
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:395|uart_mod.v:537|uart_mod.v:154|uart_mod.v:83|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/arith_map.v:62|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:56"
.param LUT_INIT 0110100110010110
.gate SB_CARRY CI=$auto$alumacc.cc:474:replace_alu$16169.C[4] CO=$auto$alumacc.cc:474:replace_alu$16169.C[5] I0=common.pb.uart.tx_mod.symclk.clks_per_sym_limited[4] I1=$true
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:395|uart_mod.v:537|uart_mod.v:154|uart_mod.v:83|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/arith_map.v:56"
.gate SB_LUT4 I0=$false I1=common.pb.uart.tx_mod.symclk.clks_per_sym_limited[5] I2=$true I3=$auto$alumacc.cc:474:replace_alu$16169.C[5] O=$abc$44715$auto$alumacc.cc:474:replace_alu$15981.B_buf[5]
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:395|uart_mod.v:537|uart_mod.v:154|uart_mod.v:83|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/arith_map.v:62|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:56"
.param LUT_INIT 0110100110010110
.gate SB_CARRY CI=$auto$alumacc.cc:474:replace_alu$16169.C[5] CO=$auto$alumacc.cc:474:replace_alu$16169.C[6] I0=common.pb.uart.tx_mod.symclk.clks_per_sym_limited[5] I1=$true
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:395|uart_mod.v:537|uart_mod.v:154|uart_mod.v:83|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/arith_map.v:56"
.gate SB_LUT4 I0=$false I1=common.pb.uart.tx_mod.symclk.clks_per_sym_limited[6] I2=$true I3=$auto$alumacc.cc:474:replace_alu$16169.C[6] O=$abc$44715$auto$alumacc.cc:474:replace_alu$15981.B_buf[6]
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:395|uart_mod.v:537|uart_mod.v:154|uart_mod.v:83|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/arith_map.v:62|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:56"
.param LUT_INIT 0110100110010110
.gate SB_CARRY CI=$auto$alumacc.cc:474:replace_alu$16169.C[6] CO=$auto$alumacc.cc:474:replace_alu$16169.C[7] I0=common.pb.uart.tx_mod.symclk.clks_per_sym_limited[6] I1=$true
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:395|uart_mod.v:537|uart_mod.v:154|uart_mod.v:83|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/arith_map.v:56"
.gate SB_LUT4 I0=$false I1=common.pb.uart.tx_mod.symclk.clks_per_sym_limited[7] I2=$true I3=$auto$alumacc.cc:474:replace_alu$16169.C[7] O=$abc$44715$auto$alumacc.cc:474:replace_alu$15981.B_buf[7]
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:395|uart_mod.v:537|uart_mod.v:154|uart_mod.v:83|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/arith_map.v:62|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:56"
.param LUT_INIT 0110100110010110
.gate SB_CARRY CI=$auto$alumacc.cc:474:replace_alu$16169.C[7] CO=$auto$alumacc.cc:474:replace_alu$16169.C[8] I0=common.pb.uart.tx_mod.symclk.clks_per_sym_limited[7] I1=$true
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:395|uart_mod.v:537|uart_mod.v:154|uart_mod.v:83|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/arith_map.v:56"
.gate SB_LUT4 I0=$false I1=common.pb.uart.tx_mod.symclk.clks_per_sym_limited[8] I2=$true I3=$auto$alumacc.cc:474:replace_alu$16169.C[8] O=$abc$44715$auto$alumacc.cc:474:replace_alu$15981.B_buf[8]
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:395|uart_mod.v:537|uart_mod.v:154|uart_mod.v:83|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/arith_map.v:62|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:56"
.param LUT_INIT 0110100110010110
.gate SB_CARRY CI=$auto$alumacc.cc:474:replace_alu$16169.C[8] CO=$auto$alumacc.cc:474:replace_alu$16169.C[9] I0=common.pb.uart.tx_mod.symclk.clks_per_sym_limited[8] I1=$true
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:395|uart_mod.v:537|uart_mod.v:154|uart_mod.v:83|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/arith_map.v:56"
.gate SB_LUT4 I0=$false I1=common.pb.uart.tx_mod.symclk.clks_per_sym_limited[9] I2=$true I3=$auto$alumacc.cc:474:replace_alu$16169.C[9] O=$abc$44715$auto$alumacc.cc:474:replace_alu$15981.B_buf[9]
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:395|uart_mod.v:537|uart_mod.v:154|uart_mod.v:83|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/arith_map.v:62|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:56"
.param LUT_INIT 0110100110010110
.gate SB_CARRY CI=$auto$alumacc.cc:474:replace_alu$16169.C[9] CO=$auto$alumacc.cc:474:replace_alu$16169.C[10] I0=common.pb.uart.tx_mod.symclk.clks_per_sym_limited[9] I1=$true
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:395|uart_mod.v:537|uart_mod.v:154|uart_mod.v:83|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/arith_map.v:56"
.gate SB_CARRY CI=common.pb.uart.tx_mod.sym_count[0] CO=$auto$alumacc.cc:474:replace_alu$16172.C[2] I0=$false I1=common.pb.uart.tx_mod.sym_count[1]
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:395|uart_mod.v:561|uart_mod.v:335|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/arith_map.v:56"
.gate SB_LUT4 I0=$false I1=$false I2=common.pb.uart.tx_mod.sym_count[2] I3=$auto$alumacc.cc:474:replace_alu$16172.C[2] O=$abc$44715$auto$wreduce.cc:455:run$15914[2]
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:395|uart_mod.v:561|uart_mod.v:335|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/arith_map.v:62|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:56"
.param LUT_INIT 0110100110010110
.gate SB_CARRY CI=$auto$alumacc.cc:474:replace_alu$16172.C[2] CO=$auto$alumacc.cc:474:replace_alu$16172.C[3] I0=$false I1=common.pb.uart.tx_mod.sym_count[2]
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:395|uart_mod.v:561|uart_mod.v:335|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/arith_map.v:56"
.gate SB_LUT4 I0=$abc$44715$new_n2095_ I1=$abc$44715$new_n2090_ I2=common.pb.uart.tx_mod.sym_count[3] I3=$auto$alumacc.cc:474:replace_alu$16172.C[3] O=$abc$44715$techmap\common.pb.uart.tx_mod.$procmux$15610_Y[3]
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:395|uart_mod.v:561|uart_mod.v:335|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/arith_map.v:62|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:56"
.param LUT_INIT 0011010101110000
.gate SB_LUT4 I0=$false I1=$false I2=common.pb.uart.tx_mod.symclk.count[10] I3=$auto$alumacc.cc:474:replace_alu$16178.C[10] O=$abc$44715$auto$wreduce.cc:455:run$15915[10]
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:395|uart_mod.v:561|uart_mod.v:300|uart_mod.v:74|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/arith_map.v:62|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:56"
.param LUT_INIT 0110100110010110
.gate SB_CARRY CI=$auto$alumacc.cc:474:replace_alu$16178.C[10] CO=$auto$alumacc.cc:474:replace_alu$16178.C[11] I0=$false I1=common.pb.uart.tx_mod.symclk.count[10]
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:395|uart_mod.v:561|uart_mod.v:300|uart_mod.v:74|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/arith_map.v:56"
.gate SB_LUT4 I0=$false I1=$false I2=common.pb.uart.tx_mod.symclk.count[11] I3=$auto$alumacc.cc:474:replace_alu$16178.C[11] O=$abc$44715$auto$wreduce.cc:455:run$15915[11]
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:395|uart_mod.v:561|uart_mod.v:300|uart_mod.v:74|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/arith_map.v:62|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:56"
.param LUT_INIT 0110100110010110
.gate SB_CARRY CI=$auto$alumacc.cc:474:replace_alu$16178.C[11] CO=$auto$alumacc.cc:474:replace_alu$16178.C[12] I0=$false I1=common.pb.uart.tx_mod.symclk.count[11]
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:395|uart_mod.v:561|uart_mod.v:300|uart_mod.v:74|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/arith_map.v:56"
.gate SB_LUT4 I0=$false I1=$false I2=common.pb.uart.tx_mod.symclk.count[12] I3=$auto$alumacc.cc:474:replace_alu$16178.C[12] O=$abc$44715$auto$wreduce.cc:455:run$15915[12]
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:395|uart_mod.v:561|uart_mod.v:300|uart_mod.v:74|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/arith_map.v:62|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:56"
.param LUT_INIT 0110100110010110
.gate SB_CARRY CI=$auto$alumacc.cc:474:replace_alu$16178.C[12] CO=$auto$alumacc.cc:474:replace_alu$16178.C[13] I0=$false I1=common.pb.uart.tx_mod.symclk.count[12]
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:395|uart_mod.v:561|uart_mod.v:300|uart_mod.v:74|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/arith_map.v:56"
.gate SB_LUT4 I0=$false I1=$false I2=common.pb.uart.tx_mod.symclk.count[13] I3=$auto$alumacc.cc:474:replace_alu$16178.C[13] O=$abc$44715$auto$wreduce.cc:455:run$15915[13]
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:395|uart_mod.v:561|uart_mod.v:300|uart_mod.v:74|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/arith_map.v:62|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:56"
.param LUT_INIT 0110100110010110
.gate SB_CARRY CI=$auto$alumacc.cc:474:replace_alu$16178.C[13] CO=$auto$alumacc.cc:474:replace_alu$16178.C[14] I0=$false I1=common.pb.uart.tx_mod.symclk.count[13]
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:395|uart_mod.v:561|uart_mod.v:300|uart_mod.v:74|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/arith_map.v:56"
.gate SB_LUT4 I0=$false I1=$false I2=common.pb.uart.tx_mod.symclk.count[14] I3=$auto$alumacc.cc:474:replace_alu$16178.C[14] O=$abc$44715$auto$wreduce.cc:455:run$15915[14]
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:395|uart_mod.v:561|uart_mod.v:300|uart_mod.v:74|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/arith_map.v:62|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:56"
.param LUT_INIT 0110100110010110
.gate SB_CARRY CI=$auto$alumacc.cc:474:replace_alu$16178.C[14] CO=$auto$alumacc.cc:474:replace_alu$16178.C[15] I0=$false I1=common.pb.uart.tx_mod.symclk.count[14]
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:395|uart_mod.v:561|uart_mod.v:300|uart_mod.v:74|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/arith_map.v:56"
.gate SB_LUT4 I0=$false I1=$false I2=common.pb.uart.tx_mod.symclk.count[15] I3=$auto$alumacc.cc:474:replace_alu$16178.C[15] O=$abc$44715$auto$wreduce.cc:455:run$15915[15]
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:395|uart_mod.v:561|uart_mod.v:300|uart_mod.v:74|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/arith_map.v:62|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:56"
.param LUT_INIT 0110100110010110
.gate SB_CARRY CI=$auto$alumacc.cc:474:replace_alu$16178.C[15] CO=$auto$alumacc.cc:474:replace_alu$16178.C[16] I0=$false I1=common.pb.uart.tx_mod.symclk.count[15]
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:395|uart_mod.v:561|uart_mod.v:300|uart_mod.v:74|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/arith_map.v:56"
.gate SB_LUT4 I0=$false I1=$false I2=common.pb.uart.tx_mod.symclk.count[16] I3=$auto$alumacc.cc:474:replace_alu$16178.C[16] O=$abc$44715$auto$wreduce.cc:455:run$15915[16]
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:395|uart_mod.v:561|uart_mod.v:300|uart_mod.v:74|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/arith_map.v:62|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:56"
.param LUT_INIT 0110100110010110
.gate SB_CARRY CI=$auto$alumacc.cc:474:replace_alu$16178.C[16] CO=$auto$alumacc.cc:474:replace_alu$16178.C[17] I0=$false I1=common.pb.uart.tx_mod.symclk.count[16]
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:395|uart_mod.v:561|uart_mod.v:300|uart_mod.v:74|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/arith_map.v:56"
.gate SB_LUT4 I0=$false I1=$false I2=common.pb.uart.tx_mod.symclk.count[17] I3=$auto$alumacc.cc:474:replace_alu$16178.C[17] O=$abc$44715$auto$wreduce.cc:455:run$15915[17]
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:395|uart_mod.v:561|uart_mod.v:300|uart_mod.v:74|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/arith_map.v:62|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:56"
.param LUT_INIT 0110100110010110
.gate SB_CARRY CI=$auto$alumacc.cc:474:replace_alu$16178.C[17] CO=$auto$alumacc.cc:474:replace_alu$16178.C[18] I0=$false I1=common.pb.uart.tx_mod.symclk.count[17]
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:395|uart_mod.v:561|uart_mod.v:300|uart_mod.v:74|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/arith_map.v:56"
.gate SB_LUT4 I0=$false I1=$false I2=common.pb.uart.tx_mod.symclk.count[18] I3=$auto$alumacc.cc:474:replace_alu$16178.C[18] O=$abc$44715$auto$wreduce.cc:455:run$15915[18]
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:395|uart_mod.v:561|uart_mod.v:300|uart_mod.v:74|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/arith_map.v:62|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:56"
.param LUT_INIT 0110100110010110
.gate SB_CARRY CI=$auto$alumacc.cc:474:replace_alu$16178.C[18] CO=$auto$alumacc.cc:474:replace_alu$16178.C[19] I0=$false I1=common.pb.uart.tx_mod.symclk.count[18]
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:395|uart_mod.v:561|uart_mod.v:300|uart_mod.v:74|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/arith_map.v:56"
.gate SB_LUT4 I0=$false I1=$false I2=common.pb.uart.tx_mod.symclk.count[19] I3=$auto$alumacc.cc:474:replace_alu$16178.C[19] O=$abc$44715$auto$wreduce.cc:455:run$15915[19]
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:395|uart_mod.v:561|uart_mod.v:300|uart_mod.v:74|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/arith_map.v:62|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:56"
.param LUT_INIT 0110100110010110
.gate SB_CARRY CI=$auto$alumacc.cc:474:replace_alu$16178.C[19] CO=$auto$alumacc.cc:474:replace_alu$16178.C[20] I0=$false I1=common.pb.uart.tx_mod.symclk.count[19]
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:395|uart_mod.v:561|uart_mod.v:300|uart_mod.v:74|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/arith_map.v:56"
.gate SB_CARRY CI=common.pb.uart.tx_mod.symclk.count[0] CO=$auto$alumacc.cc:474:replace_alu$16178.C[2] I0=$false I1=common.pb.uart.tx_mod.symclk.count[1]
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:395|uart_mod.v:561|uart_mod.v:300|uart_mod.v:74|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/arith_map.v:56"
.gate SB_LUT4 I0=$false I1=$false I2=common.pb.uart.tx_mod.symclk.count[20] I3=$auto$alumacc.cc:474:replace_alu$16178.C[20] O=$abc$44715$auto$wreduce.cc:455:run$15915[20]
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:395|uart_mod.v:561|uart_mod.v:300|uart_mod.v:74|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/arith_map.v:62|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:56"
.param LUT_INIT 0110100110010110
.gate SB_CARRY CI=$auto$alumacc.cc:474:replace_alu$16178.C[20] CO=$auto$alumacc.cc:474:replace_alu$16178.C[21] I0=$false I1=common.pb.uart.tx_mod.symclk.count[20]
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:395|uart_mod.v:561|uart_mod.v:300|uart_mod.v:74|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/arith_map.v:56"
.gate SB_LUT4 I0=$false I1=$false I2=common.pb.uart.tx_mod.symclk.count[21] I3=$auto$alumacc.cc:474:replace_alu$16178.C[21] O=$abc$44715$auto$wreduce.cc:455:run$15915[21]
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:395|uart_mod.v:561|uart_mod.v:300|uart_mod.v:74|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/arith_map.v:62|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:56"
.param LUT_INIT 0110100110010110
.gate SB_CARRY CI=$auto$alumacc.cc:474:replace_alu$16178.C[21] CO=$auto$alumacc.cc:474:replace_alu$16178.C[22] I0=$false I1=common.pb.uart.tx_mod.symclk.count[21]
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:395|uart_mod.v:561|uart_mod.v:300|uart_mod.v:74|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/arith_map.v:56"
.gate SB_LUT4 I0=$false I1=$false I2=common.pb.uart.tx_mod.symclk.count[22] I3=$auto$alumacc.cc:474:replace_alu$16178.C[22] O=$abc$44715$auto$wreduce.cc:455:run$15915[22]
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:395|uart_mod.v:561|uart_mod.v:300|uart_mod.v:74|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/arith_map.v:62|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:56"
.param LUT_INIT 0110100110010110
.gate SB_CARRY CI=$auto$alumacc.cc:474:replace_alu$16178.C[22] CO=$auto$alumacc.cc:474:replace_alu$16178.C[23] I0=$false I1=common.pb.uart.tx_mod.symclk.count[22]
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:395|uart_mod.v:561|uart_mod.v:300|uart_mod.v:74|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/arith_map.v:56"
.gate SB_LUT4 I0=$false I1=$false I2=common.pb.uart.tx_mod.symclk.count[23] I3=$auto$alumacc.cc:474:replace_alu$16178.C[23] O=$abc$44715$auto$wreduce.cc:455:run$15915[23]
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:395|uart_mod.v:561|uart_mod.v:300|uart_mod.v:74|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/arith_map.v:62|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:56"
.param LUT_INIT 0110100110010110
.gate SB_LUT4 I0=$false I1=$false I2=common.pb.uart.tx_mod.symclk.count[2] I3=$auto$alumacc.cc:474:replace_alu$16178.C[2] O=$abc$44715$auto$wreduce.cc:455:run$15915[2]
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:395|uart_mod.v:561|uart_mod.v:300|uart_mod.v:74|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/arith_map.v:62|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:56"
.param LUT_INIT 0110100110010110
.gate SB_CARRY CI=$auto$alumacc.cc:474:replace_alu$16178.C[2] CO=$auto$alumacc.cc:474:replace_alu$16178.C[3] I0=$false I1=common.pb.uart.tx_mod.symclk.count[2]
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:395|uart_mod.v:561|uart_mod.v:300|uart_mod.v:74|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/arith_map.v:56"
.gate SB_LUT4 I0=$false I1=$false I2=common.pb.uart.tx_mod.symclk.count[3] I3=$auto$alumacc.cc:474:replace_alu$16178.C[3] O=$abc$44715$auto$wreduce.cc:455:run$15915[3]
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:395|uart_mod.v:561|uart_mod.v:300|uart_mod.v:74|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/arith_map.v:62|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:56"
.param LUT_INIT 0110100110010110
.gate SB_CARRY CI=$auto$alumacc.cc:474:replace_alu$16178.C[3] CO=$auto$alumacc.cc:474:replace_alu$16178.C[4] I0=$false I1=common.pb.uart.tx_mod.symclk.count[3]
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:395|uart_mod.v:561|uart_mod.v:300|uart_mod.v:74|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/arith_map.v:56"
.gate SB_LUT4 I0=$false I1=$false I2=common.pb.uart.tx_mod.symclk.count[4] I3=$auto$alumacc.cc:474:replace_alu$16178.C[4] O=$abc$44715$auto$wreduce.cc:455:run$15915[4]
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:395|uart_mod.v:561|uart_mod.v:300|uart_mod.v:74|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/arith_map.v:62|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:56"
.param LUT_INIT 0110100110010110
.gate SB_CARRY CI=$auto$alumacc.cc:474:replace_alu$16178.C[4] CO=$auto$alumacc.cc:474:replace_alu$16178.C[5] I0=$false I1=common.pb.uart.tx_mod.symclk.count[4]
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:395|uart_mod.v:561|uart_mod.v:300|uart_mod.v:74|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/arith_map.v:56"
.gate SB_LUT4 I0=$false I1=$false I2=common.pb.uart.tx_mod.symclk.count[5] I3=$auto$alumacc.cc:474:replace_alu$16178.C[5] O=$abc$44715$auto$wreduce.cc:455:run$15915[5]
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:395|uart_mod.v:561|uart_mod.v:300|uart_mod.v:74|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/arith_map.v:62|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:56"
.param LUT_INIT 0110100110010110
.gate SB_CARRY CI=$auto$alumacc.cc:474:replace_alu$16178.C[5] CO=$auto$alumacc.cc:474:replace_alu$16178.C[6] I0=$false I1=common.pb.uart.tx_mod.symclk.count[5]
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:395|uart_mod.v:561|uart_mod.v:300|uart_mod.v:74|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/arith_map.v:56"
.gate SB_LUT4 I0=$false I1=$false I2=common.pb.uart.tx_mod.symclk.count[6] I3=$auto$alumacc.cc:474:replace_alu$16178.C[6] O=$abc$44715$auto$wreduce.cc:455:run$15915[6]
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:395|uart_mod.v:561|uart_mod.v:300|uart_mod.v:74|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/arith_map.v:62|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:56"
.param LUT_INIT 0110100110010110
.gate SB_CARRY CI=$auto$alumacc.cc:474:replace_alu$16178.C[6] CO=$auto$alumacc.cc:474:replace_alu$16178.C[7] I0=$false I1=common.pb.uart.tx_mod.symclk.count[6]
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:395|uart_mod.v:561|uart_mod.v:300|uart_mod.v:74|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/arith_map.v:56"
.gate SB_LUT4 I0=$false I1=$false I2=common.pb.uart.tx_mod.symclk.count[7] I3=$auto$alumacc.cc:474:replace_alu$16178.C[7] O=$abc$44715$auto$wreduce.cc:455:run$15915[7]
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:395|uart_mod.v:561|uart_mod.v:300|uart_mod.v:74|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/arith_map.v:62|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:56"
.param LUT_INIT 0110100110010110
.gate SB_CARRY CI=$auto$alumacc.cc:474:replace_alu$16178.C[7] CO=$auto$alumacc.cc:474:replace_alu$16178.C[8] I0=$false I1=common.pb.uart.tx_mod.symclk.count[7]
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:395|uart_mod.v:561|uart_mod.v:300|uart_mod.v:74|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/arith_map.v:56"
.gate SB_LUT4 I0=$false I1=$false I2=common.pb.uart.tx_mod.symclk.count[8] I3=$auto$alumacc.cc:474:replace_alu$16178.C[8] O=$abc$44715$auto$wreduce.cc:455:run$15915[8]
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:395|uart_mod.v:561|uart_mod.v:300|uart_mod.v:74|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/arith_map.v:62|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:56"
.param LUT_INIT 0110100110010110
.gate SB_CARRY CI=$auto$alumacc.cc:474:replace_alu$16178.C[8] CO=$auto$alumacc.cc:474:replace_alu$16178.C[9] I0=$false I1=common.pb.uart.tx_mod.symclk.count[8]
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:395|uart_mod.v:561|uart_mod.v:300|uart_mod.v:74|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/arith_map.v:56"
.gate SB_LUT4 I0=$false I1=$false I2=common.pb.uart.tx_mod.symclk.count[9] I3=$auto$alumacc.cc:474:replace_alu$16178.C[9] O=$abc$44715$auto$wreduce.cc:455:run$15915[9]
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:395|uart_mod.v:561|uart_mod.v:300|uart_mod.v:74|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/arith_map.v:62|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:56"
.param LUT_INIT 0110100110010110
.gate SB_CARRY CI=$auto$alumacc.cc:474:replace_alu$16178.C[9] CO=$auto$alumacc.cc:474:replace_alu$16178.C[10] I0=$false I1=common.pb.uart.tx_mod.symclk.count[9]
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:395|uart_mod.v:561|uart_mod.v:300|uart_mod.v:74|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/arith_map.v:56"
.gate $_TBUF_ A=common.pb.spi.miso_r E=$abc$44715$auto$rtlil.cc:1832:Not$15840 Y=PIN_10
.attr src "main.v:206|main.v:94"
.gate SB_DFFSR C=common.led_blink.clk D=$abc$44715$techmap\common.led_blink.$procmux$9288_Y Q=common.led_blink.led R=$abc$44715$auto$rtlil.cc:1969:NotGate$44099
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:109|led_blink_mod.v:44|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:2"
.gate SB_DFFSR C=common.led_blink.clk D=$abc$44715$techmap\common.pb.$procmux$14662_Y Q=common.pb.uart_tx_trigger R=$abc$44715$auto$rtlil.cc:1969:NotGate$44101
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:510|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:2"
.gate SB_DFFESR C=common.led_blink.clk D=$abc$44715$techmap\common.led_blink.$procmux$9260_Y[0] E=$abc$44715$auto$dff2dffe.cc:175:make_patterns_logic$26906 Q=common.led_blink.led_off_count[0] R=$abc$44715$auto$rtlil.cc:1969:NotGate$44099
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:109|led_blink_mod.v:44|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:8"
.gate SB_DFFESR C=common.led_blink.clk D=$abc$44715$techmap\common.led_blink.$procmux$9260_Y[1] E=$abc$44715$auto$dff2dffe.cc:175:make_patterns_logic$26948 Q=common.led_blink.led_off_count[1] R=$abc$44715$auto$rtlil.cc:1969:NotGate$44099
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:109|led_blink_mod.v:44|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:8"
.gate SB_DFFESR C=common.led_blink.clk D=$abc$44715$techmap\common.led_blink.$procmux$9260_Y[2] E=$abc$44715$auto$dff2dffe.cc:175:make_patterns_logic$26906 Q=common.led_blink.led_off_count[2] R=$abc$44715$auto$rtlil.cc:1969:NotGate$44099
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:109|led_blink_mod.v:44|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:8"
.gate SB_DFFESR C=common.led_blink.clk D=$abc$44715$techmap\common.led_blink.$procmux$9260_Y[3] E=$abc$44715$auto$dff2dffe.cc:175:make_patterns_logic$26906 Q=common.led_blink.led_off_count[3] R=$abc$44715$auto$rtlil.cc:1969:NotGate$44099
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:109|led_blink_mod.v:44|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:8"
.gate SB_DFFESR C=common.led_blink.clk D=$abc$44715$techmap\common.led_blink.$procmux$9260_Y[4] E=$abc$44715$auto$dff2dffe.cc:175:make_patterns_logic$26906 Q=common.led_blink.led_off_count[4] R=$abc$44715$auto$rtlil.cc:1969:NotGate$44099
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:109|led_blink_mod.v:44|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:8"
.gate SB_DFFESR C=common.led_blink.clk D=$abc$44715$techmap\common.led_blink.$procmux$9260_Y[5] E=$abc$44715$auto$dff2dffe.cc:175:make_patterns_logic$26906 Q=common.led_blink.led_off_count[5] R=$abc$44715$auto$rtlil.cc:1969:NotGate$44099
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:109|led_blink_mod.v:44|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:8"
.gate SB_DFFESR C=common.led_blink.clk D=$abc$44715$techmap\common.led_blink.$procmux$9260_Y[6] E=$abc$44715$auto$dff2dffe.cc:175:make_patterns_logic$26906 Q=common.led_blink.led_off_count[6] R=$abc$44715$auto$rtlil.cc:1969:NotGate$44099
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:109|led_blink_mod.v:44|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:8"
.gate SB_DFFESR C=common.led_blink.clk D=$abc$44715$techmap\common.led_blink.$procmux$9260_Y[7] E=$abc$44715$auto$dff2dffe.cc:175:make_patterns_logic$26906 Q=common.led_blink.led_off_count[7] R=$abc$44715$auto$rtlil.cc:1969:NotGate$44099
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:109|led_blink_mod.v:44|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:8"
.gate SB_DFFESR C=common.led_blink.clk D=$abc$44715$techmap\common.led_blink.$procmux$9260_Y[8] E=$abc$44715$auto$dff2dffe.cc:175:make_patterns_logic$26906 Q=common.led_blink.led_off_count[8] R=$abc$44715$auto$rtlil.cc:1969:NotGate$44099
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:109|led_blink_mod.v:44|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:8"
.gate SB_DFFESR C=common.led_blink.clk D=$abc$44715$techmap\common.led_blink.$procmux$9260_Y[9] E=$abc$44715$auto$dff2dffe.cc:175:make_patterns_logic$26906 Q=common.led_blink.led_off_count[9] R=$abc$44715$auto$rtlil.cc:1969:NotGate$44099
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:109|led_blink_mod.v:44|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:8"
.gate SB_DFFESR C=common.led_blink.clk D=$abc$44715$techmap\common.led_blink.$procmux$9260_Y[10] E=$abc$44715$auto$dff2dffe.cc:175:make_patterns_logic$26906 Q=common.led_blink.led_off_count[10] R=$abc$44715$auto$rtlil.cc:1969:NotGate$44099
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:109|led_blink_mod.v:44|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:8"
.gate SB_DFFESR C=common.led_blink.clk D=$abc$44715$techmap\common.led_blink.$procmux$9260_Y[11] E=$abc$44715$auto$dff2dffe.cc:175:make_patterns_logic$26906 Q=common.led_blink.led_off_count[11] R=$abc$44715$auto$rtlil.cc:1969:NotGate$44099
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:109|led_blink_mod.v:44|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:8"
.gate SB_DFFESR C=common.led_blink.clk D=$abc$44715$techmap\common.led_blink.$procmux$9260_Y[12] E=$abc$44715$auto$dff2dffe.cc:175:make_patterns_logic$26906 Q=common.led_blink.led_off_count[12] R=$abc$44715$auto$rtlil.cc:1969:NotGate$44099
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:109|led_blink_mod.v:44|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:8"
.gate SB_DFFESR C=common.led_blink.clk D=$abc$44715$techmap\common.led_blink.$procmux$9260_Y[13] E=$abc$44715$auto$dff2dffe.cc:175:make_patterns_logic$26906 Q=common.led_blink.led_off_count[13] R=$abc$44715$auto$rtlil.cc:1969:NotGate$44099
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:109|led_blink_mod.v:44|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:8"
.gate SB_DFFESR C=common.led_blink.clk D=$abc$44715$techmap\common.led_blink.$procmux$9260_Y[14] E=$abc$44715$auto$dff2dffe.cc:175:make_patterns_logic$26906 Q=common.led_blink.led_off_count[14] R=$abc$44715$auto$rtlil.cc:1969:NotGate$44099
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:109|led_blink_mod.v:44|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:8"
.gate SB_DFFESR C=common.led_blink.clk D=$abc$44715$techmap\common.led_blink.$procmux$9260_Y[15] E=$abc$44715$auto$dff2dffe.cc:175:make_patterns_logic$26906 Q=common.led_blink.led_off_count[15] R=$abc$44715$auto$rtlil.cc:1969:NotGate$44099
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:109|led_blink_mod.v:44|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:8"
.gate SB_DFFESR C=common.led_blink.clk D=$abc$44715$techmap\common.led_blink.$procmux$9260_Y[16] E=$abc$44715$auto$dff2dffe.cc:175:make_patterns_logic$26906 Q=common.led_blink.led_off_count[16] R=$abc$44715$auto$rtlil.cc:1969:NotGate$44099
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:109|led_blink_mod.v:44|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:8"
.gate SB_DFFESR C=common.led_blink.clk D=$abc$44715$techmap\common.led_blink.$procmux$9260_Y[17] E=$abc$44715$auto$dff2dffe.cc:175:make_patterns_logic$26906 Q=common.led_blink.led_off_count[17] R=$abc$44715$auto$rtlil.cc:1969:NotGate$44099
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:109|led_blink_mod.v:44|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:8"
.gate SB_DFFESR C=common.led_blink.clk D=$abc$44715$techmap\common.led_blink.$procmux$9260_Y[18] E=$abc$44715$auto$dff2dffe.cc:175:make_patterns_logic$26906 Q=common.led_blink.led_off_count[18] R=$abc$44715$auto$rtlil.cc:1969:NotGate$44099
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:109|led_blink_mod.v:44|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:8"
.gate SB_DFFESR C=common.led_blink.clk D=$abc$44715$techmap\common.led_blink.$procmux$9260_Y[19] E=$abc$44715$auto$dff2dffe.cc:175:make_patterns_logic$26906 Q=common.led_blink.led_off_count[19] R=$abc$44715$auto$rtlil.cc:1969:NotGate$44099
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:109|led_blink_mod.v:44|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:8"
.gate SB_DFFESR C=common.led_blink.clk D=$abc$44715$techmap\common.led_blink.$procmux$9260_Y[20] E=$abc$44715$auto$dff2dffe.cc:175:make_patterns_logic$26906 Q=common.led_blink.led_off_count[20] R=$abc$44715$auto$rtlil.cc:1969:NotGate$44099
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:109|led_blink_mod.v:44|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:8"
.gate SB_DFFESR C=common.led_blink.clk D=$abc$44715$techmap\common.led_blink.$procmux$9260_Y[21] E=$abc$44715$auto$dff2dffe.cc:175:make_patterns_logic$26906 Q=common.led_blink.led_off_count[21] R=$abc$44715$auto$rtlil.cc:1969:NotGate$44099
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:109|led_blink_mod.v:44|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:8"
.gate SB_DFFESR C=common.led_blink.clk D=$abc$44715$techmap\common.led_blink.$procmux$9260_Y[22] E=$abc$44715$auto$dff2dffe.cc:175:make_patterns_logic$26906 Q=common.led_blink.led_off_count[22] R=$abc$44715$auto$rtlil.cc:1969:NotGate$44099
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:109|led_blink_mod.v:44|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:8"
.gate SB_DFFESR C=common.led_blink.clk D=$abc$44715$techmap\common.led_blink.$procmux$9260_Y[23] E=$abc$44715$auto$dff2dffe.cc:175:make_patterns_logic$26906 Q=common.led_blink.led_off_count[23] R=$abc$44715$auto$rtlil.cc:1969:NotGate$44099
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:109|led_blink_mod.v:44|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:8"
.gate SB_DFFESR C=common.led_blink.clk D=$abc$44715$techmap\common.led_blink.$procmux$9260_Y[24] E=$abc$44715$auto$dff2dffe.cc:175:make_patterns_logic$26906 Q=common.led_blink.led_off_count[24] R=$abc$44715$auto$rtlil.cc:1969:NotGate$44099
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:109|led_blink_mod.v:44|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:8"
.gate SB_DFFESR C=common.led_blink.clk D=$abc$44715$techmap\common.led_blink.$procmux$9260_Y[25] E=$abc$44715$auto$dff2dffe.cc:175:make_patterns_logic$26906 Q=common.led_blink.led_off_count[25] R=$abc$44715$auto$rtlil.cc:1969:NotGate$44099
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:109|led_blink_mod.v:44|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:8"
.gate SB_DFFESR C=common.led_blink.clk D=$abc$44715$techmap\common.led_blink.$procmux$9260_Y[26] E=$abc$44715$auto$dff2dffe.cc:175:make_patterns_logic$26906 Q=common.led_blink.led_off_count[26] R=$abc$44715$auto$rtlil.cc:1969:NotGate$44099
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:109|led_blink_mod.v:44|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:8"
.gate SB_DFFESR C=common.led_blink.clk D=$abc$44715$techmap\common.led_blink.$procmux$9260_Y[27] E=$abc$44715$auto$dff2dffe.cc:175:make_patterns_logic$26906 Q=common.led_blink.led_off_count[27] R=$abc$44715$auto$rtlil.cc:1969:NotGate$44099
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:109|led_blink_mod.v:44|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:8"
.gate SB_DFFESR C=common.led_blink.clk D=$abc$44715$techmap\common.led_blink.$procmux$9260_Y[28] E=$abc$44715$auto$dff2dffe.cc:175:make_patterns_logic$26906 Q=common.led_blink.led_off_count[28] R=$abc$44715$auto$rtlil.cc:1969:NotGate$44099
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:109|led_blink_mod.v:44|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:8"
.gate SB_DFFESR C=common.led_blink.clk D=$abc$44715$techmap\common.led_blink.$procmux$9260_Y[29] E=$abc$44715$auto$dff2dffe.cc:175:make_patterns_logic$26906 Q=common.led_blink.led_off_count[29] R=$abc$44715$auto$rtlil.cc:1969:NotGate$44099
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:109|led_blink_mod.v:44|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:8"
.gate SB_DFFESR C=common.led_blink.clk D=$abc$44715$techmap\common.led_blink.$procmux$9260_Y[30] E=$abc$44715$auto$dff2dffe.cc:175:make_patterns_logic$26906 Q=common.led_blink.led_off_count[30] R=$abc$44715$auto$rtlil.cc:1969:NotGate$44099
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:109|led_blink_mod.v:44|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:8"
.gate SB_DFFESR C=common.led_blink.clk D=$abc$44715$techmap\common.led_blink.$procmux$9260_Y[31] E=$abc$44715$auto$dff2dffe.cc:175:make_patterns_logic$26906 Q=common.led_blink.led_off_count[31] R=$abc$44715$auto$rtlil.cc:1969:NotGate$44099
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:109|led_blink_mod.v:44|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:8"
.gate SB_DFFESR C=common.led_blink.clk D=$abc$44715$techmap\common.led_blink.$procmux$9274_Y[0] E=$abc$44715$auto$dff2dffe.cc:175:make_patterns_logic$27832 Q=common.led_blink.led_on_count[0] R=$abc$44715$auto$rtlil.cc:1969:NotGate$44099
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:109|led_blink_mod.v:44|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:8"
.gate SB_DFFESR C=common.led_blink.clk D=$abc$44715$techmap\common.led_blink.$procmux$9274_Y[1] E=$abc$44715$auto$dff2dffe.cc:175:make_patterns_logic$27890 Q=common.led_blink.led_on_count[1] R=$abc$44715$auto$rtlil.cc:1969:NotGate$44099
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:109|led_blink_mod.v:44|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:8"
.gate SB_DFFESR C=common.led_blink.clk D=$abc$44715$techmap\common.led_blink.$procmux$9274_Y[2] E=$abc$44715$auto$dff2dffe.cc:175:make_patterns_logic$27832 Q=common.led_blink.led_on_count[2] R=$abc$44715$auto$rtlil.cc:1969:NotGate$44099
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:109|led_blink_mod.v:44|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:8"
.gate SB_DFFESR C=common.led_blink.clk D=$abc$44715$techmap\common.led_blink.$procmux$9274_Y[3] E=$abc$44715$auto$dff2dffe.cc:175:make_patterns_logic$27832 Q=common.led_blink.led_on_count[3] R=$abc$44715$auto$rtlil.cc:1969:NotGate$44099
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:109|led_blink_mod.v:44|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:8"
.gate SB_DFFESR C=common.led_blink.clk D=$abc$44715$techmap\common.led_blink.$procmux$9274_Y[4] E=$abc$44715$auto$dff2dffe.cc:175:make_patterns_logic$27832 Q=common.led_blink.led_on_count[4] R=$abc$44715$auto$rtlil.cc:1969:NotGate$44099
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:109|led_blink_mod.v:44|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:8"
.gate SB_DFFESR C=common.led_blink.clk D=$abc$44715$techmap\common.led_blink.$procmux$9274_Y[5] E=$abc$44715$auto$dff2dffe.cc:175:make_patterns_logic$27832 Q=common.led_blink.led_on_count[5] R=$abc$44715$auto$rtlil.cc:1969:NotGate$44099
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:109|led_blink_mod.v:44|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:8"
.gate SB_DFFESR C=common.led_blink.clk D=$abc$44715$techmap\common.led_blink.$procmux$9274_Y[6] E=$abc$44715$auto$dff2dffe.cc:175:make_patterns_logic$27832 Q=common.led_blink.led_on_count[6] R=$abc$44715$auto$rtlil.cc:1969:NotGate$44099
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:109|led_blink_mod.v:44|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:8"
.gate SB_DFFESR C=common.led_blink.clk D=$abc$44715$techmap\common.led_blink.$procmux$9274_Y[7] E=$abc$44715$auto$dff2dffe.cc:175:make_patterns_logic$27832 Q=common.led_blink.led_on_count[7] R=$abc$44715$auto$rtlil.cc:1969:NotGate$44099
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:109|led_blink_mod.v:44|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:8"
.gate SB_DFFESR C=common.led_blink.clk D=$abc$44715$techmap\common.led_blink.$procmux$9274_Y[8] E=$abc$44715$auto$dff2dffe.cc:175:make_patterns_logic$27832 Q=common.led_blink.led_on_count[8] R=$abc$44715$auto$rtlil.cc:1969:NotGate$44099
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:109|led_blink_mod.v:44|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:8"
.gate SB_DFFESR C=common.led_blink.clk D=$abc$44715$techmap\common.led_blink.$procmux$9274_Y[9] E=$abc$44715$auto$dff2dffe.cc:175:make_patterns_logic$27832 Q=common.led_blink.led_on_count[9] R=$abc$44715$auto$rtlil.cc:1969:NotGate$44099
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:109|led_blink_mod.v:44|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:8"
.gate SB_DFFESR C=common.led_blink.clk D=$abc$44715$techmap\common.led_blink.$procmux$9274_Y[10] E=$abc$44715$auto$dff2dffe.cc:175:make_patterns_logic$27832 Q=common.led_blink.led_on_count[10] R=$abc$44715$auto$rtlil.cc:1969:NotGate$44099
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:109|led_blink_mod.v:44|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:8"
.gate SB_DFFESR C=common.led_blink.clk D=$abc$44715$techmap\common.led_blink.$procmux$9274_Y[11] E=$abc$44715$auto$dff2dffe.cc:175:make_patterns_logic$27832 Q=common.led_blink.led_on_count[11] R=$abc$44715$auto$rtlil.cc:1969:NotGate$44099
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:109|led_blink_mod.v:44|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:8"
.gate SB_DFFESR C=common.led_blink.clk D=$abc$44715$techmap\common.led_blink.$procmux$9274_Y[12] E=$abc$44715$auto$dff2dffe.cc:175:make_patterns_logic$27832 Q=common.led_blink.led_on_count[12] R=$abc$44715$auto$rtlil.cc:1969:NotGate$44099
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:109|led_blink_mod.v:44|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:8"
.gate SB_DFFESR C=common.led_blink.clk D=$abc$44715$techmap\common.led_blink.$procmux$9274_Y[13] E=$abc$44715$auto$dff2dffe.cc:175:make_patterns_logic$27832 Q=common.led_blink.led_on_count[13] R=$abc$44715$auto$rtlil.cc:1969:NotGate$44099
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:109|led_blink_mod.v:44|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:8"
.gate SB_DFFESR C=common.led_blink.clk D=$abc$44715$techmap\common.led_blink.$procmux$9274_Y[14] E=$abc$44715$auto$dff2dffe.cc:175:make_patterns_logic$27832 Q=common.led_blink.led_on_count[14] R=$abc$44715$auto$rtlil.cc:1969:NotGate$44099
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:109|led_blink_mod.v:44|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:8"
.gate SB_DFFESR C=common.led_blink.clk D=$abc$44715$techmap\common.led_blink.$procmux$9274_Y[15] E=$abc$44715$auto$dff2dffe.cc:175:make_patterns_logic$27832 Q=common.led_blink.led_on_count[15] R=$abc$44715$auto$rtlil.cc:1969:NotGate$44099
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:109|led_blink_mod.v:44|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:8"
.gate SB_DFFESR C=common.led_blink.clk D=$abc$44715$techmap\common.led_blink.$procmux$9274_Y[16] E=$abc$44715$auto$dff2dffe.cc:175:make_patterns_logic$27832 Q=common.led_blink.led_on_count[16] R=$abc$44715$auto$rtlil.cc:1969:NotGate$44099
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:109|led_blink_mod.v:44|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:8"
.gate SB_DFFESR C=common.led_blink.clk D=$abc$44715$techmap\common.led_blink.$procmux$9274_Y[17] E=$abc$44715$auto$dff2dffe.cc:175:make_patterns_logic$27832 Q=common.led_blink.led_on_count[17] R=$abc$44715$auto$rtlil.cc:1969:NotGate$44099
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:109|led_blink_mod.v:44|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:8"
.gate SB_DFFESR C=common.led_blink.clk D=$abc$44715$techmap\common.led_blink.$procmux$9274_Y[18] E=$abc$44715$auto$dff2dffe.cc:175:make_patterns_logic$27832 Q=common.led_blink.led_on_count[18] R=$abc$44715$auto$rtlil.cc:1969:NotGate$44099
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:109|led_blink_mod.v:44|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:8"
.gate SB_DFFESR C=common.led_blink.clk D=$abc$44715$techmap\common.led_blink.$procmux$9274_Y[19] E=$abc$44715$auto$dff2dffe.cc:175:make_patterns_logic$27832 Q=common.led_blink.led_on_count[19] R=$abc$44715$auto$rtlil.cc:1969:NotGate$44099
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:109|led_blink_mod.v:44|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:8"
.gate SB_DFFESR C=common.led_blink.clk D=$abc$44715$techmap\common.led_blink.$procmux$9274_Y[20] E=$abc$44715$auto$dff2dffe.cc:175:make_patterns_logic$27832 Q=common.led_blink.led_on_count[20] R=$abc$44715$auto$rtlil.cc:1969:NotGate$44099
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:109|led_blink_mod.v:44|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:8"
.gate SB_DFFESR C=common.led_blink.clk D=$abc$44715$techmap\common.led_blink.$procmux$9274_Y[21] E=$abc$44715$auto$dff2dffe.cc:175:make_patterns_logic$27832 Q=common.led_blink.led_on_count[21] R=$abc$44715$auto$rtlil.cc:1969:NotGate$44099
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:109|led_blink_mod.v:44|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:8"
.gate SB_DFFESR C=common.led_blink.clk D=$abc$44715$techmap\common.led_blink.$procmux$9274_Y[22] E=$abc$44715$auto$dff2dffe.cc:175:make_patterns_logic$27832 Q=common.led_blink.led_on_count[22] R=$abc$44715$auto$rtlil.cc:1969:NotGate$44099
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:109|led_blink_mod.v:44|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:8"
.gate SB_DFFESR C=common.led_blink.clk D=$abc$44715$techmap\common.led_blink.$procmux$9274_Y[23] E=$abc$44715$auto$dff2dffe.cc:175:make_patterns_logic$27832 Q=common.led_blink.led_on_count[23] R=$abc$44715$auto$rtlil.cc:1969:NotGate$44099
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:109|led_blink_mod.v:44|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:8"
.gate SB_DFFESR C=common.led_blink.clk D=$abc$44715$techmap\common.led_blink.$procmux$9274_Y[24] E=$abc$44715$auto$dff2dffe.cc:175:make_patterns_logic$27832 Q=common.led_blink.led_on_count[24] R=$abc$44715$auto$rtlil.cc:1969:NotGate$44099
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:109|led_blink_mod.v:44|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:8"
.gate SB_DFFESR C=common.led_blink.clk D=$abc$44715$techmap\common.led_blink.$procmux$9274_Y[25] E=$abc$44715$auto$dff2dffe.cc:175:make_patterns_logic$27832 Q=common.led_blink.led_on_count[25] R=$abc$44715$auto$rtlil.cc:1969:NotGate$44099
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:109|led_blink_mod.v:44|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:8"
.gate SB_DFFESR C=common.led_blink.clk D=$abc$44715$techmap\common.led_blink.$procmux$9274_Y[26] E=$abc$44715$auto$dff2dffe.cc:175:make_patterns_logic$27832 Q=common.led_blink.led_on_count[26] R=$abc$44715$auto$rtlil.cc:1969:NotGate$44099
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:109|led_blink_mod.v:44|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:8"
.gate SB_DFFESR C=common.led_blink.clk D=$abc$44715$techmap\common.led_blink.$procmux$9274_Y[27] E=$abc$44715$auto$dff2dffe.cc:175:make_patterns_logic$27832 Q=common.led_blink.led_on_count[27] R=$abc$44715$auto$rtlil.cc:1969:NotGate$44099
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:109|led_blink_mod.v:44|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:8"
.gate SB_DFFESR C=common.led_blink.clk D=$abc$44715$techmap\common.led_blink.$procmux$9274_Y[28] E=$abc$44715$auto$dff2dffe.cc:175:make_patterns_logic$27832 Q=common.led_blink.led_on_count[28] R=$abc$44715$auto$rtlil.cc:1969:NotGate$44099
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:109|led_blink_mod.v:44|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:8"
.gate SB_DFFESR C=common.led_blink.clk D=$abc$44715$techmap\common.led_blink.$procmux$9274_Y[29] E=$abc$44715$auto$dff2dffe.cc:175:make_patterns_logic$27832 Q=common.led_blink.led_on_count[29] R=$abc$44715$auto$rtlil.cc:1969:NotGate$44099
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:109|led_blink_mod.v:44|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:8"
.gate SB_DFFESR C=common.led_blink.clk D=$abc$44715$techmap\common.led_blink.$procmux$9274_Y[30] E=$abc$44715$auto$dff2dffe.cc:175:make_patterns_logic$27832 Q=common.led_blink.led_on_count[30] R=$abc$44715$auto$rtlil.cc:1969:NotGate$44099
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:109|led_blink_mod.v:44|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:8"
.gate SB_DFFESR C=common.led_blink.clk D=$abc$44715$techmap\common.led_blink.$procmux$9274_Y[31] E=$abc$44715$auto$dff2dffe.cc:175:make_patterns_logic$27832 Q=common.led_blink.led_on_count[31] R=$abc$44715$auto$rtlil.cc:1969:NotGate$44099
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:109|led_blink_mod.v:44|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:8"
.gate SB_DFFE C=common.led_blink.clk D=$abc$44715$techmap\common.pb.$0\rx_buf_overflow[0:0] E=$abc$44715$auto$dff2dffe.cc:175:make_patterns_logic$29258 Q=common.pb.rx_buf_overflow[0]
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:476|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:8"
.gate SB_DFFESR C=common.led_blink.clk D=common.pb.uart.rx_mod.rx_irq E=$abc$44715$auto$dff2dffe.cc:175:make_patterns_logic$29291 Q=common.pb.rx_buf_wr R=$abc$44715$auto$rtlil.cc:1969:NotGate$44101
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:476|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:8"
.gate SB_DFFE C=common.led_blink.clk D=common.pb.uart.rx_mod.rx_data[0] E=$abc$44715$auto$dff2dffe.cc:175:make_patterns_logic$29336 Q=common.pb.rx_buf_wr_data[0]
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:476|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:8"
.gate SB_DFFE C=common.led_blink.clk D=common.pb.uart.rx_mod.rx_data[1] E=$abc$44715$auto$dff2dffe.cc:175:make_patterns_logic$29336 Q=common.pb.rx_buf_wr_data[1]
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:476|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:8"
.gate SB_DFFE C=common.led_blink.clk D=common.pb.uart.rx_mod.rx_data[2] E=$abc$44715$auto$dff2dffe.cc:175:make_patterns_logic$29336 Q=common.pb.rx_buf_wr_data[2]
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:476|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:8"
.gate SB_DFFE C=common.led_blink.clk D=common.pb.uart.rx_mod.rx_data[3] E=$abc$44715$auto$dff2dffe.cc:175:make_patterns_logic$29336 Q=common.pb.rx_buf_wr_data[3]
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:476|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:8"
.gate SB_DFFE C=common.led_blink.clk D=common.pb.uart.rx_mod.rx_data[4] E=$abc$44715$auto$dff2dffe.cc:175:make_patterns_logic$29336 Q=common.pb.rx_buf_wr_data[4]
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:476|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:8"
.gate SB_DFFE C=common.led_blink.clk D=common.pb.uart.rx_mod.rx_data[5] E=$abc$44715$auto$dff2dffe.cc:175:make_patterns_logic$29336 Q=common.pb.rx_buf_wr_data[5]
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:476|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:8"
.gate SB_DFFE C=common.led_blink.clk D=common.pb.uart.rx_mod.rx_data[6] E=$abc$44715$auto$dff2dffe.cc:175:make_patterns_logic$29336 Q=common.pb.rx_buf_wr_data[6]
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:476|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:8"
.gate SB_DFFE C=common.led_blink.clk D=common.pb.uart.rx_mod.rx_data[7] E=$abc$44715$auto$dff2dffe.cc:175:make_patterns_logic$29336 Q=common.pb.rx_buf_wr_data[7]
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:476|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:8"
.gate SB_DFFE C=common.led_blink.clk D=$abc$44715$auto$rtlil.cc:1836:ReduceOr$16117 E=$abc$44715$auto$dff2dffe.cc:175:make_patterns_logic$29336 Q=common.pb.rx_buf_wr_data[8]
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:476|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:8"
.gate SB_DFFESR C=common.led_blink.clk D=common.pb.rx_buf_wr_addr_next[0] E=$abc$44715$auto$dff2dffe.cc:175:make_patterns_logic$29748 Q=common.pb.rx_buf_wr_addr[0] R=$abc$44715$auto$rtlil.cc:1969:NotGate$44101
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:476|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:8"
.gate SB_DFFESR C=common.led_blink.clk D=common.pb.rx_buf_wr_addr_next[1] E=$abc$44715$auto$dff2dffe.cc:175:make_patterns_logic$29748 Q=common.pb.rx_buf_wr_addr[1] R=$abc$44715$auto$rtlil.cc:1969:NotGate$44101
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:476|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:8"
.gate SB_DFFESR C=common.led_blink.clk D=common.pb.rx_buf_wr_addr_next[2] E=$abc$44715$auto$dff2dffe.cc:175:make_patterns_logic$29748 Q=common.pb.rx_buf_wr_addr[2] R=$abc$44715$auto$rtlil.cc:1969:NotGate$44101
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:476|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:8"
.gate SB_DFFESR C=common.led_blink.clk D=common.pb.rx_buf_wr_addr_next[3] E=$abc$44715$auto$dff2dffe.cc:175:make_patterns_logic$29748 Q=common.pb.rx_buf_wr_addr[3] R=$abc$44715$auto$rtlil.cc:1969:NotGate$44101
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:476|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:8"
.gate SB_DFFESR C=common.led_blink.clk D=common.pb.rx_buf_wr_addr_next[4] E=$abc$44715$auto$dff2dffe.cc:175:make_patterns_logic$29748 Q=common.pb.rx_buf_wr_addr[4] R=$abc$44715$auto$rtlil.cc:1969:NotGate$44101
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:476|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:8"
.gate SB_DFFESR C=common.led_blink.clk D=common.pb.rx_buf_wr_addr_next[5] E=$abc$44715$auto$dff2dffe.cc:175:make_patterns_logic$29748 Q=common.pb.rx_buf_wr_addr[5] R=$abc$44715$auto$rtlil.cc:1969:NotGate$44101
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:476|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:8"
.gate SB_DFFESR C=common.led_blink.clk D=common.pb.rx_buf_wr_addr_next[6] E=$abc$44715$auto$dff2dffe.cc:175:make_patterns_logic$29748 Q=common.pb.rx_buf_wr_addr[6] R=$abc$44715$auto$rtlil.cc:1969:NotGate$44101
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:476|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:8"
.gate SB_DFFESR C=common.led_blink.clk D=common.pb.rx_buf_wr_addr_next[7] E=$abc$44715$auto$dff2dffe.cc:175:make_patterns_logic$29748 Q=common.pb.rx_buf_wr_addr[7] R=$abc$44715$auto$rtlil.cc:1969:NotGate$44101
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:476|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:8"
.gate SB_DFFESR C=common.led_blink.clk D=common.pb.tx_buf.rd_data1[0] E=$abc$44715$auto$dff2dffe.cc:175:make_patterns_logic$29962 Q=common.pb.uart_tx_data[0] R=$abc$44715$auto$rtlil.cc:1969:NotGate$44101
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:510|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:8"
.gate SB_DFFESR C=common.led_blink.clk D=common.pb.tx_buf.rd_data1[1] E=$abc$44715$auto$dff2dffe.cc:175:make_patterns_logic$29962 Q=common.pb.uart_tx_data[1] R=$abc$44715$auto$rtlil.cc:1969:NotGate$44101
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:510|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:8"
.gate SB_DFFESR C=common.led_blink.clk D=common.pb.tx_buf.rd_data1[2] E=$abc$44715$auto$dff2dffe.cc:175:make_patterns_logic$29962 Q=common.pb.uart_tx_data[2] R=$abc$44715$auto$rtlil.cc:1969:NotGate$44101
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:510|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:8"
.gate SB_DFFESR C=common.led_blink.clk D=common.pb.tx_buf.rd_data1[3] E=$abc$44715$auto$dff2dffe.cc:175:make_patterns_logic$29962 Q=common.pb.uart_tx_data[3] R=$abc$44715$auto$rtlil.cc:1969:NotGate$44101
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:510|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:8"
.gate SB_DFFESR C=common.led_blink.clk D=common.pb.tx_buf.rd_data1[4] E=$abc$44715$auto$dff2dffe.cc:175:make_patterns_logic$29962 Q=common.pb.uart_tx_data[4] R=$abc$44715$auto$rtlil.cc:1969:NotGate$44101
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:510|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:8"
.gate SB_DFFESR C=common.led_blink.clk D=common.pb.tx_buf.rd_data1[5] E=$abc$44715$auto$dff2dffe.cc:175:make_patterns_logic$29962 Q=common.pb.uart_tx_data[5] R=$abc$44715$auto$rtlil.cc:1969:NotGate$44101
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:510|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:8"
.gate SB_DFFESR C=common.led_blink.clk D=common.pb.tx_buf.rd_data1[6] E=$abc$44715$auto$dff2dffe.cc:175:make_patterns_logic$29962 Q=common.pb.uart_tx_data[6] R=$abc$44715$auto$rtlil.cc:1969:NotGate$44101
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:510|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:8"
.gate SB_DFFESR C=common.led_blink.clk D=common.pb.tx_buf.rd_data1[7] E=$abc$44715$auto$dff2dffe.cc:175:make_patterns_logic$29962 Q=common.pb.uart_tx_data[7] R=$abc$44715$auto$rtlil.cc:1969:NotGate$44101
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:510|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:8"
.gate SB_DFFESR C=common.led_blink.clk D=$auto$wreduce.cc:455:run$15906[0] E=$abc$44715$auto$dff2dffe.cc:175:make_patterns_logic$29962 Q=common.pb.tx_buf_rd_addr[0] R=$abc$44715$auto$rtlil.cc:1969:NotGate$44101
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:510|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:8"
.gate SB_DFFESR C=common.led_blink.clk D=$abc$44715$auto$simplemap.cc:309:simplemap_lut$25661[1] E=$abc$44715$auto$dff2dffe.cc:175:make_patterns_logic$30348 Q=common.pb.tx_buf_rd_addr[1] R=$abc$44715$auto$rtlil.cc:1969:NotGate$44101
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:510|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:8"
.gate SB_DFFESR C=common.led_blink.clk D=$auto$wreduce.cc:455:run$15906[2] E=$abc$44715$auto$dff2dffe.cc:175:make_patterns_logic$29962 Q=common.pb.tx_buf_rd_addr[2] R=$abc$44715$auto$rtlil.cc:1969:NotGate$44101
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:510|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:8"
.gate SB_DFFESR C=common.led_blink.clk D=$auto$wreduce.cc:455:run$15906[3] E=$abc$44715$auto$dff2dffe.cc:175:make_patterns_logic$29962 Q=common.pb.tx_buf_rd_addr[3] R=$abc$44715$auto$rtlil.cc:1969:NotGate$44101
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:510|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:8"
.gate SB_DFFESR C=common.led_blink.clk D=$auto$wreduce.cc:455:run$15906[4] E=$abc$44715$auto$dff2dffe.cc:175:make_patterns_logic$29962 Q=common.pb.tx_buf_rd_addr[4] R=$abc$44715$auto$rtlil.cc:1969:NotGate$44101
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:510|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:8"
.gate SB_DFFESR C=common.led_blink.clk D=$auto$wreduce.cc:455:run$15906[5] E=$abc$44715$auto$dff2dffe.cc:175:make_patterns_logic$29962 Q=common.pb.tx_buf_rd_addr[5] R=$abc$44715$auto$rtlil.cc:1969:NotGate$44101
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:510|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:8"
.gate SB_DFFESR C=common.led_blink.clk D=$auto$wreduce.cc:455:run$15906[6] E=$abc$44715$auto$dff2dffe.cc:175:make_patterns_logic$29962 Q=common.pb.tx_buf_rd_addr[6] R=$abc$44715$auto$rtlil.cc:1969:NotGate$44101
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:510|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:8"
.gate SB_DFFESR C=common.led_blink.clk D=$auto$wreduce.cc:455:run$15906[7] E=$abc$44715$auto$dff2dffe.cc:175:make_patterns_logic$29962 Q=common.pb.tx_buf_rd_addr[7] R=$abc$44715$auto$rtlil.cc:1969:NotGate$44101
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:510|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:8"
.gate SB_DFFE C=common.led_blink.clk D=$abc$44715$techmap\common.pb.$0\spitx_ctrl_pending[0:0] E=$abc$44715$auto$dff2dffe.cc:175:make_patterns_logic$30642 Q=common.pb.spitx_ctrl_pending
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:604|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:8"
.gate SB_DFFE C=common.led_blink.clk D=$abc$44715$techmap$techmap\common.pb.$procmux$13142.$reduce_or$/home/mb/fpga-toolchain/yosys/bin/../share/yosys/techmap.v:441$18553_Y E=$abc$44715$auto$dff2dffe.cc:175:make_patterns_logic$30676 Q=common.pb.spitx_ctrl_reply_data[0]
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:604|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:8"
.gate SB_DFFE C=common.led_blink.clk D=$abc$44715$techmap$techmap\common.pb.$procmux$13106.$reduce_or$/home/mb/fpga-toolchain/yosys/bin/../share/yosys/techmap.v:441$18553_Y E=$abc$44715$auto$dff2dffe.cc:175:make_patterns_logic$30676 Q=common.pb.spitx_ctrl_reply_data[1]
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:604|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:8"
.gate SB_DFFE C=common.led_blink.clk D=$abc$44715$techmap$techmap\common.pb.$procmux$13070.$reduce_or$/home/mb/fpga-toolchain/yosys/bin/../share/yosys/techmap.v:441$18553_Y E=$abc$44715$auto$dff2dffe.cc:175:make_patterns_logic$30676 Q=common.pb.spitx_ctrl_reply_data[2]
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:604|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:8"
.gate SB_DFFE C=common.led_blink.clk D=$abc$44715$techmap$techmap\common.pb.$procmux$13034.$reduce_or$/home/mb/fpga-toolchain/yosys/bin/../share/yosys/techmap.v:441$18553_Y E=$abc$44715$auto$dff2dffe.cc:175:make_patterns_logic$30676 Q=common.pb.spitx_ctrl_reply_data[3]
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:604|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:8"
.gate SB_DFFE C=common.led_blink.clk D=$abc$44715$techmap$techmap\common.pb.$procmux$13013.$reduce_or$/home/mb/fpga-toolchain/yosys/bin/../share/yosys/techmap.v:441$18553_Y E=$abc$44715$auto$dff2dffe.cc:175:make_patterns_logic$30676 Q=common.pb.spitx_ctrl_reply_data[4]
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:604|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:8"
.gate SB_DFFE C=common.led_blink.clk D=$abc$44715$techmap$techmap\common.pb.$procmux$13163.$reduce_or$/home/mb/fpga-toolchain/yosys/bin/../share/yosys/techmap.v:441$18553_Y E=$abc$44715$auto$dff2dffe.cc:175:make_patterns_logic$30676 Q=common.pb.spitx_ctrl_reply_data[5]
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:604|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:8"
.gate SB_DFFE C=common.led_blink.clk D=$abc$44715$techmap$techmap\common.pb.$procmux$12992.$reduce_or$/home/mb/fpga-toolchain/yosys/bin/../share/yosys/techmap.v:441$18830_Y E=$abc$44715$auto$dff2dffe.cc:175:make_patterns_logic$30676 Q=common.pb.spitx_ctrl_reply_data[6]
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:604|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:8"
.gate SB_DFFE C=common.led_blink.clk D=$abc$44715$techmap$techmap\common.pb.$procmux$12992.$reduce_or$/home/mb/fpga-toolchain/yosys/bin/../share/yosys/techmap.v:441$18831_Y E=$abc$44715$auto$dff2dffe.cc:175:make_patterns_logic$30676 Q=common.pb.spitx_ctrl_reply_data[7]
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:604|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:8"
.gate SB_DFFE C=common.led_blink.clk D=$abc$44715$techmap$techmap\common.pb.$procmux$12992.$reduce_or$/home/mb/fpga-toolchain/yosys/bin/../share/yosys/techmap.v:441$18832_Y E=$abc$44715$auto$dff2dffe.cc:175:make_patterns_logic$30676 Q=common.pb.spitx_ctrl_reply_data[8]
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:604|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:8"
.gate SB_DFFE C=common.led_blink.clk D=$abc$44715$techmap$techmap\common.pb.$procmux$12992.$reduce_or$/home/mb/fpga-toolchain/yosys/bin/../share/yosys/techmap.v:441$18833_Y E=$abc$44715$auto$dff2dffe.cc:175:make_patterns_logic$30676 Q=common.pb.spitx_ctrl_reply_data[9]
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:604|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:8"
.gate SB_DFFE C=common.led_blink.clk D=$abc$44715$techmap$techmap\common.pb.$procmux$12992.$reduce_or$/home/mb/fpga-toolchain/yosys/bin/../share/yosys/techmap.v:441$18834_Y E=$abc$44715$auto$dff2dffe.cc:175:make_patterns_logic$30676 Q=common.pb.spitx_ctrl_reply_data[10]
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:604|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:8"
.gate SB_DFFE C=common.led_blink.clk D=$abc$44715$techmap$techmap\common.pb.$procmux$12992.$reduce_or$/home/mb/fpga-toolchain/yosys/bin/../share/yosys/techmap.v:441$18835_Y E=$abc$44715$auto$dff2dffe.cc:175:make_patterns_logic$30676 Q=common.pb.spitx_ctrl_reply_data[11]
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:604|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:8"
.gate SB_DFFE C=common.led_blink.clk D=$abc$44715$techmap$techmap\common.pb.$procmux$12992.$reduce_or$/home/mb/fpga-toolchain/yosys/bin/../share/yosys/techmap.v:441$18836_Y E=$abc$44715$auto$dff2dffe.cc:175:make_patterns_logic$30676 Q=common.pb.spitx_ctrl_reply_data[12]
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:604|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:8"
.gate SB_DFFE C=common.led_blink.clk D=$abc$44715$techmap$techmap\common.pb.$procmux$12992.$reduce_or$/home/mb/fpga-toolchain/yosys/bin/../share/yosys/techmap.v:441$18837_Y E=$abc$44715$auto$dff2dffe.cc:175:make_patterns_logic$30676 Q=common.pb.spitx_ctrl_reply_data[13]
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:604|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:8"
.gate SB_DFFE C=common.led_blink.clk D=$abc$44715$techmap$techmap\common.pb.$procmux$12992.$reduce_or$/home/mb/fpga-toolchain/yosys/bin/../share/yosys/techmap.v:441$18838_Y E=$abc$44715$auto$dff2dffe.cc:175:make_patterns_logic$30676 Q=common.pb.spitx_ctrl_reply_data[14]
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:604|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:8"
.gate SB_DFFE C=common.led_blink.clk D=$abc$44715$techmap$techmap\common.pb.$procmux$12992.$reduce_or$/home/mb/fpga-toolchain/yosys/bin/../share/yosys/techmap.v:441$18839_Y E=$abc$44715$auto$dff2dffe.cc:175:make_patterns_logic$30676 Q=common.pb.spitx_ctrl_reply_data[15]
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:604|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:8"
.gate SB_DFFE C=common.led_blink.clk D=$abc$44715$techmap$techmap\common.pb.$procmux$12992.$reduce_or$/home/mb/fpga-toolchain/yosys/bin/../share/yosys/techmap.v:441$18840_Y E=$abc$44715$auto$dff2dffe.cc:175:make_patterns_logic$30676 Q=common.pb.spitx_ctrl_reply_data[16]
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:604|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:8"
.gate SB_DFFE C=common.led_blink.clk D=$abc$44715$techmap$techmap\common.pb.$procmux$12992.$reduce_or$/home/mb/fpga-toolchain/yosys/bin/../share/yosys/techmap.v:441$18841_Y E=$abc$44715$auto$dff2dffe.cc:175:make_patterns_logic$30676 Q=common.pb.spitx_ctrl_reply_data[17]
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:604|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:8"
.gate SB_DFFE C=common.led_blink.clk D=$abc$44715$techmap$techmap\common.pb.$procmux$12992.$reduce_or$/home/mb/fpga-toolchain/yosys/bin/../share/yosys/techmap.v:441$18842_Y E=$abc$44715$auto$dff2dffe.cc:175:make_patterns_logic$30676 Q=common.pb.spitx_ctrl_reply_data[18]
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:604|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:8"
.gate SB_DFFE C=common.led_blink.clk D=$abc$44715$techmap$techmap\common.pb.$procmux$12992.$reduce_or$/home/mb/fpga-toolchain/yosys/bin/../share/yosys/techmap.v:441$18843_Y E=$abc$44715$auto$dff2dffe.cc:175:make_patterns_logic$30676 Q=common.pb.spitx_ctrl_reply_data[19]
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:604|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:8"
.gate SB_DFFE C=common.led_blink.clk D=$abc$44715$techmap$techmap\common.pb.$procmux$12992.$reduce_or$/home/mb/fpga-toolchain/yosys/bin/../share/yosys/techmap.v:441$18844_Y E=$abc$44715$auto$dff2dffe.cc:175:make_patterns_logic$30676 Q=common.pb.spitx_ctrl_reply_data[20]
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:604|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:8"
.gate SB_DFFE C=common.led_blink.clk D=$abc$44715$techmap$techmap\common.pb.$procmux$12992.$reduce_or$/home/mb/fpga-toolchain/yosys/bin/../share/yosys/techmap.v:441$18845_Y E=$abc$44715$auto$dff2dffe.cc:175:make_patterns_logic$30676 Q=common.pb.spitx_ctrl_reply_data[21]
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:604|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:8"
.gate SB_DFFE C=common.led_blink.clk D=$abc$44715$techmap$techmap\common.pb.$procmux$12992.$reduce_or$/home/mb/fpga-toolchain/yosys/bin/../share/yosys/techmap.v:441$18846_Y E=$abc$44715$auto$dff2dffe.cc:175:make_patterns_logic$30676 Q=common.pb.spitx_ctrl_reply_data[22]
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:604|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:8"
.gate SB_DFFE C=common.led_blink.clk D=$abc$44715$techmap$techmap\common.pb.$procmux$12992.$reduce_or$/home/mb/fpga-toolchain/yosys/bin/../share/yosys/techmap.v:441$18847_Y E=$abc$44715$auto$dff2dffe.cc:175:make_patterns_logic$30676 Q=common.pb.spitx_ctrl_reply_data[23]
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:604|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:8"
.gate SB_DFFE C=common.led_blink.clk D=$false E=$abc$44715$auto$dff2dffe.cc:175:make_patterns_logic$30642 Q=common.pb.spitx_ctrl_reply_data[24]
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:604|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:8"
.gate SB_DFFE C=common.led_blink.clk D=$false E=$abc$44715$auto$dff2dffe.cc:175:make_patterns_logic$30642 Q=common.pb.spitx_ctrl_reply_data[25]
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:604|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:8"
.gate SB_DFFE C=common.led_blink.clk D=$false E=$abc$44715$auto$dff2dffe.cc:175:make_patterns_logic$30642 Q=common.pb.spitx_ctrl_reply_data[26]
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:604|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:8"
.gate SB_DFFE C=common.led_blink.clk D=$false E=$abc$44715$auto$dff2dffe.cc:175:make_patterns_logic$30642 Q=common.pb.spitx_ctrl_reply_data[27]
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:604|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:8"
.gate SB_DFFE C=common.led_blink.clk D=$false E=$abc$44715$auto$dff2dffe.cc:175:make_patterns_logic$30642 Q=common.pb.spitx_ctrl_reply_data[28]
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:604|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:8"
.gate SB_DFFE C=common.led_blink.clk D=$false E=$abc$44715$auto$dff2dffe.cc:175:make_patterns_logic$30642 Q=common.pb.spitx_ctrl_reply_data[29]
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:604|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:8"
.gate SB_DFFE C=common.led_blink.clk D=$false E=$abc$44715$auto$dff2dffe.cc:175:make_patterns_logic$30642 Q=common.pb.spitx_ctrl_reply_data[30]
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:604|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:8"
.gate SB_DFFE C=common.led_blink.clk D=$false E=$abc$44715$auto$dff2dffe.cc:175:make_patterns_logic$30642 Q=common.pb.spitx_ctrl_reply_data[31]
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:604|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:8"
.gate SB_DFFE C=common.led_blink.clk D=$abc$44715$techmap$techmap\common.pb.$procmux$14211.$reduce_or$/home/mb/fpga-toolchain/yosys/bin/../share/yosys/techmap.v:441$18295_Y E=$abc$44715$auto$dff2dffe.cc:175:make_patterns_logic$30676 Q=common.pb.spitx_ctrl_reply[0]
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:604|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:8"
.gate SB_DFFE C=common.led_blink.clk D=$abc$44715$techmap$techmap\common.pb.$procmux$14211.$reduce_or$/home/mb/fpga-toolchain/yosys/bin/../share/yosys/techmap.v:441$18296_Y E=$abc$44715$auto$dff2dffe.cc:175:make_patterns_logic$30676 Q=common.pb.spitx_ctrl_reply[1]
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:604|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:8"
.gate SB_DFFE C=common.led_blink.clk D=$abc$44715$techmap$techmap\common.pb.$procmux$14211.$reduce_or$/home/mb/fpga-toolchain/yosys/bin/../share/yosys/techmap.v:441$18297_Y E=$abc$44715$auto$dff2dffe.cc:175:make_patterns_logic$30676 Q=common.pb.spitx_ctrl_reply[2]
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:604|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:8"
.gate SB_DFFE C=common.led_blink.clk D=$abc$44715$techmap$techmap\common.pb.$procmux$14211.$reduce_or$/home/mb/fpga-toolchain/yosys/bin/../share/yosys/techmap.v:441$18298_Y E=$abc$44715$auto$dff2dffe.cc:175:make_patterns_logic$30676 Q=common.pb.spitx_ctrl_reply[3]
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:604|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:8"
.gate SB_DFFE C=common.led_blink.clk D=$abc$44715$techmap$techmap\common.pb.$procmux$14211.$reduce_or$/home/mb/fpga-toolchain/yosys/bin/../share/yosys/techmap.v:441$18299_Y E=$abc$44715$auto$dff2dffe.cc:175:make_patterns_logic$30676 Q=common.pb.spitx_ctrl_reply[4]
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:604|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:8"
.gate SB_DFFE C=common.led_blink.clk D=$abc$44715$techmap$techmap\common.pb.$procmux$14211.$reduce_or$/home/mb/fpga-toolchain/yosys/bin/../share/yosys/techmap.v:441$18300_Y E=$abc$44715$auto$dff2dffe.cc:175:make_patterns_logic$30676 Q=common.pb.spitx_ctrl_reply[5]
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:604|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:8"
.gate SB_DFFE C=common.led_blink.clk D=$abc$44715$techmap$techmap\common.pb.$procmux$14211.$reduce_or$/home/mb/fpga-toolchain/yosys/bin/../share/yosys/techmap.v:441$18301_Y E=$abc$44715$auto$dff2dffe.cc:175:make_patterns_logic$30676 Q=common.pb.spitx_ctrl_reply[6]
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:604|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:8"
.gate SB_DFFE C=common.led_blink.clk D=$abc$44715$techmap$techmap\common.pb.$procmux$14211.$reduce_or$/home/mb/fpga-toolchain/yosys/bin/../share/yosys/techmap.v:441$18302_Y E=$abc$44715$auto$dff2dffe.cc:175:make_patterns_logic$30676 Q=common.pb.spitx_ctrl_reply[7]
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:604|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:8"
.gate SB_DFFE C=common.led_blink.clk D=$abc$44715$techmap$techmap\common.pb.$procmux$14236.$and$/home/mb/fpga-toolchain/yosys/bin/../share/yosys/techmap.v:434$17950_Y E=$abc$44715$auto$dff2dffe.cc:175:make_patterns_logic$32104 Q=common.pb.spirx_lencalc_new
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:604|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:8"
.gate SB_DFFE C=common.led_blink.clk D=$abc$44715$techmap$techmap\common.pb.$procmux$14250.$and$/home/mb/fpga-toolchain/yosys/bin/../share/yosys/techmap.v:434$17895_Y[0] E=$abc$44715$auto$dff2dffe.cc:175:make_patterns_logic$32104 Q=common.pb.spirx_lencalc_byte[0]
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:604|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:8"
.gate SB_DFFE C=common.led_blink.clk D=$abc$44715$techmap$techmap\common.pb.$procmux$14250.$and$/home/mb/fpga-toolchain/yosys/bin/../share/yosys/techmap.v:434$17895_Y[1] E=$abc$44715$auto$dff2dffe.cc:175:make_patterns_logic$32104 Q=common.pb.spirx_lencalc_byte[1]
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:604|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:8"
.gate SB_DFFE C=common.led_blink.clk D=$abc$44715$techmap$techmap\common.pb.$procmux$14250.$and$/home/mb/fpga-toolchain/yosys/bin/../share/yosys/techmap.v:434$17895_Y[2] E=$abc$44715$auto$dff2dffe.cc:175:make_patterns_logic$32104 Q=common.pb.spirx_lencalc_byte[2]
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:604|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:8"
.gate SB_DFFE C=common.led_blink.clk D=$abc$44715$techmap$techmap\common.pb.$procmux$14250.$and$/home/mb/fpga-toolchain/yosys/bin/../share/yosys/techmap.v:434$17895_Y[3] E=$abc$44715$auto$dff2dffe.cc:175:make_patterns_logic$32104 Q=common.pb.spirx_lencalc_byte[3]
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:604|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:8"
.gate SB_DFFE C=common.led_blink.clk D=$abc$44715$techmap$techmap\common.pb.$procmux$14250.$and$/home/mb/fpga-toolchain/yosys/bin/../share/yosys/techmap.v:434$17895_Y[4] E=$abc$44715$auto$dff2dffe.cc:175:make_patterns_logic$32104 Q=common.pb.spirx_lencalc_byte[4]
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:604|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:8"
.gate SB_DFFE C=common.led_blink.clk D=$abc$44715$techmap$techmap\common.pb.$procmux$14250.$and$/home/mb/fpga-toolchain/yosys/bin/../share/yosys/techmap.v:434$17895_Y[5] E=$abc$44715$auto$dff2dffe.cc:175:make_patterns_logic$32104 Q=common.pb.spirx_lencalc_byte[5]
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:604|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:8"
.gate SB_DFFE C=common.led_blink.clk D=$abc$44715$techmap$techmap\common.pb.$procmux$14250.$and$/home/mb/fpga-toolchain/yosys/bin/../share/yosys/techmap.v:434$17895_Y[6] E=$abc$44715$auto$dff2dffe.cc:175:make_patterns_logic$32104 Q=common.pb.spirx_lencalc_byte[6]
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:604|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:8"
.gate SB_DFFE C=common.led_blink.clk D=$abc$44715$techmap$techmap\common.pb.$procmux$14250.$and$/home/mb/fpga-toolchain/yosys/bin/../share/yosys/techmap.v:434$17895_Y[7] E=$abc$44715$auto$dff2dffe.cc:175:make_patterns_logic$32104 Q=common.pb.spirx_lencalc_byte[7]
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:604|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:8"
.gate SB_DFFSR C=common.led_blink.clk D=$abc$44715$techmap$techmap\common.pb.$procmux$14257.$ternary$/home/mb/fpga-toolchain/yosys/bin/../share/yosys/techmap.v:445$18549_Y Q=common.pb.spirx_lencalc_n_reset R=$abc$44715$auto$rtlil.cc:1969:NotGate$44101
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:604|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:2"
.gate SB_DFFE C=common.led_blink.clk D=$abc$44715$techmap\common.pb.$0\spirx_ctrl_crcerr[1:0][0] E=$abc$44715$auto$dff2dffe.cc:175:make_patterns_logic$32301 Q=common.pb.spirx_ctrl_crcerr[0]
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:604|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:8"
.gate SB_DFFE C=common.led_blink.clk D=common.pb.spirx_ctrl_crcerr[0] E=$abc$44715$auto$dff2dffe.cc:175:make_patterns_logic$32343 Q=common.pb.spirx_ctrl_crcerr[1]
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:604|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:8"
.gate SB_DFFE C=common.led_blink.clk D=$abc$44715$techmap$techmap\common.pb.$procmux$14301.$reduce_or$/home/mb/fpga-toolchain/yosys/bin/../share/yosys/techmap.v:441$17897_Y E=$abc$44715$auto$dff2dffe.cc:175:make_patterns_logic$32364 Q=common.pb.spirx_crc[0]
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:604|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:8"
.gate SB_DFFE C=common.led_blink.clk D=$abc$44715$techmap$techmap\common.pb.$procmux$14301.$reduce_or$/home/mb/fpga-toolchain/yosys/bin/../share/yosys/techmap.v:441$17898_Y E=$abc$44715$auto$dff2dffe.cc:175:make_patterns_logic$32364 Q=common.pb.spirx_crc[1]
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:604|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:8"
.gate SB_DFFE C=common.led_blink.clk D=$abc$44715$techmap$techmap\common.pb.$procmux$14301.$reduce_or$/home/mb/fpga-toolchain/yosys/bin/../share/yosys/techmap.v:441$17899_Y E=$abc$44715$auto$dff2dffe.cc:175:make_patterns_logic$32364 Q=common.pb.spirx_crc[2]
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:604|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:8"
.gate SB_DFFE C=common.led_blink.clk D=$abc$44715$techmap$techmap\common.pb.$procmux$14301.$reduce_or$/home/mb/fpga-toolchain/yosys/bin/../share/yosys/techmap.v:441$17900_Y E=$abc$44715$auto$dff2dffe.cc:175:make_patterns_logic$32364 Q=common.pb.spirx_crc[3]
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:604|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:8"
.gate SB_DFFE C=common.led_blink.clk D=$abc$44715$techmap$techmap\common.pb.$procmux$14301.$reduce_or$/home/mb/fpga-toolchain/yosys/bin/../share/yosys/techmap.v:441$17901_Y E=$abc$44715$auto$dff2dffe.cc:175:make_patterns_logic$32364 Q=common.pb.spirx_crc[4]
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:604|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:8"
.gate SB_DFFE C=common.led_blink.clk D=$abc$44715$techmap$techmap\common.pb.$procmux$14301.$reduce_or$/home/mb/fpga-toolchain/yosys/bin/../share/yosys/techmap.v:441$17902_Y E=$abc$44715$auto$dff2dffe.cc:175:make_patterns_logic$32364 Q=common.pb.spirx_crc[5]
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:604|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:8"
.gate SB_DFFE C=common.led_blink.clk D=$abc$44715$techmap$techmap\common.pb.$procmux$14301.$reduce_or$/home/mb/fpga-toolchain/yosys/bin/../share/yosys/techmap.v:441$17903_Y E=$abc$44715$auto$dff2dffe.cc:175:make_patterns_logic$32364 Q=common.pb.spirx_crc[6]
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:604|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:8"
.gate SB_DFFE C=common.led_blink.clk D=$abc$44715$techmap$techmap\common.pb.$procmux$14301.$reduce_or$/home/mb/fpga-toolchain/yosys/bin/../share/yosys/techmap.v:441$17904_Y E=$abc$44715$auto$dff2dffe.cc:175:make_patterns_logic$32364 Q=common.pb.spirx_crc[7]
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:604|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:8"
.gate SB_DFFSR C=common.led_blink.clk D=$abc$44715$techmap$techmap\common.pb.$procmux$14316.$ternary$/home/mb/fpga-toolchain/yosys/bin/../share/yosys/techmap.v:445$18472_Y[0] Q=common.pb.spirx_ctrl_data[0] R=$abc$44715$auto$rtlil.cc:1969:NotGate$44101
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:604|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:2"
.gate SB_DFFSR C=common.led_blink.clk D=$abc$44715$techmap$techmap\common.pb.$procmux$14316.$ternary$/home/mb/fpga-toolchain/yosys/bin/../share/yosys/techmap.v:445$18472_Y[1] Q=common.pb.spirx_ctrl_data[1] R=$abc$44715$auto$rtlil.cc:1969:NotGate$44101
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:604|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:2"
.gate SB_DFFSR C=common.led_blink.clk D=$abc$44715$techmap$techmap\common.pb.$procmux$14316.$ternary$/home/mb/fpga-toolchain/yosys/bin/../share/yosys/techmap.v:445$18472_Y[2] Q=common.pb.spirx_ctrl_data[2] R=$abc$44715$auto$rtlil.cc:1969:NotGate$44101
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:604|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:2"
.gate SB_DFFSR C=common.led_blink.clk D=$abc$44715$techmap$techmap\common.pb.$procmux$14316.$ternary$/home/mb/fpga-toolchain/yosys/bin/../share/yosys/techmap.v:445$18472_Y[3] Q=common.pb.spirx_ctrl_data[3] R=$abc$44715$auto$rtlil.cc:1969:NotGate$44101
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:604|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:2"
.gate SB_DFFSR C=common.led_blink.clk D=$abc$44715$techmap$techmap\common.pb.$procmux$14316.$ternary$/home/mb/fpga-toolchain/yosys/bin/../share/yosys/techmap.v:445$18472_Y[4] Q=common.pb.spirx_ctrl_data[4] R=$abc$44715$auto$rtlil.cc:1969:NotGate$44101
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:604|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:2"
.gate SB_DFFSR C=common.led_blink.clk D=$abc$44715$techmap$techmap\common.pb.$procmux$14316.$ternary$/home/mb/fpga-toolchain/yosys/bin/../share/yosys/techmap.v:445$18472_Y[5] Q=common.pb.spirx_ctrl_data[5] R=$abc$44715$auto$rtlil.cc:1969:NotGate$44101
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:604|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:2"
.gate SB_DFFSR C=common.led_blink.clk D=$abc$44715$techmap$techmap\common.pb.$procmux$14316.$ternary$/home/mb/fpga-toolchain/yosys/bin/../share/yosys/techmap.v:445$18472_Y[6] Q=common.pb.spirx_ctrl_data[6] R=$abc$44715$auto$rtlil.cc:1969:NotGate$44101
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:604|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:2"
.gate SB_DFFSR C=common.led_blink.clk D=$abc$44715$techmap$techmap\common.pb.$procmux$14316.$ternary$/home/mb/fpga-toolchain/yosys/bin/../share/yosys/techmap.v:445$18472_Y[7] Q=common.pb.spirx_ctrl_data[7] R=$abc$44715$auto$rtlil.cc:1969:NotGate$44101
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:604|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:2"
.gate SB_DFFSR C=common.led_blink.clk D=$abc$44715$techmap$techmap\common.pb.$procmux$14316.$ternary$/home/mb/fpga-toolchain/yosys/bin/../share/yosys/techmap.v:445$18472_Y[8] Q=common.pb.spirx_ctrl_data[8] R=$abc$44715$auto$rtlil.cc:1969:NotGate$44101
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:604|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:2"
.gate SB_DFFSR C=common.led_blink.clk D=$abc$44715$techmap$techmap\common.pb.$procmux$14316.$ternary$/home/mb/fpga-toolchain/yosys/bin/../share/yosys/techmap.v:445$18472_Y[9] Q=common.pb.spirx_ctrl_data[9] R=$abc$44715$auto$rtlil.cc:1969:NotGate$44101
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:604|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:2"
.gate SB_DFFSR C=common.led_blink.clk D=$abc$44715$techmap$techmap\common.pb.$procmux$14316.$ternary$/home/mb/fpga-toolchain/yosys/bin/../share/yosys/techmap.v:445$18472_Y[10] Q=common.pb.spirx_ctrl_data[10] R=$abc$44715$auto$rtlil.cc:1969:NotGate$44101
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:604|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:2"
.gate SB_DFFSR C=common.led_blink.clk D=$abc$44715$techmap$techmap\common.pb.$procmux$14316.$ternary$/home/mb/fpga-toolchain/yosys/bin/../share/yosys/techmap.v:445$18472_Y[11] Q=common.pb.spirx_ctrl_data[11] R=$abc$44715$auto$rtlil.cc:1969:NotGate$44101
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:604|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:2"
.gate SB_DFFSR C=common.led_blink.clk D=$abc$44715$techmap$techmap\common.pb.$procmux$14316.$ternary$/home/mb/fpga-toolchain/yosys/bin/../share/yosys/techmap.v:445$18472_Y[12] Q=common.pb.spirx_ctrl_data[12] R=$abc$44715$auto$rtlil.cc:1969:NotGate$44101
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:604|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:2"
.gate SB_DFFSR C=common.led_blink.clk D=$abc$44715$techmap$techmap\common.pb.$procmux$14316.$ternary$/home/mb/fpga-toolchain/yosys/bin/../share/yosys/techmap.v:445$18472_Y[13] Q=common.pb.spirx_ctrl_data[13] R=$abc$44715$auto$rtlil.cc:1969:NotGate$44101
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:604|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:2"
.gate SB_DFFSR C=common.led_blink.clk D=$abc$44715$techmap$techmap\common.pb.$procmux$14316.$ternary$/home/mb/fpga-toolchain/yosys/bin/../share/yosys/techmap.v:445$18472_Y[14] Q=common.pb.spirx_ctrl_data[14] R=$abc$44715$auto$rtlil.cc:1969:NotGate$44101
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:604|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:2"
.gate SB_DFFSR C=common.led_blink.clk D=$abc$44715$techmap$techmap\common.pb.$procmux$14316.$ternary$/home/mb/fpga-toolchain/yosys/bin/../share/yosys/techmap.v:445$18472_Y[15] Q=common.pb.spirx_ctrl_data[15] R=$abc$44715$auto$rtlil.cc:1969:NotGate$44101
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:604|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:2"
.gate SB_DFFSR C=common.led_blink.clk D=$abc$44715$techmap$techmap\common.pb.$procmux$14316.$ternary$/home/mb/fpga-toolchain/yosys/bin/../share/yosys/techmap.v:445$18472_Y[16] Q=common.pb.spirx_ctrl_data[16] R=$abc$44715$auto$rtlil.cc:1969:NotGate$44101
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:604|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:2"
.gate SB_DFFSR C=common.led_blink.clk D=$abc$44715$techmap$techmap\common.pb.$procmux$14316.$ternary$/home/mb/fpga-toolchain/yosys/bin/../share/yosys/techmap.v:445$18472_Y[17] Q=common.pb.spirx_ctrl_data[17] R=$abc$44715$auto$rtlil.cc:1969:NotGate$44101
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:604|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:2"
.gate SB_DFFSR C=common.led_blink.clk D=$abc$44715$techmap$techmap\common.pb.$procmux$14316.$ternary$/home/mb/fpga-toolchain/yosys/bin/../share/yosys/techmap.v:445$18472_Y[18] Q=common.pb.spirx_ctrl_data[18] R=$abc$44715$auto$rtlil.cc:1969:NotGate$44101
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:604|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:2"
.gate SB_DFFSR C=common.led_blink.clk D=$abc$44715$techmap$techmap\common.pb.$procmux$14316.$ternary$/home/mb/fpga-toolchain/yosys/bin/../share/yosys/techmap.v:445$18472_Y[19] Q=common.pb.spirx_ctrl_data[19] R=$abc$44715$auto$rtlil.cc:1969:NotGate$44101
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:604|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:2"
.gate SB_DFFSR C=common.led_blink.clk D=$abc$44715$techmap$techmap\common.pb.$procmux$14316.$ternary$/home/mb/fpga-toolchain/yosys/bin/../share/yosys/techmap.v:445$18472_Y[20] Q=common.pb.spirx_ctrl_data[20] R=$abc$44715$auto$rtlil.cc:1969:NotGate$44101
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:604|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:2"
.gate SB_DFFSR C=common.led_blink.clk D=$abc$44715$techmap$techmap\common.pb.$procmux$14316.$ternary$/home/mb/fpga-toolchain/yosys/bin/../share/yosys/techmap.v:445$18472_Y[21] Q=common.pb.spirx_ctrl_data[21] R=$abc$44715$auto$rtlil.cc:1969:NotGate$44101
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:604|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:2"
.gate SB_DFFSR C=common.led_blink.clk D=$abc$44715$techmap$techmap\common.pb.$procmux$14316.$ternary$/home/mb/fpga-toolchain/yosys/bin/../share/yosys/techmap.v:445$18472_Y[22] Q=common.pb.spirx_ctrl_data[22] R=$abc$44715$auto$rtlil.cc:1969:NotGate$44101
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:604|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:2"
.gate SB_DFFSR C=common.led_blink.clk D=$abc$44715$techmap$techmap\common.pb.$procmux$14316.$ternary$/home/mb/fpga-toolchain/yosys/bin/../share/yosys/techmap.v:445$18472_Y[23] Q=common.pb.spirx_ctrl_data[23] R=$abc$44715$auto$rtlil.cc:1969:NotGate$44101
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:604|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:2"
.gate SB_DFFSR C=common.led_blink.clk D=$abc$44715$techmap$techmap\common.pb.$procmux$14335.$ternary$/home/mb/fpga-toolchain/yosys/bin/../share/yosys/techmap.v:445$18291_Y[0] Q=common.pb.spirx_ctrl[0] R=$abc$44715$auto$rtlil.cc:1969:NotGate$44101
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:604|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:2"
.gate SB_DFFSR C=common.led_blink.clk D=$abc$44715$techmap$techmap\common.pb.$procmux$14335.$ternary$/home/mb/fpga-toolchain/yosys/bin/../share/yosys/techmap.v:445$18291_Y[1] Q=common.pb.spirx_ctrl[1] R=$abc$44715$auto$rtlil.cc:1969:NotGate$44101
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:604|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:2"
.gate SB_DFFSR C=common.led_blink.clk D=$abc$44715$techmap$techmap\common.pb.$procmux$14335.$ternary$/home/mb/fpga-toolchain/yosys/bin/../share/yosys/techmap.v:445$18291_Y[2] Q=common.pb.spirx_ctrl[2] R=$abc$44715$auto$rtlil.cc:1969:NotGate$44101
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:604|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:2"
.gate SB_DFFSR C=common.led_blink.clk D=$abc$44715$techmap$techmap\common.pb.$procmux$14335.$ternary$/home/mb/fpga-toolchain/yosys/bin/../share/yosys/techmap.v:445$18291_Y[3] Q=common.pb.spirx_ctrl[3] R=$abc$44715$auto$rtlil.cc:1969:NotGate$44101
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:604|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:2"
.gate SB_DFFSR C=common.led_blink.clk D=$abc$44715$techmap$techmap\common.pb.$procmux$14335.$ternary$/home/mb/fpga-toolchain/yosys/bin/../share/yosys/techmap.v:445$18291_Y[4] Q=common.pb.spirx_ctrl[4] R=$abc$44715$auto$rtlil.cc:1969:NotGate$44101
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:604|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:2"
.gate SB_DFFSR C=common.led_blink.clk D=$abc$44715$techmap$techmap\common.pb.$procmux$14335.$ternary$/home/mb/fpga-toolchain/yosys/bin/../share/yosys/techmap.v:445$18291_Y[5] Q=common.pb.spirx_ctrl[5] R=$abc$44715$auto$rtlil.cc:1969:NotGate$44101
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:604|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:2"
.gate SB_DFFSR C=common.led_blink.clk D=$abc$44715$techmap$techmap\common.pb.$procmux$14335.$ternary$/home/mb/fpga-toolchain/yosys/bin/../share/yosys/techmap.v:445$18291_Y[6] Q=common.pb.spirx_ctrl[6] R=$abc$44715$auto$rtlil.cc:1969:NotGate$44101
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:604|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:2"
.gate SB_DFFSR C=common.led_blink.clk D=$abc$44715$techmap$techmap\common.pb.$procmux$14335.$ternary$/home/mb/fpga-toolchain/yosys/bin/../share/yosys/techmap.v:445$18291_Y[7] Q=common.pb.spirx_ctrl[7] R=$abc$44715$auto$rtlil.cc:1969:NotGate$44101
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:604|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:2"
.gate SB_DFFE C=common.led_blink.clk D=$abc$44715$techmap$techmap\common.pb.$procmux$14359.$reduce_or$/home/mb/fpga-toolchain/yosys/bin/../share/yosys/techmap.v:441$18295_Y E=$abc$44715$auto$dff2dffe.cc:175:make_patterns_logic$32516 Q=common.pb.spirx_bytecount[0]
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:604|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:8"
.gate SB_DFFE C=common.led_blink.clk D=$abc$44715$techmap$techmap\common.pb.$procmux$14359.$reduce_or$/home/mb/fpga-toolchain/yosys/bin/../share/yosys/techmap.v:441$18296_Y E=$abc$44715$auto$dff2dffe.cc:175:make_patterns_logic$32516 Q=common.pb.spirx_bytecount[1]
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:604|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:8"
.gate SB_DFFE C=common.led_blink.clk D=$abc$44715$techmap$techmap\common.pb.$procmux$14359.$reduce_or$/home/mb/fpga-toolchain/yosys/bin/../share/yosys/techmap.v:441$18297_Y E=$abc$44715$auto$dff2dffe.cc:175:make_patterns_logic$32516 Q=common.pb.spirx_bytecount[2]
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:604|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:8"
.gate SB_DFFE C=common.led_blink.clk D=$abc$44715$techmap$techmap\common.pb.$procmux$14359.$reduce_or$/home/mb/fpga-toolchain/yosys/bin/../share/yosys/techmap.v:441$18298_Y E=$abc$44715$auto$dff2dffe.cc:175:make_patterns_logic$32516 Q=common.pb.spirx_bytecount[3]
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:604|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:8"
.gate SB_DFFE C=common.led_blink.clk D=$abc$44715$techmap$techmap\common.pb.$procmux$14359.$reduce_or$/home/mb/fpga-toolchain/yosys/bin/../share/yosys/techmap.v:441$18299_Y E=$abc$44715$auto$dff2dffe.cc:175:make_patterns_logic$32516 Q=common.pb.spirx_bytecount[4]
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:604|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:8"
.gate SB_DFFE C=common.led_blink.clk D=$abc$44715$techmap$techmap\common.pb.$procmux$14359.$reduce_or$/home/mb/fpga-toolchain/yosys/bin/../share/yosys/techmap.v:441$18300_Y E=$abc$44715$auto$dff2dffe.cc:175:make_patterns_logic$32516 Q=common.pb.spirx_bytecount[5]
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:604|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:8"
.gate SB_DFFE C=common.led_blink.clk D=$abc$44715$techmap$techmap\common.pb.$procmux$14359.$reduce_or$/home/mb/fpga-toolchain/yosys/bin/../share/yosys/techmap.v:441$18301_Y E=$abc$44715$auto$dff2dffe.cc:175:make_patterns_logic$32516 Q=common.pb.spirx_bytecount[6]
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:604|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:8"
.gate SB_DFFE C=common.led_blink.clk D=$abc$44715$techmap$techmap\common.pb.$procmux$14359.$reduce_or$/home/mb/fpga-toolchain/yosys/bin/../share/yosys/techmap.v:441$18302_Y E=$abc$44715$auto$dff2dffe.cc:175:make_patterns_logic$32516 Q=common.pb.spirx_bytecount[7]
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:604|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:8"
.gate SB_DFFE C=common.led_blink.clk D=$abc$44715$techmap$techmap\common.pb.$procmux$14395.$reduce_or$/home/mb/fpga-toolchain/yosys/bin/../share/yosys/techmap.v:441$17952_Y E=$abc$44715$auto$dff2dffe.cc:175:make_patterns_logic$32104 Q=common.pb.spirx_len_valid
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:604|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:8"
.gate SB_DFFE C=common.led_blink.clk D=$abc$44715$techmap$techmap\common.pb.$procmux$14418.$reduce_or$/home/mb/fpga-toolchain/yosys/bin/../share/yosys/techmap.v:441$17897_Y E=$abc$44715$auto$dff2dffe.cc:175:make_patterns_logic$32104 Q=common.pb.spirx_len[0]
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:604|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:8"
.gate SB_DFFE C=common.led_blink.clk D=$abc$44715$techmap$techmap\common.pb.$procmux$14418.$reduce_or$/home/mb/fpga-toolchain/yosys/bin/../share/yosys/techmap.v:441$17898_Y E=$abc$44715$auto$dff2dffe.cc:175:make_patterns_logic$32104 Q=common.pb.spirx_len[1]
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:604|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:8"
.gate SB_DFFE C=common.led_blink.clk D=$abc$44715$techmap$techmap\common.pb.$procmux$14418.$reduce_or$/home/mb/fpga-toolchain/yosys/bin/../share/yosys/techmap.v:441$17899_Y E=$abc$44715$auto$dff2dffe.cc:175:make_patterns_logic$32104 Q=common.pb.spirx_len[2]
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:604|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:8"
.gate SB_DFFE C=common.led_blink.clk D=$abc$44715$techmap$techmap\common.pb.$procmux$14418.$reduce_or$/home/mb/fpga-toolchain/yosys/bin/../share/yosys/techmap.v:441$17900_Y E=$abc$44715$auto$dff2dffe.cc:175:make_patterns_logic$32104 Q=common.pb.spirx_len[3]
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:604|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:8"
.gate SB_DFFE C=common.led_blink.clk D=$abc$44715$techmap$techmap\common.pb.$procmux$14418.$reduce_or$/home/mb/fpga-toolchain/yosys/bin/../share/yosys/techmap.v:441$17901_Y E=$abc$44715$auto$dff2dffe.cc:175:make_patterns_logic$32104 Q=common.pb.spirx_len[4]
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:604|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:8"
.gate SB_DFFE C=common.led_blink.clk D=$abc$44715$techmap$techmap\common.pb.$procmux$14418.$reduce_or$/home/mb/fpga-toolchain/yosys/bin/../share/yosys/techmap.v:441$17902_Y E=$abc$44715$auto$dff2dffe.cc:175:make_patterns_logic$32104 Q=common.pb.spirx_len[5]
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:604|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:8"
.gate SB_DFFE C=common.led_blink.clk D=$abc$44715$techmap$techmap\common.pb.$procmux$14418.$reduce_or$/home/mb/fpga-toolchain/yosys/bin/../share/yosys/techmap.v:441$17903_Y E=$abc$44715$auto$dff2dffe.cc:175:make_patterns_logic$32104 Q=common.pb.spirx_len[6]
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:604|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:8"
.gate SB_DFFE C=common.led_blink.clk D=$abc$44715$techmap$techmap\common.pb.$procmux$14418.$reduce_or$/home/mb/fpga-toolchain/yosys/bin/../share/yosys/techmap.v:441$17904_Y E=$abc$44715$auto$dff2dffe.cc:175:make_patterns_logic$32104 Q=common.pb.spirx_len[7]
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:604|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:8"
.gate SB_DFFSR C=common.led_blink.clk D=$abc$44715$techmap$techmap\common.pb.$procmux$14444.$ternary$/home/mb/fpga-toolchain/yosys/bin/../share/yosys/techmap.v:445$18186_Y[0] Q=common.pb.spirx_state[0] R=$abc$44715$auto$rtlil.cc:1969:NotGate$44101
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:604|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:2"
.gate SB_DFFSR C=common.led_blink.clk D=$abc$44715$techmap$techmap\common.pb.$procmux$14444.$ternary$/home/mb/fpga-toolchain/yosys/bin/../share/yosys/techmap.v:445$18186_Y[1] Q=common.pb.spirx_state[1] R=$abc$44715$auto$rtlil.cc:1969:NotGate$44101
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:604|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:2"
.gate SB_DFFSR C=common.led_blink.clk D=$abc$44715$techmap$techmap\common.pb.$procmux$14444.$ternary$/home/mb/fpga-toolchain/yosys/bin/../share/yosys/techmap.v:445$18186_Y[2] Q=common.pb.spirx_state[2] R=$abc$44715$auto$rtlil.cc:1969:NotGate$44101
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:604|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:2"
.gate SB_DFFE C=common.led_blink.clk D=common.pb.spirx_ctrl_data[0] E=$abc$44715$auto$dff2dffe.cc:175:make_patterns_logic$32865 Q=common.pb.tsyn_clks[0]
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:604|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:8"
.gate SB_DFFE C=common.led_blink.clk D=common.pb.spirx_ctrl_data[1] E=$abc$44715$auto$dff2dffe.cc:175:make_patterns_logic$32865 Q=common.pb.tsyn_clks[1]
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:604|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:8"
.gate SB_DFFE C=common.led_blink.clk D=common.pb.spirx_ctrl_data[2] E=$abc$44715$auto$dff2dffe.cc:175:make_patterns_logic$32865 Q=common.pb.tsyn_clks[2]
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:604|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:8"
.gate SB_DFFE C=common.led_blink.clk D=common.pb.spirx_ctrl_data[3] E=$abc$44715$auto$dff2dffe.cc:175:make_patterns_logic$32865 Q=common.pb.tsyn_clks[3]
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:604|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:8"
.gate SB_DFFE C=common.led_blink.clk D=common.pb.spirx_ctrl_data[4] E=$abc$44715$auto$dff2dffe.cc:175:make_patterns_logic$32865 Q=common.pb.tsyn_clks[4]
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:604|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:8"
.gate SB_DFFE C=common.led_blink.clk D=$abc$44715$auto$simplemap.cc:309:simplemap_lut$26877[0] E=$abc$44715$auto$dff2dffe.cc:175:make_patterns_logic$32865 Q=common.pb.tsyn_clks[5]
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:604|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:8"
.gate SB_DFFE C=common.led_blink.clk D=$techmap\common.pb.$0\tsyn_clks[23:0][6] E=$abc$44715$auto$dff2dffe.cc:175:make_patterns_logic$32865 Q=common.pb.tsyn_clks[6]
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:604|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:8"
.gate SB_DFFE C=common.led_blink.clk D=$techmap\common.pb.$0\tsyn_clks[23:0][7] E=$abc$44715$auto$dff2dffe.cc:175:make_patterns_logic$32865 Q=common.pb.tsyn_clks[7]
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:604|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:8"
.gate SB_DFFE C=common.led_blink.clk D=$techmap\common.pb.$0\tsyn_clks[23:0][8] E=$abc$44715$auto$dff2dffe.cc:175:make_patterns_logic$32865 Q=common.pb.tsyn_clks[8]
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:604|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:8"
.gate SB_DFFE C=common.led_blink.clk D=$techmap\common.pb.$0\tsyn_clks[23:0][9] E=$abc$44715$auto$dff2dffe.cc:175:make_patterns_logic$32865 Q=common.pb.tsyn_clks[9]
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:604|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:8"
.gate SB_DFFE C=common.led_blink.clk D=$techmap\common.pb.$0\tsyn_clks[23:0][10] E=$abc$44715$auto$dff2dffe.cc:175:make_patterns_logic$32865 Q=common.pb.tsyn_clks[10]
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:604|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:8"
.gate SB_DFFE C=common.led_blink.clk D=$techmap\common.pb.$0\tsyn_clks[23:0][11] E=$abc$44715$auto$dff2dffe.cc:175:make_patterns_logic$32865 Q=common.pb.tsyn_clks[11]
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:604|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:8"
.gate SB_DFFE C=common.led_blink.clk D=$techmap\common.pb.$0\tsyn_clks[23:0][12] E=$abc$44715$auto$dff2dffe.cc:175:make_patterns_logic$32865 Q=common.pb.tsyn_clks[12]
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:604|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:8"
.gate SB_DFFE C=common.led_blink.clk D=$techmap\common.pb.$0\tsyn_clks[23:0][13] E=$abc$44715$auto$dff2dffe.cc:175:make_patterns_logic$32865 Q=common.pb.tsyn_clks[13]
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:604|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:8"
.gate SB_DFFE C=common.led_blink.clk D=$techmap\common.pb.$0\tsyn_clks[23:0][14] E=$abc$44715$auto$dff2dffe.cc:175:make_patterns_logic$32865 Q=common.pb.tsyn_clks[14]
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:604|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:8"
.gate SB_DFFE C=common.led_blink.clk D=$techmap\common.pb.$0\tsyn_clks[23:0][15] E=$abc$44715$auto$dff2dffe.cc:175:make_patterns_logic$32865 Q=common.pb.tsyn_clks[15]
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:604|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:8"
.gate SB_DFFE C=common.led_blink.clk D=$techmap\common.pb.$0\tsyn_clks[23:0][16] E=$abc$44715$auto$dff2dffe.cc:175:make_patterns_logic$32865 Q=common.pb.tsyn_clks[16]
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:604|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:8"
.gate SB_DFFE C=common.led_blink.clk D=$techmap\common.pb.$0\tsyn_clks[23:0][17] E=$abc$44715$auto$dff2dffe.cc:175:make_patterns_logic$32865 Q=common.pb.tsyn_clks[17]
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:604|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:8"
.gate SB_DFFE C=common.led_blink.clk D=$techmap\common.pb.$0\tsyn_clks[23:0][18] E=$abc$44715$auto$dff2dffe.cc:175:make_patterns_logic$32865 Q=common.pb.tsyn_clks[18]
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:604|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:8"
.gate SB_DFFE C=common.led_blink.clk D=$techmap\common.pb.$0\tsyn_clks[23:0][19] E=$abc$44715$auto$dff2dffe.cc:175:make_patterns_logic$32865 Q=common.pb.tsyn_clks[19]
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:604|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:8"
.gate SB_DFFE C=common.led_blink.clk D=$techmap\common.pb.$0\tsyn_clks[23:0][20] E=$abc$44715$auto$dff2dffe.cc:175:make_patterns_logic$32865 Q=common.pb.tsyn_clks[20]
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:604|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:8"
.gate SB_DFFE C=common.led_blink.clk D=$techmap\common.pb.$0\tsyn_clks[23:0][21] E=$abc$44715$auto$dff2dffe.cc:175:make_patterns_logic$32865 Q=common.pb.tsyn_clks[21]
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:604|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:8"
.gate SB_DFFE C=common.led_blink.clk D=$techmap\common.pb.$0\tsyn_clks[23:0][22] E=$abc$44715$auto$dff2dffe.cc:175:make_patterns_logic$32865 Q=common.pb.tsyn_clks[22]
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:604|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:8"
.gate SB_DFFE C=common.led_blink.clk D=$techmap\common.pb.$0\tsyn_clks[23:0][23] E=$abc$44715$auto$dff2dffe.cc:175:make_patterns_logic$32865 Q=common.pb.tsyn_clks[23]
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:604|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:8"
.gate SB_DFFE C=common.led_blink.clk D=common.pb.spirx_ctrl_data[0] E=$abc$44715$auto$dff2dffe.cc:175:make_patterns_logic$32865 Q=common.pb.uart_clks_per_sym[0]
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:604|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:8"
.gate SB_DFFE C=common.led_blink.clk D=common.pb.spirx_ctrl_data[1] E=$abc$44715$auto$dff2dffe.cc:175:make_patterns_logic$32865 Q=common.pb.uart_clks_per_sym[1]
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:604|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:8"
.gate SB_DFFE C=common.led_blink.clk D=common.pb.spirx_ctrl_data[2] E=$abc$44715$auto$dff2dffe.cc:175:make_patterns_logic$32865 Q=common.pb.uart_clks_per_sym[2]
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:604|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:8"
.gate SB_DFFE C=common.led_blink.clk D=common.pb.spirx_ctrl_data[3] E=$abc$44715$auto$dff2dffe.cc:175:make_patterns_logic$32865 Q=common.pb.uart_clks_per_sym[3]
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:604|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:8"
.gate SB_DFFE C=common.led_blink.clk D=common.pb.spirx_ctrl_data[4] E=$abc$44715$auto$dff2dffe.cc:175:make_patterns_logic$32865 Q=common.pb.uart_clks_per_sym[4]
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:604|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:8"
.gate SB_DFFE C=common.led_blink.clk D=common.pb.spirx_ctrl_data[5] E=$abc$44715$auto$dff2dffe.cc:175:make_patterns_logic$32865 Q=common.pb.uart_clks_per_sym[5]
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:604|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:8"
.gate SB_DFFE C=common.led_blink.clk D=common.pb.spirx_ctrl_data[6] E=$abc$44715$auto$dff2dffe.cc:175:make_patterns_logic$32865 Q=common.pb.uart_clks_per_sym[6]
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:604|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:8"
.gate SB_DFFE C=common.led_blink.clk D=common.pb.spirx_ctrl_data[7] E=$abc$44715$auto$dff2dffe.cc:175:make_patterns_logic$32865 Q=common.pb.uart_clks_per_sym[7]
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:604|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:8"
.gate SB_DFFE C=common.led_blink.clk D=common.pb.spirx_ctrl_data[8] E=$abc$44715$auto$dff2dffe.cc:175:make_patterns_logic$32865 Q=common.pb.uart_clks_per_sym[8]
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:604|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:8"
.gate SB_DFFE C=common.led_blink.clk D=common.pb.spirx_ctrl_data[9] E=$abc$44715$auto$dff2dffe.cc:175:make_patterns_logic$32865 Q=common.pb.uart_clks_per_sym[9]
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:604|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:8"
.gate SB_DFFE C=common.led_blink.clk D=common.pb.spirx_ctrl_data[10] E=$abc$44715$auto$dff2dffe.cc:175:make_patterns_logic$32865 Q=common.pb.uart_clks_per_sym[10]
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:604|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:8"
.gate SB_DFFE C=common.led_blink.clk D=common.pb.spirx_ctrl_data[11] E=$abc$44715$auto$dff2dffe.cc:175:make_patterns_logic$32865 Q=common.pb.uart_clks_per_sym[11]
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:604|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:8"
.gate SB_DFFE C=common.led_blink.clk D=common.pb.spirx_ctrl_data[12] E=$abc$44715$auto$dff2dffe.cc:175:make_patterns_logic$32865 Q=common.pb.uart_clks_per_sym[12]
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:604|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:8"
.gate SB_DFFE C=common.led_blink.clk D=common.pb.spirx_ctrl_data[13] E=$abc$44715$auto$dff2dffe.cc:175:make_patterns_logic$32865 Q=common.pb.uart_clks_per_sym[13]
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:604|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:8"
.gate SB_DFFE C=common.led_blink.clk D=common.pb.spirx_ctrl_data[14] E=$abc$44715$auto$dff2dffe.cc:175:make_patterns_logic$32865 Q=common.pb.uart_clks_per_sym[14]
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:604|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:8"
.gate SB_DFFE C=common.led_blink.clk D=common.pb.spirx_ctrl_data[15] E=$abc$44715$auto$dff2dffe.cc:175:make_patterns_logic$32865 Q=common.pb.uart_clks_per_sym[15]
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:604|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:8"
.gate SB_DFFE C=common.led_blink.clk D=common.pb.spirx_ctrl_data[16] E=$abc$44715$auto$dff2dffe.cc:175:make_patterns_logic$32865 Q=common.pb.uart_clks_per_sym[16]
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:604|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:8"
.gate SB_DFFE C=common.led_blink.clk D=common.pb.spirx_ctrl_data[17] E=$abc$44715$auto$dff2dffe.cc:175:make_patterns_logic$32865 Q=common.pb.uart_clks_per_sym[17]
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:604|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:8"
.gate SB_DFFE C=common.led_blink.clk D=common.pb.spirx_ctrl_data[18] E=$abc$44715$auto$dff2dffe.cc:175:make_patterns_logic$32865 Q=common.pb.uart_clks_per_sym[18]
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:604|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:8"
.gate SB_DFFE C=common.led_blink.clk D=common.pb.spirx_ctrl_data[19] E=$abc$44715$auto$dff2dffe.cc:175:make_patterns_logic$32865 Q=common.pb.uart_clks_per_sym[19]
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:604|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:8"
.gate SB_DFFE C=common.led_blink.clk D=common.pb.spirx_ctrl_data[20] E=$abc$44715$auto$dff2dffe.cc:175:make_patterns_logic$32865 Q=common.pb.uart_clks_per_sym[20]
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:604|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:8"
.gate SB_DFFE C=common.led_blink.clk D=common.pb.spirx_ctrl_data[21] E=$abc$44715$auto$dff2dffe.cc:175:make_patterns_logic$32865 Q=common.pb.uart_clks_per_sym[21]
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:604|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:8"
.gate SB_DFFE C=common.led_blink.clk D=common.pb.spirx_ctrl_data[22] E=$abc$44715$auto$dff2dffe.cc:175:make_patterns_logic$32865 Q=common.pb.uart_clks_per_sym[22]
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:604|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:8"
.gate SB_DFFE C=common.led_blink.clk D=common.pb.spirx_ctrl_data[23] E=$abc$44715$auto$dff2dffe.cc:175:make_patterns_logic$32865 Q=common.pb.uart_clks_per_sym[23]
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:604|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:8"
.gate SB_DFFE C=common.led_blink.clk D=common.pb.rx_buf_overflow[0] E=$abc$44715$auto$dff2dffe.cc:175:make_patterns_logic$32343 Q=common.pb.rx_buf_overflow[1]
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:604|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:8"
.gate SB_DFFE C=common.led_blink.clk D=$abc$44715$techmap\common.pb.$0\tx_buf_overflow[1:0][0] E=$abc$44715$auto$dff2dffe.cc:175:make_patterns_logic$35227 Q=common.pb.tx_buf_overflow[0]
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:604|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:8"
.gate SB_DFFE C=common.led_blink.clk D=common.pb.tx_buf_overflow[0] E=$abc$44715$auto$dff2dffe.cc:175:make_patterns_logic$32343 Q=common.pb.tx_buf_overflow[1]
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:604|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:8"
.gate SB_DFFSR C=common.led_blink.clk D=$abc$44715$techmap$techmap\common.pb.$procmux$14541.$ternary$/home/mb/fpga-toolchain/yosys/bin/../share/yosys/techmap.v:445$17949_Y Q=common.pb.tx_buf_wr R=$abc$44715$auto$rtlil.cc:1969:NotGate$44101
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:604|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:2"
.gate SB_DFFSR C=common.led_blink.clk D=$abc$44715$techmap$techmap\common.pb.$procmux$14563.$ternary$/home/mb/fpga-toolchain/yosys/bin/../share/yosys/techmap.v:445$17894_Y[0] Q=common.pb.tx_buf_wr_data[0] R=$abc$44715$auto$rtlil.cc:1969:NotGate$44101
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:604|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:2"
.gate SB_DFFSR C=common.led_blink.clk D=$abc$44715$techmap$techmap\common.pb.$procmux$14563.$ternary$/home/mb/fpga-toolchain/yosys/bin/../share/yosys/techmap.v:445$17894_Y[1] Q=common.pb.tx_buf_wr_data[1] R=$abc$44715$auto$rtlil.cc:1969:NotGate$44101
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:604|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:2"
.gate SB_DFFSR C=common.led_blink.clk D=$abc$44715$techmap$techmap\common.pb.$procmux$14563.$ternary$/home/mb/fpga-toolchain/yosys/bin/../share/yosys/techmap.v:445$17894_Y[2] Q=common.pb.tx_buf_wr_data[2] R=$abc$44715$auto$rtlil.cc:1969:NotGate$44101
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:604|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:2"
.gate SB_DFFSR C=common.led_blink.clk D=$abc$44715$techmap$techmap\common.pb.$procmux$14563.$ternary$/home/mb/fpga-toolchain/yosys/bin/../share/yosys/techmap.v:445$17894_Y[3] Q=common.pb.tx_buf_wr_data[3] R=$abc$44715$auto$rtlil.cc:1969:NotGate$44101
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:604|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:2"
.gate SB_DFFSR C=common.led_blink.clk D=$abc$44715$techmap$techmap\common.pb.$procmux$14563.$ternary$/home/mb/fpga-toolchain/yosys/bin/../share/yosys/techmap.v:445$17894_Y[4] Q=common.pb.tx_buf_wr_data[4] R=$abc$44715$auto$rtlil.cc:1969:NotGate$44101
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:604|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:2"
.gate SB_DFFSR C=common.led_blink.clk D=$abc$44715$techmap$techmap\common.pb.$procmux$14563.$ternary$/home/mb/fpga-toolchain/yosys/bin/../share/yosys/techmap.v:445$17894_Y[5] Q=common.pb.tx_buf_wr_data[5] R=$abc$44715$auto$rtlil.cc:1969:NotGate$44101
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:604|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:2"
.gate SB_DFFSR C=common.led_blink.clk D=$abc$44715$techmap$techmap\common.pb.$procmux$14563.$ternary$/home/mb/fpga-toolchain/yosys/bin/../share/yosys/techmap.v:445$17894_Y[6] Q=common.pb.tx_buf_wr_data[6] R=$abc$44715$auto$rtlil.cc:1969:NotGate$44101
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:604|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:2"
.gate SB_DFFSR C=common.led_blink.clk D=$abc$44715$techmap$techmap\common.pb.$procmux$14563.$ternary$/home/mb/fpga-toolchain/yosys/bin/../share/yosys/techmap.v:445$17894_Y[7] Q=common.pb.tx_buf_wr_data[7] R=$abc$44715$auto$rtlil.cc:1969:NotGate$44101
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:604|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:2"
.gate SB_DFFSR C=common.led_blink.clk D=$abc$44715$techmap$techmap\common.pb.$procmux$14583.$ternary$/home/mb/fpga-toolchain/yosys/bin/../share/yosys/techmap.v:445$17894_Y[0] Q=common.pb.tx_buf_wr_addr[0] R=$abc$44715$auto$rtlil.cc:1969:NotGate$44101
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:604|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:2"
.gate SB_DFFSR C=common.led_blink.clk D=$abc$44715$techmap$techmap\common.pb.$procmux$14583.$ternary$/home/mb/fpga-toolchain/yosys/bin/../share/yosys/techmap.v:445$17894_Y[1] Q=common.pb.tx_buf_wr_addr[1] R=$abc$44715$auto$rtlil.cc:1969:NotGate$44101
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:604|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:2"
.gate SB_DFFSR C=common.led_blink.clk D=$abc$44715$techmap$techmap\common.pb.$procmux$14583.$ternary$/home/mb/fpga-toolchain/yosys/bin/../share/yosys/techmap.v:445$17894_Y[2] Q=common.pb.tx_buf_wr_addr[2] R=$abc$44715$auto$rtlil.cc:1969:NotGate$44101
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:604|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:2"
.gate SB_DFFSR C=common.led_blink.clk D=$abc$44715$techmap$techmap\common.pb.$procmux$14583.$ternary$/home/mb/fpga-toolchain/yosys/bin/../share/yosys/techmap.v:445$17894_Y[3] Q=common.pb.tx_buf_wr_addr[3] R=$abc$44715$auto$rtlil.cc:1969:NotGate$44101
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:604|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:2"
.gate SB_DFFSR C=common.led_blink.clk D=$abc$44715$techmap$techmap\common.pb.$procmux$14583.$ternary$/home/mb/fpga-toolchain/yosys/bin/../share/yosys/techmap.v:445$17894_Y[4] Q=common.pb.tx_buf_wr_addr[4] R=$abc$44715$auto$rtlil.cc:1969:NotGate$44101
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:604|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:2"
.gate SB_DFFSR C=common.led_blink.clk D=$abc$44715$techmap$techmap\common.pb.$procmux$14583.$ternary$/home/mb/fpga-toolchain/yosys/bin/../share/yosys/techmap.v:445$17894_Y[5] Q=common.pb.tx_buf_wr_addr[5] R=$abc$44715$auto$rtlil.cc:1969:NotGate$44101
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:604|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:2"
.gate SB_DFFSR C=common.led_blink.clk D=$abc$44715$techmap$techmap\common.pb.$procmux$14583.$ternary$/home/mb/fpga-toolchain/yosys/bin/../share/yosys/techmap.v:445$17894_Y[6] Q=common.pb.tx_buf_wr_addr[6] R=$abc$44715$auto$rtlil.cc:1969:NotGate$44101
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:604|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:2"
.gate SB_DFFSR C=common.led_blink.clk D=$abc$44715$techmap$techmap\common.pb.$procmux$14583.$ternary$/home/mb/fpga-toolchain/yosys/bin/../share/yosys/techmap.v:445$17894_Y[7] Q=common.pb.tx_buf_wr_addr[7] R=$abc$44715$auto$rtlil.cc:1969:NotGate$44101
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:604|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:2"
.gate SB_DFFE C=common.led_blink.clk D=$abc$44715$auto$dff2dffe.cc:158:make_patterns_logic$29217 E=$abc$44715$auto$dff2dffe.cc:175:make_patterns_logic$35298 Q=common.pb.softreset
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:604|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:8"
.gate SB_DFFESR C=common.led_blink.clk D=common.pb.softreset E=$abc$44715$auto$dff2dffe.cc:175:make_patterns_logic$32343 Q=common.pb.softreset_status R=$abc$44715$auto$dff2dffe.cc:158:make_patterns_logic$29217
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:604|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:8"
.gate SB_DFFESS C=common.led_blink.clk D=common.pb.n_reset E=$abc$44715$auto$dff2dffe.cc:175:make_patterns_logic$32343 Q=common.pb.n_hardreset_status S=$abc$44715$auto$dff2dffe.cc:158:make_patterns_logic$29217
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:604|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:8"
.gate SB_DFFE C=common.led_blink.clk D=$true E=$abc$44715$auto$dff2dffe.cc:175:make_patterns_logic$32343 Q=common.pb.n_poweronreset_status
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:604|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:8"
.gate SB_DFFESR C=common.led_blink.clk D=$abc$44715$techmap$techmap\common.pb.$procmux$12803.$reduce_or$/home/mb/fpga-toolchain/yosys/bin/../share/yosys/techmap.v:441$19144_Y E=$abc$44715$auto$dff2dffe.cc:175:make_patterns_logic$35460 Q=common.pb.spitx_crc[0] R=$abc$44715$auto$rtlil.cc:1969:NotGate$44101
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:881|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:8"
.gate SB_DFFESR C=common.led_blink.clk D=$abc$44715$techmap$techmap\common.pb.$procmux$12803.$reduce_or$/home/mb/fpga-toolchain/yosys/bin/../share/yosys/techmap.v:441$19145_Y E=$abc$44715$auto$dff2dffe.cc:175:make_patterns_logic$35460 Q=common.pb.spitx_crc[1] R=$abc$44715$auto$rtlil.cc:1969:NotGate$44101
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:881|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:8"
.gate SB_DFFESR C=common.led_blink.clk D=$abc$44715$techmap$techmap\common.pb.$procmux$12803.$reduce_or$/home/mb/fpga-toolchain/yosys/bin/../share/yosys/techmap.v:441$19146_Y E=$abc$44715$auto$dff2dffe.cc:175:make_patterns_logic$35460 Q=common.pb.spitx_crc[2] R=$abc$44715$auto$rtlil.cc:1969:NotGate$44101
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:881|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:8"
.gate SB_DFFESR C=common.led_blink.clk D=$abc$44715$techmap$techmap\common.pb.$procmux$12803.$reduce_or$/home/mb/fpga-toolchain/yosys/bin/../share/yosys/techmap.v:441$19147_Y E=$abc$44715$auto$dff2dffe.cc:175:make_patterns_logic$35460 Q=common.pb.spitx_crc[3] R=$abc$44715$auto$rtlil.cc:1969:NotGate$44101
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:881|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:8"
.gate SB_DFFESR C=common.led_blink.clk D=$abc$44715$techmap$techmap\common.pb.$procmux$12803.$reduce_or$/home/mb/fpga-toolchain/yosys/bin/../share/yosys/techmap.v:441$19148_Y E=$abc$44715$auto$dff2dffe.cc:175:make_patterns_logic$35460 Q=common.pb.spitx_crc[4] R=$abc$44715$auto$rtlil.cc:1969:NotGate$44101
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:881|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:8"
.gate SB_DFFESR C=common.led_blink.clk D=$abc$44715$techmap$techmap\common.pb.$procmux$12803.$reduce_or$/home/mb/fpga-toolchain/yosys/bin/../share/yosys/techmap.v:441$19149_Y E=$abc$44715$auto$dff2dffe.cc:175:make_patterns_logic$35460 Q=common.pb.spitx_crc[5] R=$abc$44715$auto$rtlil.cc:1969:NotGate$44101
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:881|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:8"
.gate SB_DFFESR C=common.led_blink.clk D=$abc$44715$techmap$techmap\common.pb.$procmux$12803.$reduce_or$/home/mb/fpga-toolchain/yosys/bin/../share/yosys/techmap.v:441$19150_Y E=$abc$44715$auto$dff2dffe.cc:175:make_patterns_logic$35460 Q=common.pb.spitx_crc[6] R=$abc$44715$auto$rtlil.cc:1969:NotGate$44101
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:881|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:8"
.gate SB_DFFESR C=common.led_blink.clk D=$abc$44715$techmap$techmap\common.pb.$procmux$12803.$reduce_or$/home/mb/fpga-toolchain/yosys/bin/../share/yosys/techmap.v:441$19151_Y E=$abc$44715$auto$dff2dffe.cc:175:make_patterns_logic$35460 Q=common.pb.spitx_crc[7] R=$abc$44715$auto$rtlil.cc:1969:NotGate$44101
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:881|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:8"
.gate SB_DFFESR C=common.led_blink.clk D=$abc$44715$techmap\common.pb.$procmux$12830_Y E=$abc$44715$auto$dff2dffe.cc:175:make_patterns_logic$35776 Q=common.pb.spitx_data_running R=$abc$44715$auto$rtlil.cc:1969:NotGate$44101
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:881|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:8"
.gate SB_DFFESR C=common.led_blink.clk D=$abc$44715$techmap\common.pb.$procmux$12855_Y E=$abc$44715$auto$dff2dffe.cc:175:make_patterns_logic$35804 Q=common.pb.spitx_ctrl_running R=$abc$44715$auto$rtlil.cc:1969:NotGate$44101
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:881|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:8"
.gate SB_DFFESR C=common.led_blink.clk D=$abc$44715$auto$simplemap.cc:168:logic_reduce$19575 E=$abc$44715$auto$dff2dffe.cc:175:make_patterns_logic$35906 Q=common.pb.spitx_tail R=$abc$44715$auto$rtlil.cc:1969:NotGate$44101
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:881|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:8"
.gate SB_DFFESR C=common.led_blink.clk D=$abc$44715$techmap\common.pb.$procmux$12896_Y[0] E=$abc$44715$auto$dff2dffe.cc:175:make_patterns_logic$36014 Q=common.pb.spitx_len[0] R=$abc$44715$auto$rtlil.cc:1969:NotGate$44101
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:881|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:8"
.gate SB_DFFESR C=common.led_blink.clk D=$abc$44715$techmap\common.pb.$procmux$12896_Y[1] E=$abc$44715$auto$dff2dffe.cc:175:make_patterns_logic$36148 Q=common.pb.spitx_len[1] R=$abc$44715$auto$rtlil.cc:1969:NotGate$44101
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:881|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:8"
.gate SB_DFFESR C=common.led_blink.clk D=$abc$44715$techmap\common.pb.$procmux$12896_Y[2] E=$abc$44715$auto$dff2dffe.cc:175:make_patterns_logic$36014 Q=common.pb.spitx_len[2] R=$abc$44715$auto$rtlil.cc:1969:NotGate$44101
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:881|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:8"
.gate SB_DFFESR C=common.led_blink.clk D=$abc$44715$techmap\common.pb.$procmux$12896_Y[3] E=$abc$44715$auto$dff2dffe.cc:175:make_patterns_logic$36014 Q=common.pb.spitx_len[3] R=$abc$44715$auto$rtlil.cc:1969:NotGate$44101
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:881|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:8"
.gate SB_DFFESR C=common.led_blink.clk D=$abc$44715$techmap\common.pb.$procmux$12896_Y[4] E=$abc$44715$auto$dff2dffe.cc:175:make_patterns_logic$36014 Q=common.pb.spitx_len[4] R=$abc$44715$auto$rtlil.cc:1969:NotGate$44101
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:881|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:8"
.gate SB_DFFESR C=common.led_blink.clk D=$abc$44715$techmap\common.pb.$procmux$12896_Y[5] E=$abc$44715$auto$dff2dffe.cc:175:make_patterns_logic$36014 Q=common.pb.spitx_len[5] R=$abc$44715$auto$rtlil.cc:1969:NotGate$44101
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:881|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:8"
.gate SB_DFFESR C=common.led_blink.clk D=$abc$44715$techmap\common.pb.$procmux$12896_Y[6] E=$abc$44715$auto$dff2dffe.cc:175:make_patterns_logic$36014 Q=common.pb.spitx_len[6] R=$abc$44715$auto$rtlil.cc:1969:NotGate$44101
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:881|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:8"
.gate SB_DFFESR C=common.led_blink.clk D=$abc$44715$techmap\common.pb.$procmux$12896_Y[7] E=$abc$44715$auto$dff2dffe.cc:175:make_patterns_logic$36014 Q=common.pb.spitx_len[7] R=$abc$44715$auto$rtlil.cc:1969:NotGate$44101
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:881|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:8"
.gate SB_DFFESR C=common.led_blink.clk D=$abc$44715$techmap\common.pb.$procmux$12940_Y[0] E=$abc$44715$auto$dff2dffe.cc:175:make_patterns_logic$36833 Q=common.pb.spitx_bytecount[0] R=$abc$44715$auto$rtlil.cc:1969:NotGate$44101
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:881|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:8"
.gate SB_DFFESR C=common.led_blink.clk D=$abc$44715$techmap\common.pb.$procmux$12940_Y[1] E=$abc$44715$auto$dff2dffe.cc:175:make_patterns_logic$36833 Q=common.pb.spitx_bytecount[1] R=$abc$44715$auto$rtlil.cc:1969:NotGate$44101
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:881|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:8"
.gate SB_DFFESR C=common.led_blink.clk D=$abc$44715$techmap\common.pb.$procmux$12940_Y[2] E=$abc$44715$auto$dff2dffe.cc:175:make_patterns_logic$36833 Q=common.pb.spitx_bytecount[2] R=$abc$44715$auto$rtlil.cc:1969:NotGate$44101
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:881|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:8"
.gate SB_DFFESR C=common.led_blink.clk D=$abc$44715$techmap\common.pb.$procmux$12940_Y[3] E=$abc$44715$auto$dff2dffe.cc:175:make_patterns_logic$36833 Q=common.pb.spitx_bytecount[3] R=$abc$44715$auto$rtlil.cc:1969:NotGate$44101
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:881|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:8"
.gate SB_DFFESR C=common.led_blink.clk D=$abc$44715$techmap\common.pb.$procmux$12940_Y[4] E=$abc$44715$auto$dff2dffe.cc:175:make_patterns_logic$36833 Q=common.pb.spitx_bytecount[4] R=$abc$44715$auto$rtlil.cc:1969:NotGate$44101
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:881|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:8"
.gate SB_DFFESR C=common.led_blink.clk D=$abc$44715$techmap\common.pb.$procmux$12940_Y[5] E=$abc$44715$auto$dff2dffe.cc:175:make_patterns_logic$36833 Q=common.pb.spitx_bytecount[5] R=$abc$44715$auto$rtlil.cc:1969:NotGate$44101
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:881|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:8"
.gate SB_DFFESR C=common.led_blink.clk D=$abc$44715$techmap\common.pb.$procmux$12940_Y[6] E=$abc$44715$auto$dff2dffe.cc:175:make_patterns_logic$36833 Q=common.pb.spitx_bytecount[6] R=$abc$44715$auto$rtlil.cc:1969:NotGate$44101
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:881|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:8"
.gate SB_DFFESR C=common.led_blink.clk D=$abc$44715$techmap\common.pb.$procmux$12940_Y[7] E=$abc$44715$auto$dff2dffe.cc:175:make_patterns_logic$36833 Q=common.pb.spitx_bytecount[7] R=$abc$44715$auto$rtlil.cc:1969:NotGate$44101
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:881|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:8"
.gate SB_DFFE C=common.led_blink.clk D=common.pb.spitx_ctrl_pending E=$abc$44715$auto$dff2dffe.cc:175:make_patterns_logic$37082 Q=common.pb.spitx_ctrl_pending_ack
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:881|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:8"
.gate SB_DFFESR C=common.led_blink.clk D=$abc$44715$techmap\common.pb.$2\spi_tx_data[7:0][0] E=$abc$44715$auto$dff2dffe.cc:175:make_patterns_logic$37142 Q=common.pb.spi_tx_data[0] R=$abc$44715$auto$rtlil.cc:1969:NotGate$44101
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:881|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:8"
.gate SB_DFFESR C=common.led_blink.clk D=$abc$44715$techmap\common.pb.$2\spi_tx_data[7:0][1] E=$abc$44715$auto$dff2dffe.cc:175:make_patterns_logic$37142 Q=common.pb.spi_tx_data[1] R=$abc$44715$auto$rtlil.cc:1969:NotGate$44101
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:881|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:8"
.gate SB_DFFESR C=common.led_blink.clk D=$abc$44715$techmap\common.pb.$2\spi_tx_data[7:0][2] E=$abc$44715$auto$dff2dffe.cc:175:make_patterns_logic$37142 Q=common.pb.spi_tx_data[2] R=$abc$44715$auto$rtlil.cc:1969:NotGate$44101
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:881|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:8"
.gate SB_DFFESR C=common.led_blink.clk D=$abc$44715$techmap\common.pb.$2\spi_tx_data[7:0][3] E=$abc$44715$auto$dff2dffe.cc:175:make_patterns_logic$37142 Q=common.pb.spi_tx_data[3] R=$abc$44715$auto$rtlil.cc:1969:NotGate$44101
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:881|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:8"
.gate SB_DFFESR C=common.led_blink.clk D=$abc$44715$techmap\common.pb.$2\spi_tx_data[7:0][4] E=$abc$44715$auto$dff2dffe.cc:175:make_patterns_logic$37142 Q=common.pb.spi_tx_data[4] R=$abc$44715$auto$rtlil.cc:1969:NotGate$44101
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:881|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:8"
.gate SB_DFFESR C=common.led_blink.clk D=$abc$44715$techmap\common.pb.$2\spi_tx_data[7:0][5] E=$abc$44715$auto$dff2dffe.cc:175:make_patterns_logic$37142 Q=common.pb.spi_tx_data[5] R=$abc$44715$auto$rtlil.cc:1969:NotGate$44101
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:881|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:8"
.gate SB_DFFESR C=common.led_blink.clk D=$abc$44715$techmap\common.pb.$2\spi_tx_data[7:0][6] E=$abc$44715$auto$dff2dffe.cc:175:make_patterns_logic$37142 Q=common.pb.spi_tx_data[6] R=$abc$44715$auto$rtlil.cc:1969:NotGate$44101
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:881|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:8"
.gate SB_DFFESR C=common.led_blink.clk D=$abc$44715$techmap\common.pb.$2\spi_tx_data[7:0][7] E=$abc$44715$auto$dff2dffe.cc:175:make_patterns_logic$37142 Q=common.pb.spi_tx_data[7] R=$abc$44715$auto$rtlil.cc:1969:NotGate$44101
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:881|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:8"
.gate SB_DFFE C=common.led_blink.clk D=$techmap\common.pb.$0\rx_buf_rd_addr[7:0][0] E=$abc$44715$auto$dff2dffe.cc:175:make_patterns_logic$37697 Q=common.pb.rx_buf_rd_addr[0]
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:881|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:8"
.gate SB_DFFE C=common.led_blink.clk D=$abc$44715$auto$simplemap.cc:309:simplemap_lut$25737[1] E=$abc$44715$auto$dff2dffe.cc:175:make_patterns_logic$37856 Q=common.pb.rx_buf_rd_addr[1]
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:881|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:8"
.gate SB_DFFE C=common.led_blink.clk D=$techmap\common.pb.$0\rx_buf_rd_addr[7:0][2] E=$abc$44715$auto$dff2dffe.cc:175:make_patterns_logic$37697 Q=common.pb.rx_buf_rd_addr[2]
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:881|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:8"
.gate SB_DFFE C=common.led_blink.clk D=$techmap\common.pb.$0\rx_buf_rd_addr[7:0][3] E=$abc$44715$auto$dff2dffe.cc:175:make_patterns_logic$37697 Q=common.pb.rx_buf_rd_addr[3]
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:881|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:8"
.gate SB_DFFE C=common.led_blink.clk D=$techmap\common.pb.$0\rx_buf_rd_addr[7:0][4] E=$abc$44715$auto$dff2dffe.cc:175:make_patterns_logic$37697 Q=common.pb.rx_buf_rd_addr[4]
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:881|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:8"
.gate SB_DFFE C=common.led_blink.clk D=$techmap\common.pb.$0\rx_buf_rd_addr[7:0][5] E=$abc$44715$auto$dff2dffe.cc:175:make_patterns_logic$37697 Q=common.pb.rx_buf_rd_addr[5]
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:881|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:8"
.gate SB_DFFE C=common.led_blink.clk D=$techmap\common.pb.$0\rx_buf_rd_addr[7:0][6] E=$abc$44715$auto$dff2dffe.cc:175:make_patterns_logic$37697 Q=common.pb.rx_buf_rd_addr[6]
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:881|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:8"
.gate SB_DFFE C=common.led_blink.clk D=$techmap\common.pb.$0\rx_buf_rd_addr[7:0][7] E=$abc$44715$auto$dff2dffe.cc:175:make_patterns_logic$37697 Q=common.pb.rx_buf_rd_addr[7]
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:881|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:8"
.gate SB_DFFE C=common.led_blink.clk D=$abc$44715$auto$ice40_ffinit.cc:140:execute$44090 E=$abc$44715$auto$dff2dffe.cc:175:make_patterns_logic$38689 Q=$abc$44715$auto$ice40_ffinit.cc:141:execute$44091
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:1046|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:8"
.gate SB_DFFE C=common.led_blink.clk D=$abc$44715$auto$ice40_ffinit.cc:140:execute$43998 E=$abc$44715$auto$dff2dffe.cc:175:make_patterns_logic$38689 Q=$abc$44715$auto$ice40_ffinit.cc:141:execute$43999
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:1046|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:8"
.gate SB_DFFE C=common.led_blink.clk D=$abc$44715$auto$ice40_ffinit.cc:140:execute$44002 E=$abc$44715$auto$dff2dffe.cc:175:make_patterns_logic$38689 Q=$abc$44715$auto$ice40_ffinit.cc:141:execute$44003
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:1046|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:8"
.gate SB_DFFE C=common.led_blink.clk D=$abc$44715$auto$ice40_ffinit.cc:140:execute$44006 E=$abc$44715$auto$dff2dffe.cc:175:make_patterns_logic$38689 Q=$abc$44715$auto$ice40_ffinit.cc:141:execute$44007
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:1046|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:8"
.gate SB_DFFE C=common.led_blink.clk D=$abc$44715$auto$ice40_ffinit.cc:140:execute$44010 E=$abc$44715$auto$dff2dffe.cc:175:make_patterns_logic$38689 Q=$abc$44715$auto$ice40_ffinit.cc:141:execute$44011
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:1046|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:8"
.gate SB_DFFE C=common.led_blink.clk D=$abc$44715$auto$ice40_ffinit.cc:140:execute$44014 E=$abc$44715$auto$dff2dffe.cc:175:make_patterns_logic$38689 Q=$abc$44715$auto$ice40_ffinit.cc:141:execute$44015
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:1046|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:8"
.gate SB_DFFE C=common.led_blink.clk D=$abc$44715$auto$ice40_ffinit.cc:140:execute$44018 E=$abc$44715$auto$dff2dffe.cc:175:make_patterns_logic$38689 Q=$abc$44715$auto$ice40_ffinit.cc:141:execute$44019
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:1046|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:8"
.gate SB_DFFE C=common.led_blink.clk D=$abc$44715$auto$ice40_ffinit.cc:140:execute$44022 E=$abc$44715$auto$dff2dffe.cc:175:make_patterns_logic$38689 Q=$abc$44715$auto$ice40_ffinit.cc:141:execute$44023
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:1046|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:8"
.gate SB_DFFE C=common.led_blink.clk D=$abc$44715$auto$ice40_ffinit.cc:140:execute$44026 E=$abc$44715$auto$dff2dffe.cc:175:make_patterns_logic$38689 Q=$abc$44715$auto$ice40_ffinit.cc:141:execute$44027
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:1046|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:8"
.gate SB_DFFE C=common.led_blink.clk D=$abc$44715$auto$ice40_ffinit.cc:140:execute$44030 E=$abc$44715$auto$dff2dffe.cc:175:make_patterns_logic$38689 Q=$abc$44715$auto$ice40_ffinit.cc:141:execute$44031
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:1046|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:8"
.gate SB_DFFE C=common.led_blink.clk D=$abc$44715$auto$ice40_ffinit.cc:140:execute$44034 E=$abc$44715$auto$dff2dffe.cc:175:make_patterns_logic$38689 Q=$abc$44715$auto$ice40_ffinit.cc:141:execute$44035
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:1046|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:8"
.gate SB_DFFE C=common.led_blink.clk D=$abc$44715$auto$ice40_ffinit.cc:140:execute$44038 E=$abc$44715$auto$dff2dffe.cc:175:make_patterns_logic$38689 Q=$abc$44715$auto$ice40_ffinit.cc:141:execute$44039
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:1046|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:8"
.gate SB_DFFE C=common.led_blink.clk D=$abc$44715$auto$ice40_ffinit.cc:140:execute$44042 E=$abc$44715$auto$dff2dffe.cc:175:make_patterns_logic$38689 Q=$abc$44715$auto$ice40_ffinit.cc:141:execute$44043
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:1046|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:8"
.gate SB_DFFE C=common.led_blink.clk D=$abc$44715$auto$ice40_ffinit.cc:140:execute$44046 E=$abc$44715$auto$dff2dffe.cc:175:make_patterns_logic$38689 Q=$abc$44715$auto$ice40_ffinit.cc:141:execute$44047
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:1046|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:8"
.gate SB_DFFE C=common.led_blink.clk D=$abc$44715$auto$ice40_ffinit.cc:140:execute$44050 E=$abc$44715$auto$dff2dffe.cc:175:make_patterns_logic$38689 Q=$abc$44715$auto$ice40_ffinit.cc:141:execute$44051
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:1046|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:8"
.gate SB_DFFE C=common.led_blink.clk D=$abc$44715$auto$ice40_ffinit.cc:140:execute$44054 E=$abc$44715$auto$dff2dffe.cc:175:make_patterns_logic$38689 Q=$abc$44715$auto$ice40_ffinit.cc:141:execute$44055
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:1046|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:8"
.gate SB_DFFE C=common.led_blink.clk D=$abc$44715$auto$ice40_ffinit.cc:140:execute$44058 E=$abc$44715$auto$dff2dffe.cc:175:make_patterns_logic$38689 Q=$abc$44715$auto$ice40_ffinit.cc:141:execute$44059
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:1046|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:8"
.gate SB_DFFE C=common.led_blink.clk D=$abc$44715$auto$ice40_ffinit.cc:140:execute$44062 E=$abc$44715$auto$dff2dffe.cc:175:make_patterns_logic$38689 Q=$abc$44715$auto$ice40_ffinit.cc:141:execute$44063
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:1046|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:8"
.gate SB_DFFE C=common.led_blink.clk D=$abc$44715$auto$ice40_ffinit.cc:140:execute$44066 E=$abc$44715$auto$dff2dffe.cc:175:make_patterns_logic$38689 Q=$abc$44715$auto$ice40_ffinit.cc:141:execute$44067
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:1046|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:8"
.gate SB_DFFE C=common.led_blink.clk D=$abc$44715$auto$ice40_ffinit.cc:140:execute$44070 E=$abc$44715$auto$dff2dffe.cc:175:make_patterns_logic$38689 Q=$abc$44715$auto$ice40_ffinit.cc:141:execute$44071
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:1046|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:8"
.gate SB_DFFE C=common.led_blink.clk D=$abc$44715$auto$ice40_ffinit.cc:140:execute$44074 E=$abc$44715$auto$dff2dffe.cc:175:make_patterns_logic$38689 Q=$abc$44715$auto$ice40_ffinit.cc:141:execute$44075
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:1046|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:8"
.gate SB_DFFE C=common.led_blink.clk D=$abc$44715$auto$ice40_ffinit.cc:140:execute$44078 E=$abc$44715$auto$dff2dffe.cc:175:make_patterns_logic$38689 Q=$abc$44715$auto$ice40_ffinit.cc:141:execute$44079
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:1046|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:8"
.gate SB_DFFE C=common.led_blink.clk D=$abc$44715$auto$ice40_ffinit.cc:140:execute$44082 E=$abc$44715$auto$dff2dffe.cc:175:make_patterns_logic$38689 Q=$abc$44715$auto$ice40_ffinit.cc:141:execute$44083
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:1046|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:8"
.gate SB_DFFE C=common.led_blink.clk D=$abc$44715$auto$ice40_ffinit.cc:140:execute$44086 E=$abc$44715$auto$dff2dffe.cc:175:make_patterns_logic$38689 Q=$abc$44715$auto$ice40_ffinit.cc:141:execute$44087
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:1046|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:8"
.gate SB_DFFESR C=common.led_blink.clk D=$abc$44715$techmap\common.pb.$procmux$9310_Y[0] E=$abc$44715$auto$dff2dffe.cc:158:make_patterns_logic$39268 Q=common.pb.timer_idle[0] R=$abc$44715$auto$rtlil.cc:1969:NotGate$44101
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:1046|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:8"
.gate SB_DFFESR C=common.led_blink.clk D=$abc$44715$techmap\common.pb.$procmux$9310_Y[1] E=$abc$44715$auto$dff2dffe.cc:175:make_patterns_logic$39306 Q=common.pb.timer_idle[1] R=$abc$44715$auto$rtlil.cc:1969:NotGate$44101
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:1046|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:8"
.gate SB_DFFESR C=common.led_blink.clk D=$abc$44715$techmap\common.pb.$procmux$9310_Y[2] E=$abc$44715$auto$dff2dffe.cc:158:make_patterns_logic$39268 Q=common.pb.timer_idle[2] R=$abc$44715$auto$rtlil.cc:1969:NotGate$44101
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:1046|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:8"
.gate SB_DFFESR C=common.led_blink.clk D=$abc$44715$techmap\common.pb.$procmux$9310_Y[3] E=$abc$44715$auto$dff2dffe.cc:158:make_patterns_logic$39268 Q=common.pb.timer_idle[3] R=$abc$44715$auto$rtlil.cc:1969:NotGate$44101
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:1046|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:8"
.gate SB_DFFESR C=common.led_blink.clk D=$abc$44715$techmap\common.pb.$procmux$9310_Y[4] E=$abc$44715$auto$dff2dffe.cc:158:make_patterns_logic$39268 Q=common.pb.timer_idle[4] R=$abc$44715$auto$rtlil.cc:1969:NotGate$44101
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:1046|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:8"
.gate SB_DFFESR C=common.led_blink.clk D=$abc$44715$techmap\common.pb.$procmux$9310_Y[5] E=$abc$44715$auto$dff2dffe.cc:158:make_patterns_logic$39268 Q=common.pb.timer_idle[5] R=$abc$44715$auto$rtlil.cc:1969:NotGate$44101
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:1046|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:8"
.gate SB_DFFESR C=common.led_blink.clk D=$abc$44715$techmap\common.pb.$procmux$9310_Y[6] E=$abc$44715$auto$dff2dffe.cc:158:make_patterns_logic$39268 Q=common.pb.timer_idle[6] R=$abc$44715$auto$rtlil.cc:1969:NotGate$44101
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:1046|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:8"
.gate SB_DFFESR C=common.led_blink.clk D=$abc$44715$techmap\common.pb.$procmux$9310_Y[7] E=$abc$44715$auto$dff2dffe.cc:158:make_patterns_logic$39268 Q=common.pb.timer_idle[7] R=$abc$44715$auto$rtlil.cc:1969:NotGate$44101
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:1046|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:8"
.gate SB_DFFESR C=common.led_blink.clk D=$abc$44715$techmap\common.pb.$procmux$9310_Y[8] E=$abc$44715$auto$dff2dffe.cc:158:make_patterns_logic$39268 Q=common.pb.timer_idle[8] R=$abc$44715$auto$rtlil.cc:1969:NotGate$44101
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:1046|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:8"
.gate SB_DFFESR C=common.led_blink.clk D=$abc$44715$techmap\common.pb.$procmux$9310_Y[9] E=$abc$44715$auto$dff2dffe.cc:158:make_patterns_logic$39268 Q=common.pb.timer_idle[9] R=$abc$44715$auto$rtlil.cc:1969:NotGate$44101
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:1046|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:8"
.gate SB_DFFESR C=common.led_blink.clk D=$abc$44715$techmap\common.pb.$procmux$9310_Y[10] E=$abc$44715$auto$dff2dffe.cc:158:make_patterns_logic$39268 Q=common.pb.timer_idle[10] R=$abc$44715$auto$rtlil.cc:1969:NotGate$44101
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:1046|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:8"
.gate SB_DFFESR C=common.led_blink.clk D=$abc$44715$techmap\common.pb.$procmux$9310_Y[11] E=$abc$44715$auto$dff2dffe.cc:158:make_patterns_logic$39268 Q=common.pb.timer_idle[11] R=$abc$44715$auto$rtlil.cc:1969:NotGate$44101
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:1046|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:8"
.gate SB_DFFESR C=common.led_blink.clk D=$abc$44715$techmap\common.pb.$procmux$9310_Y[12] E=$abc$44715$auto$dff2dffe.cc:158:make_patterns_logic$39268 Q=common.pb.timer_idle[12] R=$abc$44715$auto$rtlil.cc:1969:NotGate$44101
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:1046|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:8"
.gate SB_DFFESR C=common.led_blink.clk D=$abc$44715$techmap\common.pb.$procmux$9310_Y[13] E=$abc$44715$auto$dff2dffe.cc:158:make_patterns_logic$39268 Q=common.pb.timer_idle[13] R=$abc$44715$auto$rtlil.cc:1969:NotGate$44101
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:1046|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:8"
.gate SB_DFFESR C=common.led_blink.clk D=$abc$44715$techmap\common.pb.$procmux$9310_Y[14] E=$abc$44715$auto$dff2dffe.cc:158:make_patterns_logic$39268 Q=common.pb.timer_idle[14] R=$abc$44715$auto$rtlil.cc:1969:NotGate$44101
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:1046|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:8"
.gate SB_DFFESR C=common.led_blink.clk D=$abc$44715$techmap\common.pb.$procmux$9310_Y[15] E=$abc$44715$auto$dff2dffe.cc:158:make_patterns_logic$39268 Q=common.pb.timer_idle[15] R=$abc$44715$auto$rtlil.cc:1969:NotGate$44101
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:1046|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:8"
.gate SB_DFFESR C=common.led_blink.clk D=$abc$44715$techmap\common.pb.$procmux$9310_Y[16] E=$abc$44715$auto$dff2dffe.cc:158:make_patterns_logic$39268 Q=common.pb.timer_idle[16] R=$abc$44715$auto$rtlil.cc:1969:NotGate$44101
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:1046|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:8"
.gate SB_DFFESR C=common.led_blink.clk D=$abc$44715$techmap\common.pb.$procmux$9310_Y[17] E=$abc$44715$auto$dff2dffe.cc:158:make_patterns_logic$39268 Q=common.pb.timer_idle[17] R=$abc$44715$auto$rtlil.cc:1969:NotGate$44101
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:1046|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:8"
.gate SB_DFFESR C=common.led_blink.clk D=$abc$44715$techmap\common.pb.$procmux$9310_Y[18] E=$abc$44715$auto$dff2dffe.cc:158:make_patterns_logic$39268 Q=common.pb.timer_idle[18] R=$abc$44715$auto$rtlil.cc:1969:NotGate$44101
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:1046|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:8"
.gate SB_DFFESR C=common.led_blink.clk D=$abc$44715$techmap\common.pb.$procmux$9310_Y[19] E=$abc$44715$auto$dff2dffe.cc:158:make_patterns_logic$39268 Q=common.pb.timer_idle[19] R=$abc$44715$auto$rtlil.cc:1969:NotGate$44101
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:1046|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:8"
.gate SB_DFFESR C=common.led_blink.clk D=$abc$44715$techmap\common.pb.$procmux$9310_Y[20] E=$abc$44715$auto$dff2dffe.cc:158:make_patterns_logic$39268 Q=common.pb.timer_idle[20] R=$abc$44715$auto$rtlil.cc:1969:NotGate$44101
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:1046|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:8"
.gate SB_DFFESR C=common.led_blink.clk D=$abc$44715$techmap\common.pb.$procmux$9310_Y[21] E=$abc$44715$auto$dff2dffe.cc:158:make_patterns_logic$39268 Q=common.pb.timer_idle[21] R=$abc$44715$auto$rtlil.cc:1969:NotGate$44101
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:1046|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:8"
.gate SB_DFFESR C=common.led_blink.clk D=$abc$44715$techmap\common.pb.$procmux$9310_Y[22] E=$abc$44715$auto$dff2dffe.cc:158:make_patterns_logic$39268 Q=common.pb.timer_idle[22] R=$abc$44715$auto$rtlil.cc:1969:NotGate$44101
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:1046|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:8"
.gate SB_DFFESR C=common.led_blink.clk D=$abc$44715$techmap\common.pb.$procmux$9310_Y[23] E=$abc$44715$auto$dff2dffe.cc:158:make_patterns_logic$39268 Q=common.pb.timer_idle[23] R=$abc$44715$auto$rtlil.cc:1969:NotGate$44101
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:1046|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:8"
.gate SB_DFFSR C=common.led_blink.clk D=$abc$44715$techmap\common.pb.$procmux$9294_Y Q=common.pb.timer_idle_active R=$abc$44715$auto$rtlil.cc:1969:NotGate$44101
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:1046|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:2"
.gate SB_DFFSR C=common.led_blink.clk D=$abc$44715$techmap$techmap\common.pb.spirx_lencalc.$procmux$14747.$ternary$/home/mb/fpga-toolchain/yosys/bin/../share/yosys/techmap.v:445$18291_Y[0] Q=common.pb.spirx_lencalc.length[0] R=$abc$44715$auto$rtlil.cc:1969:NotGate$44229
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:566|profibus_phy_mod.v:109|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:2"
.gate SB_DFFSR C=common.led_blink.clk D=$abc$44715$techmap$techmap\common.pb.spirx_lencalc.$procmux$14747.$ternary$/home/mb/fpga-toolchain/yosys/bin/../share/yosys/techmap.v:445$18291_Y[1] Q=common.pb.spirx_lencalc.length[1] R=$abc$44715$auto$rtlil.cc:1969:NotGate$44229
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:566|profibus_phy_mod.v:109|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:2"
.gate SB_DFFSR C=common.led_blink.clk D=$abc$44715$techmap$techmap\common.pb.spirx_lencalc.$procmux$14747.$ternary$/home/mb/fpga-toolchain/yosys/bin/../share/yosys/techmap.v:445$18291_Y[2] Q=common.pb.spirx_lencalc.length[2] R=$abc$44715$auto$rtlil.cc:1969:NotGate$44229
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:566|profibus_phy_mod.v:109|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:2"
.gate SB_DFFSR C=common.led_blink.clk D=$abc$44715$techmap$techmap\common.pb.spirx_lencalc.$procmux$14747.$ternary$/home/mb/fpga-toolchain/yosys/bin/../share/yosys/techmap.v:445$18291_Y[3] Q=common.pb.spirx_lencalc.length[3] R=$abc$44715$auto$rtlil.cc:1969:NotGate$44229
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:566|profibus_phy_mod.v:109|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:2"
.gate SB_DFFSR C=common.led_blink.clk D=$abc$44715$techmap$techmap\common.pb.spirx_lencalc.$procmux$14747.$ternary$/home/mb/fpga-toolchain/yosys/bin/../share/yosys/techmap.v:445$18291_Y[4] Q=common.pb.spirx_lencalc.length[4] R=$abc$44715$auto$rtlil.cc:1969:NotGate$44229
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:566|profibus_phy_mod.v:109|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:2"
.gate SB_DFFSR C=common.led_blink.clk D=$abc$44715$techmap$techmap\common.pb.spirx_lencalc.$procmux$14747.$ternary$/home/mb/fpga-toolchain/yosys/bin/../share/yosys/techmap.v:445$18291_Y[5] Q=common.pb.spirx_lencalc.length[5] R=$abc$44715$auto$rtlil.cc:1969:NotGate$44229
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:566|profibus_phy_mod.v:109|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:2"
.gate SB_DFFSR C=common.led_blink.clk D=$abc$44715$techmap$techmap\common.pb.spirx_lencalc.$procmux$14747.$ternary$/home/mb/fpga-toolchain/yosys/bin/../share/yosys/techmap.v:445$18291_Y[6] Q=common.pb.spirx_lencalc.length[6] R=$abc$44715$auto$rtlil.cc:1969:NotGate$44229
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:566|profibus_phy_mod.v:109|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:2"
.gate SB_DFFSR C=common.led_blink.clk D=$abc$44715$techmap$techmap\common.pb.spirx_lencalc.$procmux$14747.$ternary$/home/mb/fpga-toolchain/yosys/bin/../share/yosys/techmap.v:445$18291_Y[7] Q=common.pb.spirx_lencalc.length[7] R=$abc$44715$auto$rtlil.cc:1969:NotGate$44229
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:566|profibus_phy_mod.v:109|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:2"
.gate SB_DFFSR C=common.led_blink.clk D=$abc$44715$techmap$techmap\common.pb.spirx_lencalc.$procmux$14776.$ternary$/home/mb/fpga-toolchain/yosys/bin/../share/yosys/techmap.v:445$20137_Y[0] Q=common.pb.spirx_lencalc.state[0] R=$abc$44715$auto$rtlil.cc:1969:NotGate$44229
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:566|profibus_phy_mod.v:109|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:2"
.gate SB_DFFSR C=common.led_blink.clk D=$abc$44715$techmap$techmap\common.pb.spirx_lencalc.$procmux$14776.$ternary$/home/mb/fpga-toolchain/yosys/bin/../share/yosys/techmap.v:445$20137_Y[1] Q=common.pb.spirx_lencalc.state[1] R=$abc$44715$auto$rtlil.cc:1969:NotGate$44229
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:566|profibus_phy_mod.v:109|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:2"
.gate SB_DFFSR C=common.led_blink.clk D=$abc$44715$techmap$techmap\common.pb.spirx_lencalc.$procmux$14797.$ternary$/home/mb/fpga-toolchain/yosys/bin/../share/yosys/techmap.v:445$17894_Y[0] Q=common.pb.spirx_lencalc.byte_le[0] R=$abc$44715$auto$rtlil.cc:1969:NotGate$44229
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:566|profibus_phy_mod.v:109|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:2"
.gate SB_DFFSR C=common.led_blink.clk D=$abc$44715$techmap$techmap\common.pb.spirx_lencalc.$procmux$14797.$ternary$/home/mb/fpga-toolchain/yosys/bin/../share/yosys/techmap.v:445$17894_Y[1] Q=common.pb.spirx_lencalc.byte_le[1] R=$abc$44715$auto$rtlil.cc:1969:NotGate$44229
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:566|profibus_phy_mod.v:109|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:2"
.gate SB_DFFSR C=common.led_blink.clk D=$abc$44715$techmap$techmap\common.pb.spirx_lencalc.$procmux$14797.$ternary$/home/mb/fpga-toolchain/yosys/bin/../share/yosys/techmap.v:445$17894_Y[2] Q=common.pb.spirx_lencalc.byte_le[2] R=$abc$44715$auto$rtlil.cc:1969:NotGate$44229
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:566|profibus_phy_mod.v:109|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:2"
.gate SB_DFFSR C=common.led_blink.clk D=$abc$44715$techmap$techmap\common.pb.spirx_lencalc.$procmux$14797.$ternary$/home/mb/fpga-toolchain/yosys/bin/../share/yosys/techmap.v:445$17894_Y[3] Q=common.pb.spirx_lencalc.byte_le[3] R=$abc$44715$auto$rtlil.cc:1969:NotGate$44229
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:566|profibus_phy_mod.v:109|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:2"
.gate SB_DFFSR C=common.led_blink.clk D=$abc$44715$techmap$techmap\common.pb.spirx_lencalc.$procmux$14797.$ternary$/home/mb/fpga-toolchain/yosys/bin/../share/yosys/techmap.v:445$17894_Y[4] Q=common.pb.spirx_lencalc.byte_le[4] R=$abc$44715$auto$rtlil.cc:1969:NotGate$44229
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:566|profibus_phy_mod.v:109|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:2"
.gate SB_DFFSR C=common.led_blink.clk D=$abc$44715$techmap$techmap\common.pb.spirx_lencalc.$procmux$14797.$ternary$/home/mb/fpga-toolchain/yosys/bin/../share/yosys/techmap.v:445$17894_Y[5] Q=common.pb.spirx_lencalc.byte_le[5] R=$abc$44715$auto$rtlil.cc:1969:NotGate$44229
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:566|profibus_phy_mod.v:109|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:2"
.gate SB_DFFSR C=common.led_blink.clk D=$abc$44715$techmap$techmap\common.pb.spirx_lencalc.$procmux$14797.$ternary$/home/mb/fpga-toolchain/yosys/bin/../share/yosys/techmap.v:445$17894_Y[6] Q=common.pb.spirx_lencalc.byte_le[6] R=$abc$44715$auto$rtlil.cc:1969:NotGate$44229
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:566|profibus_phy_mod.v:109|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:2"
.gate SB_DFFSR C=common.led_blink.clk D=$abc$44715$techmap$techmap\common.pb.spirx_lencalc.$procmux$14797.$ternary$/home/mb/fpga-toolchain/yosys/bin/../share/yosys/techmap.v:445$17894_Y[7] Q=common.pb.spirx_lencalc.byte_le[7] R=$abc$44715$auto$rtlil.cc:1969:NotGate$44229
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:566|profibus_phy_mod.v:109|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:2"
.gate SB_DFFSR C=common.led_blink.clk D=$abc$44715$techmap$techmap\common.pb.spirx_lencalc.$procmux$14815.$ternary$/home/mb/fpga-toolchain/yosys/bin/../share/yosys/techmap.v:445$18549_Y Q=common.pb.spirx_lencalc.error R=$abc$44715$auto$rtlil.cc:1969:NotGate$44229
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:566|profibus_phy_mod.v:109|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:2"
.gate SB_DFFSR C=common.led_blink.clk D=$abc$44715$techmap$techmap\common.pb.spirx_lencalc.$procmux$14850.$ternary$/home/mb/fpga-toolchain/yosys/bin/../share/yosys/techmap.v:445$18549_Y Q=common.pb.spirx_lencalc.length_valid R=$abc$44715$auto$rtlil.cc:1969:NotGate$44229
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:566|profibus_phy_mod.v:109|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:2"
.gate SB_DFFSR C=common.led_blink.clk D=$abc$44715$auto$rtlil.cc:1836:ReduceOr$16042 Q=common.pb.spi.rx_irq_r R=common.pb.spi.ss_s
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:438|spi_slave_mod.v:82|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:2"
.gate SB_DFFESR C=common.led_blink.clk D=$abc$44715$techmap\common.pb.spi.$procmux$14923_Y[0] E=$abc$44715$auto$dff2dffe.cc:158:make_patterns_logic$39574 Q=common.pb.spi.bit_count[0] R=common.pb.spi.ss_s
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:438|spi_slave_mod.v:82|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:8"
.gate SB_DFFESR C=common.led_blink.clk D=$abc$44715$techmap\common.pb.spi.$procmux$14923_Y[1] E=$abc$44715$auto$dff2dffe.cc:175:make_patterns_logic$39612 Q=common.pb.spi.bit_count[1] R=common.pb.spi.ss_s
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:438|spi_slave_mod.v:82|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:8"
.gate SB_DFFESR C=common.led_blink.clk D=$abc$44715$techmap\common.pb.spi.$procmux$14923_Y[2] E=$abc$44715$auto$dff2dffe.cc:158:make_patterns_logic$39574 Q=common.pb.spi.bit_count[2] R=common.pb.spi.ss_s
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:438|spi_slave_mod.v:82|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:8"
.gate SB_DFFESR C=common.led_blink.clk D=$abc$44715$techmap\common.pb.spi.$procmux$14923_Y[3] E=$abc$44715$auto$dff2dffe.cc:158:make_patterns_logic$39574 Q=common.pb.spi.bit_count[3] R=common.pb.spi.ss_s
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:438|spi_slave_mod.v:82|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:8"
.gate SB_DFFESR C=common.led_blink.clk D=$abc$44715$techmap\common.pb.spi.$procmux$14923_Y[4] E=$abc$44715$auto$dff2dffe.cc:158:make_patterns_logic$39574 Q=common.pb.spi.bit_count[4] R=common.pb.spi.ss_s
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:438|spi_slave_mod.v:82|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:8"
.gate SB_DFFESR C=common.led_blink.clk D=$abc$44715$techmap\common.pb.spi.$procmux$14923_Y[5] E=$abc$44715$auto$dff2dffe.cc:158:make_patterns_logic$39574 Q=common.pb.spi.bit_count[5] R=common.pb.spi.ss_s
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:438|spi_slave_mod.v:82|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:8"
.gate SB_DFFE C=common.led_blink.clk D=$false E=$abc$44715$auto$dff2dffe.cc:158:make_patterns_logic$39664 Q=common.pb.spi.tx_shiftreg[0]
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:438|spi_slave_mod.v:82|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:8"
.gate SB_DFFESR C=common.led_blink.clk D=$abc$44715$techmap\common.pb.spi.$procmux$14931_Y[1] E=$abc$44715$auto$dff2dffe.cc:158:make_patterns_logic$39664 Q=common.pb.spi.tx_shiftreg[1] R=common.pb.spi.ss_s
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:438|spi_slave_mod.v:82|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:8"
.gate SB_DFFESR C=common.led_blink.clk D=$abc$44715$techmap\common.pb.spi.$procmux$14931_Y[2] E=$abc$44715$auto$dff2dffe.cc:158:make_patterns_logic$39664 Q=common.pb.spi.tx_shiftreg[2] R=common.pb.spi.ss_s
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:438|spi_slave_mod.v:82|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:8"
.gate SB_DFFESR C=common.led_blink.clk D=$abc$44715$techmap\common.pb.spi.$procmux$14931_Y[3] E=$abc$44715$auto$dff2dffe.cc:158:make_patterns_logic$39664 Q=common.pb.spi.tx_shiftreg[3] R=common.pb.spi.ss_s
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:438|spi_slave_mod.v:82|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:8"
.gate SB_DFFESR C=common.led_blink.clk D=$abc$44715$techmap\common.pb.spi.$procmux$14931_Y[4] E=$abc$44715$auto$dff2dffe.cc:158:make_patterns_logic$39664 Q=common.pb.spi.tx_shiftreg[4] R=common.pb.spi.ss_s
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:438|spi_slave_mod.v:82|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:8"
.gate SB_DFFESR C=common.led_blink.clk D=$abc$44715$techmap\common.pb.spi.$procmux$14931_Y[5] E=$abc$44715$auto$dff2dffe.cc:158:make_patterns_logic$39664 Q=common.pb.spi.tx_shiftreg[5] R=common.pb.spi.ss_s
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:438|spi_slave_mod.v:82|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:8"
.gate SB_DFFESR C=common.led_blink.clk D=$abc$44715$techmap\common.pb.spi.$procmux$14931_Y[6] E=$abc$44715$auto$dff2dffe.cc:158:make_patterns_logic$39664 Q=common.pb.spi.tx_shiftreg[6] R=common.pb.spi.ss_s
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:438|spi_slave_mod.v:82|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:8"
.gate SB_DFFESR C=common.led_blink.clk D=$abc$44715$techmap\common.pb.spi.$procmux$14931_Y[7] E=$abc$44715$auto$dff2dffe.cc:158:make_patterns_logic$39664 Q=common.pb.spi.tx_shiftreg[7] R=common.pb.spi.ss_s
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:438|spi_slave_mod.v:82|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:8"
.gate SB_DFFESR C=common.led_blink.clk D=common.pb.spi.mosi_s E=$abc$44715$auto$dff2dffe.cc:158:make_patterns_logic$39760 Q=common.pb.spi.rx_shiftreg[0] R=common.pb.spi.ss_s
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:438|spi_slave_mod.v:82|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:8"
.gate SB_DFFESR C=common.led_blink.clk D=common.pb.spi.rx_shiftreg[0] E=$abc$44715$auto$dff2dffe.cc:158:make_patterns_logic$39760 Q=common.pb.spi.rx_shiftreg[1] R=common.pb.spi.ss_s
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:438|spi_slave_mod.v:82|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:8"
.gate SB_DFFESR C=common.led_blink.clk D=common.pb.spi.rx_shiftreg[1] E=$abc$44715$auto$dff2dffe.cc:158:make_patterns_logic$39760 Q=common.pb.spi.rx_shiftreg[2] R=common.pb.spi.ss_s
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:438|spi_slave_mod.v:82|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:8"
.gate SB_DFFESR C=common.led_blink.clk D=common.pb.spi.rx_shiftreg[2] E=$abc$44715$auto$dff2dffe.cc:158:make_patterns_logic$39760 Q=common.pb.spi.rx_shiftreg[3] R=common.pb.spi.ss_s
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:438|spi_slave_mod.v:82|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:8"
.gate SB_DFFESR C=common.led_blink.clk D=common.pb.spi.rx_shiftreg[3] E=$abc$44715$auto$dff2dffe.cc:158:make_patterns_logic$39760 Q=common.pb.spi.rx_shiftreg[4] R=common.pb.spi.ss_s
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:438|spi_slave_mod.v:82|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:8"
.gate SB_DFFESR C=common.led_blink.clk D=common.pb.spi.rx_shiftreg[4] E=$abc$44715$auto$dff2dffe.cc:158:make_patterns_logic$39760 Q=common.pb.spi.rx_shiftreg[5] R=common.pb.spi.ss_s
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:438|spi_slave_mod.v:82|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:8"
.gate SB_DFFESR C=common.led_blink.clk D=common.pb.spi.rx_shiftreg[5] E=$abc$44715$auto$dff2dffe.cc:158:make_patterns_logic$39760 Q=common.pb.spi.rx_shiftreg[6] R=common.pb.spi.ss_s
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:438|spi_slave_mod.v:82|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:8"
.gate SB_DFFESR C=common.led_blink.clk D=common.pb.spi.rx_shiftreg[6] E=$abc$44715$auto$dff2dffe.cc:158:make_patterns_logic$39760 Q=common.pb.spi.rx_shiftreg[7] R=common.pb.spi.ss_s
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:438|spi_slave_mod.v:82|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:8"
.gate SB_DFFE C=common.led_blink.clk D=common.pb.spi.rx_shiftreg[0] E=$abc$44715$auto$dff2dffe.cc:175:make_patterns_logic$39847 Q=common.pb.spi.rx_data_r[0]
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:438|spi_slave_mod.v:82|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:8"
.gate SB_DFFE C=common.led_blink.clk D=common.pb.spi.rx_shiftreg[1] E=$abc$44715$auto$dff2dffe.cc:175:make_patterns_logic$39847 Q=common.pb.spi.rx_data_r[1]
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:438|spi_slave_mod.v:82|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:8"
.gate SB_DFFE C=common.led_blink.clk D=common.pb.spi.rx_shiftreg[2] E=$abc$44715$auto$dff2dffe.cc:175:make_patterns_logic$39847 Q=common.pb.spi.rx_data_r[2]
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:438|spi_slave_mod.v:82|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:8"
.gate SB_DFFE C=common.led_blink.clk D=common.pb.spi.rx_shiftreg[3] E=$abc$44715$auto$dff2dffe.cc:175:make_patterns_logic$39847 Q=common.pb.spi.rx_data_r[3]
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:438|spi_slave_mod.v:82|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:8"
.gate SB_DFFE C=common.led_blink.clk D=common.pb.spi.rx_shiftreg[4] E=$abc$44715$auto$dff2dffe.cc:175:make_patterns_logic$39847 Q=common.pb.spi.rx_data_r[4]
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:438|spi_slave_mod.v:82|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:8"
.gate SB_DFFE C=common.led_blink.clk D=common.pb.spi.rx_shiftreg[5] E=$abc$44715$auto$dff2dffe.cc:175:make_patterns_logic$39847 Q=common.pb.spi.rx_data_r[5]
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:438|spi_slave_mod.v:82|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:8"
.gate SB_DFFE C=common.led_blink.clk D=common.pb.spi.rx_shiftreg[6] E=$abc$44715$auto$dff2dffe.cc:175:make_patterns_logic$39847 Q=common.pb.spi.rx_data_r[6]
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:438|spi_slave_mod.v:82|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:8"
.gate SB_DFFE C=common.led_blink.clk D=common.pb.spi.rx_shiftreg[7] E=$abc$44715$auto$dff2dffe.cc:175:make_patterns_logic$39847 Q=common.pb.spi.rx_data_r[7]
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:438|spi_slave_mod.v:82|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:8"
.gate SB_DFFESR C=common.led_blink.clk D=$abc$44715$techmap\common.pb.spi.$procmux$14951_Y E=$abc$44715$auto$dff2dffe.cc:158:make_patterns_logic$39664 Q=common.pb.spi.miso_r R=common.pb.spi.ss_s
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:438|spi_slave_mod.v:82|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:8"
.gate SB_DFFESR C=common.led_blink.clk D=$abc$44715$techmap\common.pb.uart.$procmux$14896_Y[0] E=$abc$44715$auto$dff2dffe.cc:175:make_patterns_logic$40020 Q=common.pb.uart.tx_data_r[0] R=$abc$44715$auto$rtlil.cc:1969:NotGate$44099
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:395|uart_mod.v:582|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:8"
.gate SB_DFFESR C=common.led_blink.clk D=$abc$44715$techmap\common.pb.uart.$procmux$14896_Y[1] E=$abc$44715$auto$dff2dffe.cc:175:make_patterns_logic$40020 Q=common.pb.uart.tx_data_r[1] R=$abc$44715$auto$rtlil.cc:1969:NotGate$44099
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:395|uart_mod.v:582|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:8"
.gate SB_DFFESR C=common.led_blink.clk D=$abc$44715$techmap\common.pb.uart.$procmux$14896_Y[2] E=$abc$44715$auto$dff2dffe.cc:175:make_patterns_logic$40020 Q=common.pb.uart.tx_data_r[2] R=$abc$44715$auto$rtlil.cc:1969:NotGate$44099
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:395|uart_mod.v:582|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:8"
.gate SB_DFFESR C=common.led_blink.clk D=$abc$44715$techmap\common.pb.uart.$procmux$14896_Y[3] E=$abc$44715$auto$dff2dffe.cc:175:make_patterns_logic$40020 Q=common.pb.uart.tx_data_r[3] R=$abc$44715$auto$rtlil.cc:1969:NotGate$44099
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:395|uart_mod.v:582|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:8"
.gate SB_DFFESR C=common.led_blink.clk D=$abc$44715$techmap\common.pb.uart.$procmux$14896_Y[4] E=$abc$44715$auto$dff2dffe.cc:175:make_patterns_logic$40020 Q=common.pb.uart.tx_data_r[4] R=$abc$44715$auto$rtlil.cc:1969:NotGate$44099
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:395|uart_mod.v:582|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:8"
.gate SB_DFFESR C=common.led_blink.clk D=$abc$44715$techmap\common.pb.uart.$procmux$14896_Y[5] E=$abc$44715$auto$dff2dffe.cc:175:make_patterns_logic$40020 Q=common.pb.uart.tx_data_r[5] R=$abc$44715$auto$rtlil.cc:1969:NotGate$44099
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:395|uart_mod.v:582|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:8"
.gate SB_DFFESR C=common.led_blink.clk D=$abc$44715$techmap\common.pb.uart.$procmux$14896_Y[6] E=$abc$44715$auto$dff2dffe.cc:175:make_patterns_logic$40020 Q=common.pb.uart.tx_data_r[6] R=$abc$44715$auto$rtlil.cc:1969:NotGate$44099
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:395|uart_mod.v:582|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:8"
.gate SB_DFFESR C=common.led_blink.clk D=$abc$44715$techmap\common.pb.uart.$procmux$14896_Y[7] E=$abc$44715$auto$dff2dffe.cc:175:make_patterns_logic$40020 Q=common.pb.uart.tx_data_r[7] R=$abc$44715$auto$rtlil.cc:1969:NotGate$44099
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:395|uart_mod.v:582|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:8"
.gate SB_DFFSR C=common.led_blink.clk D=$abc$44715$techmap\common.pb.uart.$procmux$14906_Y Q=common.pb.uart.tx_trigger_req R=$abc$44715$auto$rtlil.cc:1969:NotGate$44099
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:395|uart_mod.v:582|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:2"
.gate SB_DFF C=common.led_blink.clk D=PIN_13 Q=common.pb.spi.sync_ss.shiftreg[0]
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:438|spi_slave_mod.v:50|sync_signal_mod.v:38|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:2"
.gate SB_DFF C=common.led_blink.clk D=common.pb.spi.sync_ss.shiftreg[0] Q=common.pb.spi.ss_s
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:438|spi_slave_mod.v:50|sync_signal_mod.v:38|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:2"
.gate SB_DFF C=common.led_blink.clk D=PIN_12 Q=common.pb.spi.sync_sck.shiftreg[0]
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:438|spi_slave_mod.v:49|sync_signal_mod.v:38|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:2"
.gate SB_DFF C=common.led_blink.clk D=common.pb.spi.sync_sck.shiftreg[0] Q=common.pb.spi.sync_sck.out
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:438|spi_slave_mod.v:49|sync_signal_mod.v:38|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:2"
.gate SB_DFF C=common.led_blink.clk D=common.pb.spi.sync_sck.out Q=common.pb.spi.sync_sck.shiftreg[2]
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:438|spi_slave_mod.v:49|sync_signal_mod.v:38|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:2"
.gate SB_DFF C=common.led_blink.clk D=PIN_11 Q=common.pb.spi.sync_mosi.shiftreg[0]
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:438|spi_slave_mod.v:48|sync_signal_mod.v:38|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:2"
.gate SB_DFF C=common.led_blink.clk D=common.pb.spi.sync_mosi.shiftreg[0] Q=common.pb.spi.mosi_s
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:438|spi_slave_mod.v:48|sync_signal_mod.v:38|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:2"
.gate SB_DFFESR C=common.led_blink.clk D=$abc$44715$techmap\common.pb.uart.tx_mod.$procmux$15460_Y E=$abc$44715$auto$dff2dffe.cc:175:make_patterns_logic$40319 Q=common.pb.uart.tx_mod.symclk_n_reset R=$abc$44715$auto$rtlil.cc:1969:NotGate$44285
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:395|uart_mod.v:561|uart_mod.v:330|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:8"
.gate SB_DFFESR C=common.led_blink.clk D=$abc$44715$techmap\common.pb.uart.tx_mod.$procmux$15460_Y E=$abc$44715$auto$dff2dffe.cc:175:make_patterns_logic$40319 Q=common.pb.uart.tx_mod.tx_active R=$abc$44715$auto$rtlil.cc:1969:NotGate$44285
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:395|uart_mod.v:561|uart_mod.v:330|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:8"
.gate SB_DFFE C=common.led_blink.clk D=common.pb.uart.tx_data_r[0] E=$abc$44715$auto$dff2dffe.cc:175:make_patterns_logic$40465 Q=common.pb.uart.tx_mod.tx_buf[0]
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:395|uart_mod.v:561|uart_mod.v:330|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:8"
.gate SB_DFFE C=common.led_blink.clk D=common.pb.uart.tx_data_r[1] E=$abc$44715$auto$dff2dffe.cc:175:make_patterns_logic$40465 Q=common.pb.uart.tx_mod.tx_buf[1]
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:395|uart_mod.v:561|uart_mod.v:330|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:8"
.gate SB_DFFE C=common.led_blink.clk D=common.pb.uart.tx_data_r[2] E=$abc$44715$auto$dff2dffe.cc:175:make_patterns_logic$40465 Q=common.pb.uart.tx_mod.tx_buf[2]
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:395|uart_mod.v:561|uart_mod.v:330|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:8"
.gate SB_DFFE C=common.led_blink.clk D=common.pb.uart.tx_data_r[3] E=$abc$44715$auto$dff2dffe.cc:175:make_patterns_logic$40465 Q=common.pb.uart.tx_mod.tx_buf[3]
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:395|uart_mod.v:561|uart_mod.v:330|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:8"
.gate SB_DFFE C=common.led_blink.clk D=common.pb.uart.tx_data_r[4] E=$abc$44715$auto$dff2dffe.cc:175:make_patterns_logic$40465 Q=common.pb.uart.tx_mod.tx_buf[4]
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:395|uart_mod.v:561|uart_mod.v:330|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:8"
.gate SB_DFFE C=common.led_blink.clk D=common.pb.uart.tx_data_r[5] E=$abc$44715$auto$dff2dffe.cc:175:make_patterns_logic$40465 Q=common.pb.uart.tx_mod.tx_buf[5]
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:395|uart_mod.v:561|uart_mod.v:330|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:8"
.gate SB_DFFE C=common.led_blink.clk D=common.pb.uart.tx_data_r[6] E=$abc$44715$auto$dff2dffe.cc:175:make_patterns_logic$40465 Q=common.pb.uart.tx_mod.tx_buf[6]
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:395|uart_mod.v:561|uart_mod.v:330|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:8"
.gate SB_DFFE C=common.led_blink.clk D=common.pb.uart.tx_data_r[7] E=$abc$44715$auto$dff2dffe.cc:175:make_patterns_logic$40465 Q=common.pb.uart.tx_mod.tx_buf[7]
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:395|uart_mod.v:561|uart_mod.v:330|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:8"
.gate SB_DFFE C=common.led_blink.clk D=$abc$44715$auto$ice40_ffinit.cc:140:execute$44094 E=$abc$44715$auto$dff2dffe.cc:175:make_patterns_logic$40759 Q=$abc$44715$auto$ice40_ffinit.cc:141:execute$44095
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:395|uart_mod.v:561|uart_mod.v:330|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:8"
.gate SB_DFFESR C=common.led_blink.clk D=$abc$44715$techmap\common.pb.uart.tx_mod.$procmux$15532_Y E=$abc$44715$auto$dff2dffe.cc:175:make_patterns_logic$40852 Q=common.pb.uart.tx_mod.tx_irq R=$abc$44715$auto$rtlil.cc:1969:NotGate$44285
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:395|uart_mod.v:561|uart_mod.v:330|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:8"
.gate SB_DFFESR C=common.led_blink.clk D=$abc$44715$techmap\common.pb.uart.tx_mod.$procmux$15610_Y[0] E=$abc$44715$auto$dff2dffe.cc:175:make_patterns_logic$40917 Q=common.pb.uart.tx_mod.sym_count[0] R=$abc$44715$auto$rtlil.cc:1969:NotGate$44285
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:395|uart_mod.v:561|uart_mod.v:330|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:8"
.gate SB_DFFESR C=common.led_blink.clk D=$abc$44715$techmap\common.pb.uart.tx_mod.$procmux$15610_Y[1] E=$abc$44715$auto$dff2dffe.cc:175:make_patterns_logic$40917 Q=common.pb.uart.tx_mod.sym_count[1] R=$abc$44715$auto$rtlil.cc:1969:NotGate$44285
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:395|uart_mod.v:561|uart_mod.v:330|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:8"
.gate SB_DFFESR C=common.led_blink.clk D=$abc$44715$techmap\common.pb.uart.tx_mod.$procmux$15610_Y[2] E=$abc$44715$auto$dff2dffe.cc:175:make_patterns_logic$40917 Q=common.pb.uart.tx_mod.sym_count[2] R=$abc$44715$auto$rtlil.cc:1969:NotGate$44285
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:395|uart_mod.v:561|uart_mod.v:330|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:8"
.gate SB_DFFESR C=common.led_blink.clk D=$abc$44715$techmap\common.pb.uart.tx_mod.$procmux$15610_Y[3] E=$abc$44715$auto$dff2dffe.cc:175:make_patterns_logic$40917 Q=common.pb.uart.tx_mod.sym_count[3] R=$abc$44715$auto$rtlil.cc:1969:NotGate$44285
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:395|uart_mod.v:561|uart_mod.v:330|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:8"
.gate SB_DFF C=common.led_blink.clk D=PIN_14 Q=common.pb.uart.sync_rx.shiftreg[0]
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:395|uart_mod.v:518|sync_signal_mod.v:38|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:2"
.gate SB_DFF C=common.led_blink.clk D=common.pb.uart.sync_rx.shiftreg[0] Q=common.pb.uart.arb_mod.rx
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:395|uart_mod.v:518|sync_signal_mod.v:38|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:2"
.gate SB_DFFESR C=common.led_blink.clk D=$abc$44715$techmap\common.pb.uart.rx_mod.$procmux$15345_Y E=$abc$44715$auto$dff2dffe.cc:175:make_patterns_logic$41173 Q=common.pb.uart.rx_mod.rx_irq R=$abc$44715$auto$rtlil.cc:1969:NotGate$44281
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:395|uart_mod.v:537|uart_mod.v:190|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:8"
.gate SB_DFFESR C=common.led_blink.clk D=$abc$44715$auto$rtlil.cc:1969:NotGate$44581 E=$abc$44715$auto$dff2dffe.cc:175:make_patterns_logic$41256 Q=common.pb.uart.rx_mod.symclk_n_reset R=$abc$44715$auto$rtlil.cc:1969:NotGate$44281
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:395|uart_mod.v:537|uart_mod.v:190|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:8"
.gate SB_DFFE C=common.led_blink.clk D=common.pb.uart.arb_mod.rx E=$abc$44715$auto$dff2dffe.cc:175:make_patterns_logic$41306 Q=common.pb.uart.rx_mod.rx_frame_error_start
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:395|uart_mod.v:537|uart_mod.v:190|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:8"
.gate SB_DFFE C=common.led_blink.clk D=common.pb.uart.arb_mod.rx E=$abc$44715$auto$dff2dffe.cc:175:make_patterns_logic$41390 Q=common.pb.uart.rx_mod.rx_parity_buf
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:395|uart_mod.v:537|uart_mod.v:190|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:8"
.gate SB_DFFESR C=common.led_blink.clk D=common.pb.uart.arb_mod.rx E=$abc$44715$auto$dff2dffe.cc:175:make_patterns_logic$41480 Q=common.pb.uart.rx_mod.rx_buf[0] R=$abc$44715$auto$rtlil.cc:1969:NotGate$44581
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:395|uart_mod.v:537|uart_mod.v:190|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:8"
.gate SB_DFFESR C=common.led_blink.clk D=common.pb.uart.arb_mod.rx E=$abc$44715$auto$dff2dffe.cc:175:make_patterns_logic$41570 Q=common.pb.uart.rx_mod.rx_buf[1] R=$abc$44715$auto$rtlil.cc:1969:NotGate$44581
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:395|uart_mod.v:537|uart_mod.v:190|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:8"
.gate SB_DFFESR C=common.led_blink.clk D=common.pb.uart.arb_mod.rx E=$abc$44715$auto$dff2dffe.cc:175:make_patterns_logic$41660 Q=common.pb.uart.rx_mod.rx_buf[2] R=$abc$44715$auto$rtlil.cc:1969:NotGate$44581
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:395|uart_mod.v:537|uart_mod.v:190|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:8"
.gate SB_DFFESR C=common.led_blink.clk D=common.pb.uart.arb_mod.rx E=$abc$44715$auto$dff2dffe.cc:175:make_patterns_logic$41750 Q=common.pb.uart.rx_mod.rx_buf[3] R=$abc$44715$auto$rtlil.cc:1969:NotGate$44581
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:395|uart_mod.v:537|uart_mod.v:190|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:8"
.gate SB_DFFESR C=common.led_blink.clk D=common.pb.uart.arb_mod.rx E=$abc$44715$auto$dff2dffe.cc:175:make_patterns_logic$41840 Q=common.pb.uart.rx_mod.rx_buf[4] R=$abc$44715$auto$rtlil.cc:1969:NotGate$44581
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:395|uart_mod.v:537|uart_mod.v:190|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:8"
.gate SB_DFFESR C=common.led_blink.clk D=common.pb.uart.arb_mod.rx E=$abc$44715$auto$dff2dffe.cc:175:make_patterns_logic$41930 Q=common.pb.uart.rx_mod.rx_buf[5] R=$abc$44715$auto$rtlil.cc:1969:NotGate$44581
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:395|uart_mod.v:537|uart_mod.v:190|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:8"
.gate SB_DFFESR C=common.led_blink.clk D=common.pb.uart.arb_mod.rx E=$abc$44715$auto$dff2dffe.cc:175:make_patterns_logic$42020 Q=common.pb.uart.rx_mod.rx_buf[6] R=$abc$44715$auto$rtlil.cc:1969:NotGate$44581
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:395|uart_mod.v:537|uart_mod.v:190|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:8"
.gate SB_DFFESR C=common.led_blink.clk D=common.pb.uart.arb_mod.rx E=$abc$44715$auto$dff2dffe.cc:175:make_patterns_logic$42110 Q=common.pb.uart.rx_mod.rx_buf[7] R=$abc$44715$auto$rtlil.cc:1969:NotGate$44581
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:395|uart_mod.v:537|uart_mod.v:190|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:8"
.gate SB_DFFESR C=common.led_blink.clk D=$abc$44715$techmap\common.pb.uart.rx_mod.$procmux$15305_Y[0] E=$abc$44715$auto$dff2dffe.cc:175:make_patterns_logic$42153 Q=common.pb.uart.rx_mod.sym_count[0] R=$abc$44715$auto$rtlil.cc:1969:NotGate$44281
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:395|uart_mod.v:537|uart_mod.v:190|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:8"
.gate SB_DFFESR C=common.led_blink.clk D=$abc$44715$techmap\common.pb.uart.rx_mod.$procmux$15305_Y[1] E=$abc$44715$auto$dff2dffe.cc:175:make_patterns_logic$42153 Q=common.pb.uart.rx_mod.sym_count[1] R=$abc$44715$auto$rtlil.cc:1969:NotGate$44281
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:395|uart_mod.v:537|uart_mod.v:190|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:8"
.gate SB_DFFESR C=common.led_blink.clk D=$abc$44715$techmap\common.pb.uart.rx_mod.$procmux$15305_Y[2] E=$abc$44715$auto$dff2dffe.cc:175:make_patterns_logic$42153 Q=common.pb.uart.rx_mod.sym_count[2] R=$abc$44715$auto$rtlil.cc:1969:NotGate$44281
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:395|uart_mod.v:537|uart_mod.v:190|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:8"
.gate SB_DFFESR C=common.led_blink.clk D=$abc$44715$techmap\common.pb.uart.rx_mod.$procmux$15305_Y[3] E=$abc$44715$auto$dff2dffe.cc:175:make_patterns_logic$42153 Q=common.pb.uart.rx_mod.sym_count[3] R=$abc$44715$auto$rtlil.cc:1969:NotGate$44281
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:395|uart_mod.v:537|uart_mod.v:190|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:8"
.gate SB_DFFE C=common.led_blink.clk D=common.pb.uart.rx_mod.rx_buf[0] E=$abc$44715$auto$dff2dffe.cc:175:make_patterns_logic$42366 Q=common.pb.uart.rx_mod.rx_data[0]
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:395|uart_mod.v:537|uart_mod.v:190|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:8"
.gate SB_DFFE C=common.led_blink.clk D=common.pb.uart.rx_mod.rx_buf[1] E=$abc$44715$auto$dff2dffe.cc:175:make_patterns_logic$42366 Q=common.pb.uart.rx_mod.rx_data[1]
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:395|uart_mod.v:537|uart_mod.v:190|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:8"
.gate SB_DFFE C=common.led_blink.clk D=common.pb.uart.rx_mod.rx_buf[2] E=$abc$44715$auto$dff2dffe.cc:175:make_patterns_logic$42366 Q=common.pb.uart.rx_mod.rx_data[2]
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:395|uart_mod.v:537|uart_mod.v:190|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:8"
.gate SB_DFFE C=common.led_blink.clk D=common.pb.uart.rx_mod.rx_buf[3] E=$abc$44715$auto$dff2dffe.cc:175:make_patterns_logic$42366 Q=common.pb.uart.rx_mod.rx_data[3]
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:395|uart_mod.v:537|uart_mod.v:190|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:8"
.gate SB_DFFE C=common.led_blink.clk D=common.pb.uart.rx_mod.rx_buf[4] E=$abc$44715$auto$dff2dffe.cc:175:make_patterns_logic$42366 Q=common.pb.uart.rx_mod.rx_data[4]
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:395|uart_mod.v:537|uart_mod.v:190|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:8"
.gate SB_DFFE C=common.led_blink.clk D=common.pb.uart.rx_mod.rx_buf[5] E=$abc$44715$auto$dff2dffe.cc:175:make_patterns_logic$42366 Q=common.pb.uart.rx_mod.rx_data[5]
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:395|uart_mod.v:537|uart_mod.v:190|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:8"
.gate SB_DFFE C=common.led_blink.clk D=common.pb.uart.rx_mod.rx_buf[6] E=$abc$44715$auto$dff2dffe.cc:175:make_patterns_logic$42366 Q=common.pb.uart.rx_mod.rx_data[6]
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:395|uart_mod.v:537|uart_mod.v:190|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:8"
.gate SB_DFFE C=common.led_blink.clk D=common.pb.uart.rx_mod.rx_buf[7] E=$abc$44715$auto$dff2dffe.cc:175:make_patterns_logic$42366 Q=common.pb.uart.rx_mod.rx_data[7]
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:395|uart_mod.v:537|uart_mod.v:190|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:8"
.gate SB_DFFE C=common.led_blink.clk D=$abc$44715$techmap\common.pb.uart.rx_mod.$0\rx_frame_error[0:0] E=$abc$44715$auto$dff2dffe.cc:175:make_patterns_logic$42366 Q=common.pb.uart.rx_mod.rx_frame_error
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:395|uart_mod.v:537|uart_mod.v:190|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:8"
.gate SB_DFFE C=common.led_blink.clk D=$abc$44715$techmap\common.pb.uart.rx_mod.$0\rx_parity_ok[0:0] E=$abc$44715$auto$dff2dffe.cc:175:make_patterns_logic$42366 Q=common.pb.uart.rx_mod.rx_parity_ok
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:395|uart_mod.v:537|uart_mod.v:190|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:8"
.gate SB_DFFESR C=common.led_blink.clk D=$abc$44715$auto$rtlil.cc:1969:NotGate$44581 E=$abc$44715$auto$dff2dffe.cc:175:make_patterns_logic$41256 Q=common.pb.uart.rx_mod.rx_active R=$abc$44715$auto$rtlil.cc:1969:NotGate$44281
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:395|uart_mod.v:537|uart_mod.v:190|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:8"
.gate SB_DFFSR C=common.led_blink.clk D=$abc$44715$techmap\common.pb.uart.tx_mod.symclk.$eq$uart_mod.v:73$17_Y Q=common.pb.uart.tx_mod.symclk.setup R=$abc$44715$auto$rtlil.cc:1969:NotGate$44103
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:395|uart_mod.v:561|uart_mod.v:300|uart_mod.v:71|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:2"
.gate SB_DFFSR C=common.led_blink.clk D=$abc$44715$techmap\common.pb.uart.tx_mod.symclk.$procmux$15655_Y[0] Q=common.pb.uart.tx_mod.symclk.count[0] R=$abc$44715$auto$rtlil.cc:1969:NotGate$44103
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:395|uart_mod.v:561|uart_mod.v:300|uart_mod.v:71|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:2"
.gate SB_DFFSR C=common.led_blink.clk D=$abc$44715$techmap\common.pb.uart.tx_mod.symclk.$procmux$15655_Y[1] Q=common.pb.uart.tx_mod.symclk.count[1] R=$abc$44715$auto$rtlil.cc:1969:NotGate$44103
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:395|uart_mod.v:561|uart_mod.v:300|uart_mod.v:71|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:2"
.gate SB_DFFSR C=common.led_blink.clk D=$abc$44715$techmap\common.pb.uart.tx_mod.symclk.$procmux$15655_Y[2] Q=common.pb.uart.tx_mod.symclk.count[2] R=$abc$44715$auto$rtlil.cc:1969:NotGate$44103
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:395|uart_mod.v:561|uart_mod.v:300|uart_mod.v:71|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:2"
.gate SB_DFFSR C=common.led_blink.clk D=$abc$44715$techmap\common.pb.uart.tx_mod.symclk.$procmux$15655_Y[3] Q=common.pb.uart.tx_mod.symclk.count[3] R=$abc$44715$auto$rtlil.cc:1969:NotGate$44103
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:395|uart_mod.v:561|uart_mod.v:300|uart_mod.v:71|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:2"
.gate SB_DFFSR C=common.led_blink.clk D=$abc$44715$techmap\common.pb.uart.tx_mod.symclk.$procmux$15655_Y[4] Q=common.pb.uart.tx_mod.symclk.count[4] R=$abc$44715$auto$rtlil.cc:1969:NotGate$44103
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:395|uart_mod.v:561|uart_mod.v:300|uart_mod.v:71|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:2"
.gate SB_DFFSR C=common.led_blink.clk D=$abc$44715$techmap\common.pb.uart.tx_mod.symclk.$procmux$15655_Y[5] Q=common.pb.uart.tx_mod.symclk.count[5] R=$abc$44715$auto$rtlil.cc:1969:NotGate$44103
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:395|uart_mod.v:561|uart_mod.v:300|uart_mod.v:71|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:2"
.gate SB_DFFSR C=common.led_blink.clk D=$abc$44715$techmap\common.pb.uart.tx_mod.symclk.$procmux$15655_Y[6] Q=common.pb.uart.tx_mod.symclk.count[6] R=$abc$44715$auto$rtlil.cc:1969:NotGate$44103
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:395|uart_mod.v:561|uart_mod.v:300|uart_mod.v:71|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:2"
.gate SB_DFFSR C=common.led_blink.clk D=$abc$44715$techmap\common.pb.uart.tx_mod.symclk.$procmux$15655_Y[7] Q=common.pb.uart.tx_mod.symclk.count[7] R=$abc$44715$auto$rtlil.cc:1969:NotGate$44103
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:395|uart_mod.v:561|uart_mod.v:300|uart_mod.v:71|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:2"
.gate SB_DFFSR C=common.led_blink.clk D=$abc$44715$techmap\common.pb.uart.tx_mod.symclk.$procmux$15655_Y[8] Q=common.pb.uart.tx_mod.symclk.count[8] R=$abc$44715$auto$rtlil.cc:1969:NotGate$44103
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:395|uart_mod.v:561|uart_mod.v:300|uart_mod.v:71|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:2"
.gate SB_DFFSR C=common.led_blink.clk D=$abc$44715$techmap\common.pb.uart.tx_mod.symclk.$procmux$15655_Y[9] Q=common.pb.uart.tx_mod.symclk.count[9] R=$abc$44715$auto$rtlil.cc:1969:NotGate$44103
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:395|uart_mod.v:561|uart_mod.v:300|uart_mod.v:71|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:2"
.gate SB_DFFSR C=common.led_blink.clk D=$abc$44715$techmap\common.pb.uart.tx_mod.symclk.$procmux$15655_Y[10] Q=common.pb.uart.tx_mod.symclk.count[10] R=$abc$44715$auto$rtlil.cc:1969:NotGate$44103
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:395|uart_mod.v:561|uart_mod.v:300|uart_mod.v:71|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:2"
.gate SB_DFFSR C=common.led_blink.clk D=$abc$44715$techmap\common.pb.uart.tx_mod.symclk.$procmux$15655_Y[11] Q=common.pb.uart.tx_mod.symclk.count[11] R=$abc$44715$auto$rtlil.cc:1969:NotGate$44103
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:395|uart_mod.v:561|uart_mod.v:300|uart_mod.v:71|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:2"
.gate SB_DFFSR C=common.led_blink.clk D=$abc$44715$techmap\common.pb.uart.tx_mod.symclk.$procmux$15655_Y[12] Q=common.pb.uart.tx_mod.symclk.count[12] R=$abc$44715$auto$rtlil.cc:1969:NotGate$44103
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:395|uart_mod.v:561|uart_mod.v:300|uart_mod.v:71|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:2"
.gate SB_DFFSR C=common.led_blink.clk D=$abc$44715$techmap\common.pb.uart.tx_mod.symclk.$procmux$15655_Y[13] Q=common.pb.uart.tx_mod.symclk.count[13] R=$abc$44715$auto$rtlil.cc:1969:NotGate$44103
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:395|uart_mod.v:561|uart_mod.v:300|uart_mod.v:71|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:2"
.gate SB_DFFSR C=common.led_blink.clk D=$abc$44715$techmap\common.pb.uart.tx_mod.symclk.$procmux$15655_Y[14] Q=common.pb.uart.tx_mod.symclk.count[14] R=$abc$44715$auto$rtlil.cc:1969:NotGate$44103
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:395|uart_mod.v:561|uart_mod.v:300|uart_mod.v:71|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:2"
.gate SB_DFFSR C=common.led_blink.clk D=$abc$44715$techmap\common.pb.uart.tx_mod.symclk.$procmux$15655_Y[15] Q=common.pb.uart.tx_mod.symclk.count[15] R=$abc$44715$auto$rtlil.cc:1969:NotGate$44103
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:395|uart_mod.v:561|uart_mod.v:300|uart_mod.v:71|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:2"
.gate SB_DFFSR C=common.led_blink.clk D=$abc$44715$techmap\common.pb.uart.tx_mod.symclk.$procmux$15655_Y[16] Q=common.pb.uart.tx_mod.symclk.count[16] R=$abc$44715$auto$rtlil.cc:1969:NotGate$44103
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:395|uart_mod.v:561|uart_mod.v:300|uart_mod.v:71|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:2"
.gate SB_DFFSR C=common.led_blink.clk D=$abc$44715$techmap\common.pb.uart.tx_mod.symclk.$procmux$15655_Y[17] Q=common.pb.uart.tx_mod.symclk.count[17] R=$abc$44715$auto$rtlil.cc:1969:NotGate$44103
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:395|uart_mod.v:561|uart_mod.v:300|uart_mod.v:71|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:2"
.gate SB_DFFSR C=common.led_blink.clk D=$abc$44715$techmap\common.pb.uart.tx_mod.symclk.$procmux$15655_Y[18] Q=common.pb.uart.tx_mod.symclk.count[18] R=$abc$44715$auto$rtlil.cc:1969:NotGate$44103
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:395|uart_mod.v:561|uart_mod.v:300|uart_mod.v:71|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:2"
.gate SB_DFFSR C=common.led_blink.clk D=$abc$44715$techmap\common.pb.uart.tx_mod.symclk.$procmux$15655_Y[19] Q=common.pb.uart.tx_mod.symclk.count[19] R=$abc$44715$auto$rtlil.cc:1969:NotGate$44103
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:395|uart_mod.v:561|uart_mod.v:300|uart_mod.v:71|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:2"
.gate SB_DFFSR C=common.led_blink.clk D=$abc$44715$techmap\common.pb.uart.tx_mod.symclk.$procmux$15655_Y[20] Q=common.pb.uart.tx_mod.symclk.count[20] R=$abc$44715$auto$rtlil.cc:1969:NotGate$44103
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:395|uart_mod.v:561|uart_mod.v:300|uart_mod.v:71|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:2"
.gate SB_DFFSR C=common.led_blink.clk D=$abc$44715$techmap\common.pb.uart.tx_mod.symclk.$procmux$15655_Y[21] Q=common.pb.uart.tx_mod.symclk.count[21] R=$abc$44715$auto$rtlil.cc:1969:NotGate$44103
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:395|uart_mod.v:561|uart_mod.v:300|uart_mod.v:71|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:2"
.gate SB_DFFSR C=common.led_blink.clk D=$abc$44715$techmap\common.pb.uart.tx_mod.symclk.$procmux$15655_Y[22] Q=common.pb.uart.tx_mod.symclk.count[22] R=$abc$44715$auto$rtlil.cc:1969:NotGate$44103
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:395|uart_mod.v:561|uart_mod.v:300|uart_mod.v:71|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:2"
.gate SB_DFFSR C=common.led_blink.clk D=$abc$44715$techmap\common.pb.uart.tx_mod.symclk.$procmux$15655_Y[23] Q=common.pb.uart.tx_mod.symclk.count[23] R=$abc$44715$auto$rtlil.cc:1969:NotGate$44103
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:395|uart_mod.v:561|uart_mod.v:300|uart_mod.v:71|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:2"
.gate SB_DFFSR C=common.led_blink.clk D=$abc$44715$techmap\common.pb.uart.tx_mod.symclk.$procmux$15622_Y Q=common.pb.uart.tx_mod.symclk.symend R=$abc$44715$auto$rtlil.cc:1969:NotGate$44103
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:395|uart_mod.v:561|uart_mod.v:300|uart_mod.v:71|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:2"
.gate SB_DFFSR C=common.led_blink.clk D=$abc$44715$techmap\common.pb.uart.rx_mod.symclk.$procmux$15633_Y Q=common.pb.uart.rx_mod.symclk.sample R=$abc$44715$auto$rtlil.cc:1969:NotGate$44655
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:395|uart_mod.v:537|uart_mod.v:154|uart_mod.v:71|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:2"
.gate SB_DFFSR C=common.led_blink.clk D=$abc$44715$techmap\common.pb.uart.rx_mod.symclk.$procmux$15655_Y[0] Q=common.pb.uart.rx_mod.symclk.count[0] R=$abc$44715$auto$rtlil.cc:1969:NotGate$44655
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:395|uart_mod.v:537|uart_mod.v:154|uart_mod.v:71|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:2"
.gate SB_DFFSR C=common.led_blink.clk D=$abc$44715$techmap\common.pb.uart.rx_mod.symclk.$procmux$15655_Y[1] Q=common.pb.uart.rx_mod.symclk.count[1] R=$abc$44715$auto$rtlil.cc:1969:NotGate$44655
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:395|uart_mod.v:537|uart_mod.v:154|uart_mod.v:71|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:2"
.gate SB_DFFSR C=common.led_blink.clk D=$abc$44715$techmap\common.pb.uart.rx_mod.symclk.$procmux$15655_Y[2] Q=common.pb.uart.rx_mod.symclk.count[2] R=$abc$44715$auto$rtlil.cc:1969:NotGate$44655
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:395|uart_mod.v:537|uart_mod.v:154|uart_mod.v:71|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:2"
.gate SB_DFFSR C=common.led_blink.clk D=$abc$44715$techmap\common.pb.uart.rx_mod.symclk.$procmux$15655_Y[3] Q=common.pb.uart.rx_mod.symclk.count[3] R=$abc$44715$auto$rtlil.cc:1969:NotGate$44655
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:395|uart_mod.v:537|uart_mod.v:154|uart_mod.v:71|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:2"
.gate SB_DFFSR C=common.led_blink.clk D=$abc$44715$techmap\common.pb.uart.rx_mod.symclk.$procmux$15655_Y[4] Q=common.pb.uart.rx_mod.symclk.count[4] R=$abc$44715$auto$rtlil.cc:1969:NotGate$44655
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:395|uart_mod.v:537|uart_mod.v:154|uart_mod.v:71|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:2"
.gate SB_DFFSR C=common.led_blink.clk D=$abc$44715$techmap\common.pb.uart.rx_mod.symclk.$procmux$15655_Y[5] Q=common.pb.uart.rx_mod.symclk.count[5] R=$abc$44715$auto$rtlil.cc:1969:NotGate$44655
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:395|uart_mod.v:537|uart_mod.v:154|uart_mod.v:71|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:2"
.gate SB_DFFSR C=common.led_blink.clk D=$abc$44715$techmap\common.pb.uart.rx_mod.symclk.$procmux$15655_Y[6] Q=common.pb.uart.rx_mod.symclk.count[6] R=$abc$44715$auto$rtlil.cc:1969:NotGate$44655
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:395|uart_mod.v:537|uart_mod.v:154|uart_mod.v:71|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:2"
.gate SB_DFFSR C=common.led_blink.clk D=$abc$44715$techmap\common.pb.uart.rx_mod.symclk.$procmux$15655_Y[7] Q=common.pb.uart.rx_mod.symclk.count[7] R=$abc$44715$auto$rtlil.cc:1969:NotGate$44655
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:395|uart_mod.v:537|uart_mod.v:154|uart_mod.v:71|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:2"
.gate SB_DFFSR C=common.led_blink.clk D=$abc$44715$techmap\common.pb.uart.rx_mod.symclk.$procmux$15655_Y[8] Q=common.pb.uart.rx_mod.symclk.count[8] R=$abc$44715$auto$rtlil.cc:1969:NotGate$44655
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:395|uart_mod.v:537|uart_mod.v:154|uart_mod.v:71|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:2"
.gate SB_DFFSR C=common.led_blink.clk D=$abc$44715$techmap\common.pb.uart.rx_mod.symclk.$procmux$15655_Y[9] Q=common.pb.uart.rx_mod.symclk.count[9] R=$abc$44715$auto$rtlil.cc:1969:NotGate$44655
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:395|uart_mod.v:537|uart_mod.v:154|uart_mod.v:71|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:2"
.gate SB_DFFSR C=common.led_blink.clk D=$abc$44715$techmap\common.pb.uart.rx_mod.symclk.$procmux$15655_Y[10] Q=common.pb.uart.rx_mod.symclk.count[10] R=$abc$44715$auto$rtlil.cc:1969:NotGate$44655
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:395|uart_mod.v:537|uart_mod.v:154|uart_mod.v:71|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:2"
.gate SB_DFFSR C=common.led_blink.clk D=$abc$44715$techmap\common.pb.uart.rx_mod.symclk.$procmux$15655_Y[11] Q=common.pb.uart.rx_mod.symclk.count[11] R=$abc$44715$auto$rtlil.cc:1969:NotGate$44655
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:395|uart_mod.v:537|uart_mod.v:154|uart_mod.v:71|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:2"
.gate SB_DFFSR C=common.led_blink.clk D=$abc$44715$techmap\common.pb.uart.rx_mod.symclk.$procmux$15655_Y[12] Q=common.pb.uart.rx_mod.symclk.count[12] R=$abc$44715$auto$rtlil.cc:1969:NotGate$44655
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:395|uart_mod.v:537|uart_mod.v:154|uart_mod.v:71|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:2"
.gate SB_DFFSR C=common.led_blink.clk D=$abc$44715$techmap\common.pb.uart.rx_mod.symclk.$procmux$15655_Y[13] Q=common.pb.uart.rx_mod.symclk.count[13] R=$abc$44715$auto$rtlil.cc:1969:NotGate$44655
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:395|uart_mod.v:537|uart_mod.v:154|uart_mod.v:71|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:2"
.gate SB_DFFSR C=common.led_blink.clk D=$abc$44715$techmap\common.pb.uart.rx_mod.symclk.$procmux$15655_Y[14] Q=common.pb.uart.rx_mod.symclk.count[14] R=$abc$44715$auto$rtlil.cc:1969:NotGate$44655
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:395|uart_mod.v:537|uart_mod.v:154|uart_mod.v:71|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:2"
.gate SB_DFFSR C=common.led_blink.clk D=$abc$44715$techmap\common.pb.uart.rx_mod.symclk.$procmux$15655_Y[15] Q=common.pb.uart.rx_mod.symclk.count[15] R=$abc$44715$auto$rtlil.cc:1969:NotGate$44655
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:395|uart_mod.v:537|uart_mod.v:154|uart_mod.v:71|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:2"
.gate SB_DFFSR C=common.led_blink.clk D=$abc$44715$techmap\common.pb.uart.rx_mod.symclk.$procmux$15655_Y[16] Q=common.pb.uart.rx_mod.symclk.count[16] R=$abc$44715$auto$rtlil.cc:1969:NotGate$44655
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:395|uart_mod.v:537|uart_mod.v:154|uart_mod.v:71|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:2"
.gate SB_DFFSR C=common.led_blink.clk D=$abc$44715$techmap\common.pb.uart.rx_mod.symclk.$procmux$15655_Y[17] Q=common.pb.uart.rx_mod.symclk.count[17] R=$abc$44715$auto$rtlil.cc:1969:NotGate$44655
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:395|uart_mod.v:537|uart_mod.v:154|uart_mod.v:71|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:2"
.gate SB_DFFSR C=common.led_blink.clk D=$abc$44715$techmap\common.pb.uart.rx_mod.symclk.$procmux$15655_Y[18] Q=common.pb.uart.rx_mod.symclk.count[18] R=$abc$44715$auto$rtlil.cc:1969:NotGate$44655
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:395|uart_mod.v:537|uart_mod.v:154|uart_mod.v:71|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:2"
.gate SB_DFFSR C=common.led_blink.clk D=$abc$44715$techmap\common.pb.uart.rx_mod.symclk.$procmux$15655_Y[19] Q=common.pb.uart.rx_mod.symclk.count[19] R=$abc$44715$auto$rtlil.cc:1969:NotGate$44655
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:395|uart_mod.v:537|uart_mod.v:154|uart_mod.v:71|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:2"
.gate SB_DFFSR C=common.led_blink.clk D=$abc$44715$techmap\common.pb.uart.rx_mod.symclk.$procmux$15655_Y[20] Q=common.pb.uart.rx_mod.symclk.count[20] R=$abc$44715$auto$rtlil.cc:1969:NotGate$44655
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:395|uart_mod.v:537|uart_mod.v:154|uart_mod.v:71|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:2"
.gate SB_DFFSR C=common.led_blink.clk D=$abc$44715$techmap\common.pb.uart.rx_mod.symclk.$procmux$15655_Y[21] Q=common.pb.uart.rx_mod.symclk.count[21] R=$abc$44715$auto$rtlil.cc:1969:NotGate$44655
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:395|uart_mod.v:537|uart_mod.v:154|uart_mod.v:71|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:2"
.gate SB_DFFSR C=common.led_blink.clk D=$abc$44715$techmap\common.pb.uart.rx_mod.symclk.$procmux$15655_Y[22] Q=common.pb.uart.rx_mod.symclk.count[22] R=$abc$44715$auto$rtlil.cc:1969:NotGate$44655
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:395|uart_mod.v:537|uart_mod.v:154|uart_mod.v:71|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:2"
.gate SB_DFFSR C=common.led_blink.clk D=$abc$44715$techmap\common.pb.uart.rx_mod.symclk.$procmux$15655_Y[23] Q=common.pb.uart.rx_mod.symclk.count[23] R=$abc$44715$auto$rtlil.cc:1969:NotGate$44655
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:395|uart_mod.v:537|uart_mod.v:154|uart_mod.v:71|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:2"
.gate SB_DFFSR C=common.led_blink.clk D=$abc$44715$techmap\common.pb.uart.rx_mod.symclk.$procmux$15622_Y Q=common.pb.uart.rx_mod.symclk.symend R=$abc$44715$auto$rtlil.cc:1969:NotGate$44655
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:395|uart_mod.v:537|uart_mod.v:154|uart_mod.v:71|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:2"
.gate SB_DFF C=common.led_blink.clk D=common.pb.uart.arb_mod.rx Q=common.pb.uart.rx_mod.rx_edge.prev_signal
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:206|main.v:74|profibus_phy_mod.v:395|uart_mod.v:537|uart_mod.v:142|edge_detect_mod.v:36|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v:2"
.gate SB_RAM40_4K MASK[0]=$abc$44715$auto$opt_expr.cc:189:group_cell_inputs$16197 MASK[1]=$abc$44715$auto$opt_expr.cc:189:group_cell_inputs$16197 MASK[2]=$abc$44715$auto$opt_expr.cc:189:group_cell_inputs$16197 MASK[3]=$abc$44715$auto$opt_expr.cc:189:group_cell_inputs$16197 MASK[4]=$abc$44715$auto$opt_expr.cc:189:group_cell_inputs$16197 MASK[5]=$abc$44715$auto$opt_expr.cc:189:group_cell_inputs$16197 MASK[6]=$abc$44715$auto$opt_expr.cc:189:group_cell_inputs$16197 MASK[7]=$abc$44715$auto$opt_expr.cc:189:group_cell_inputs$16197 MASK[8]=$abc$44715$auto$opt_expr.cc:189:group_cell_inputs$16197 MASK[9]=$true MASK[10]=$true MASK[11]=$true MASK[12]=$true MASK[13]=$true MASK[14]=$true MASK[15]=$true RADDR[0]=common.pb.rx_buf_rd_addr[0] RADDR[1]=common.pb.rx_buf_rd_addr[1] RADDR[2]=common.pb.rx_buf_rd_addr[2] RADDR[3]=common.pb.rx_buf_rd_addr[3] RADDR[4]=common.pb.rx_buf_rd_addr[4] RADDR[5]=common.pb.rx_buf_rd_addr[5] RADDR[6]=common.pb.rx_buf_rd_addr[6] RADDR[7]=common.pb.rx_buf_rd_addr[7] RADDR[8]=$false RADDR[9]=$false RADDR[10]=$false RCLK=common.led_blink.clk RCLKE=$true RDATA[0]=common.pb.rx_buf_rd_data[0] RDATA[1]=common.pb.rx_buf_rd_data[1] RDATA[2]=common.pb.rx_buf_rd_data[2] RDATA[3]=common.pb.rx_buf_rd_data[3] RDATA[4]=common.pb.rx_buf_rd_data[4] RDATA[5]=common.pb.rx_buf_rd_data[5] RDATA[6]=common.pb.rx_buf_rd_data[6] RDATA[7]=common.pb.rx_buf_rd_data[7] RDATA[8]=common.pb.rx_buf_rd_data[8] RDATA[9]=$auto$memory_bram.cc:926:replace_cell$16185[9] RDATA[10]=$auto$memory_bram.cc:926:replace_cell$16185[10] RDATA[11]=$auto$memory_bram.cc:926:replace_cell$16185[11] RDATA[12]=$auto$memory_bram.cc:926:replace_cell$16185[12] RDATA[13]=$auto$memory_bram.cc:926:replace_cell$16185[13] RDATA[14]=$auto$memory_bram.cc:926:replace_cell$16185[14] RDATA[15]=$auto$memory_bram.cc:926:replace_cell$16185[15] RE=$true WADDR[0]=common.pb.rx_buf_wr_addr[0] WADDR[1]=common.pb.rx_buf_wr_addr[1] WADDR[2]=common.pb.rx_buf_wr_addr[2] WADDR[3]=common.pb.rx_buf_wr_addr[3] WADDR[4]=common.pb.rx_buf_wr_addr[4] WADDR[5]=common.pb.rx_buf_wr_addr[5] WADDR[6]=common.pb.rx_buf_wr_addr[6] WADDR[7]=common.pb.rx_buf_wr_addr[7] WADDR[8]=$false WADDR[9]=$false WADDR[10]=$false WCLK=common.led_blink.clk WCLKE=common.pb.rx_buf_wr WDATA[0]=common.pb.rx_buf_wr_data[0] WDATA[1]=common.pb.rx_buf_wr_data[1] WDATA[2]=common.pb.rx_buf_wr_data[2] WDATA[3]=common.pb.rx_buf_wr_data[3] WDATA[4]=common.pb.rx_buf_wr_data[4] WDATA[5]=common.pb.rx_buf_wr_data[5] WDATA[6]=common.pb.rx_buf_wr_data[6] WDATA[7]=common.pb.rx_buf_wr_data[7] WDATA[8]=common.pb.rx_buf_wr_data[8] WDATA[9]=$false WDATA[10]=$false WDATA[11]=$false WDATA[12]=$false WDATA[13]=$false WDATA[14]=$false WDATA[15]=$false WE=$true
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/brams_map.v:191|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/brams_map.v:35"
.param INIT_0 xxxxxxx000000000xxxxxxx000000000xxxxxxx000000000xxxxxxx000000000xxxxxxx000000000xxxxxxx000000000xxxxxxx000000000xxxxxxx000000000xxxxxxx000000000xxxxxxx000000000xxxxxxx000000000xxxxxxx000000000xxxxxxx000000000xxxxxxx000000000xxxxxxx000000000xxxxxxx000000000
.param INIT_1 xxxxxxx000000000xxxxxxx000000000xxxxxxx000000000xxxxxxx000000000xxxxxxx000000000xxxxxxx000000000xxxxxxx000000000xxxxxxx000000000xxxxxxx000000000xxxxxxx000000000xxxxxxx000000000xxxxxxx000000000xxxxxxx000000000xxxxxxx000000000xxxxxxx000000000xxxxxxx000000000
.param INIT_2 xxxxxxx000000000xxxxxxx000000000xxxxxxx000000000xxxxxxx000000000xxxxxxx000000000xxxxxxx000000000xxxxxxx000000000xxxxxxx000000000xxxxxxx000000000xxxxxxx000000000xxxxxxx000000000xxxxxxx000000000xxxxxxx000000000xxxxxxx000000000xxxxxxx000000000xxxxxxx000000000
.param INIT_3 xxxxxxx000000000xxxxxxx000000000xxxxxxx000000000xxxxxxx000000000xxxxxxx000000000xxxxxxx000000000xxxxxxx000000000xxxxxxx000000000xxxxxxx000000000xxxxxxx000000000xxxxxxx000000000xxxxxxx000000000xxxxxxx000000000xxxxxxx000000000xxxxxxx000000000xxxxxxx000000000
.param INIT_4 xxxxxxx000000000xxxxxxx000000000xxxxxxx000000000xxxxxxx000000000xxxxxxx000000000xxxxxxx000000000xxxxxxx000000000xxxxxxx000000000xxxxxxx000000000xxxxxxx000000000xxxxxxx000000000xxxxxxx000000000xxxxxxx000000000xxxxxxx000000000xxxxxxx000000000xxxxxxx000000000
.param INIT_5 xxxxxxx000000000xxxxxxx000000000xxxxxxx000000000xxxxxxx000000000xxxxxxx000000000xxxxxxx000000000xxxxxxx000000000xxxxxxx000000000xxxxxxx000000000xxxxxxx000000000xxxxxxx000000000xxxxxxx000000000xxxxxxx000000000xxxxxxx000000000xxxxxxx000000000xxxxxxx000000000
.param INIT_6 xxxxxxx000000000xxxxxxx000000000xxxxxxx000000000xxxxxxx000000000xxxxxxx000000000xxxxxxx000000000xxxxxxx000000000xxxxxxx000000000xxxxxxx000000000xxxxxxx000000000xxxxxxx000000000xxxxxxx000000000xxxxxxx000000000xxxxxxx000000000xxxxxxx000000000xxxxxxx000000000
.param INIT_7 xxxxxxx000000000xxxxxxx000000000xxxxxxx000000000xxxxxxx000000000xxxxxxx000000000xxxxxxx000000000xxxxxxx000000000xxxxxxx000000000xxxxxxx000000000xxxxxxx000000000xxxxxxx000000000xxxxxxx000000000xxxxxxx000000000xxxxxxx000000000xxxxxxx000000000xxxxxxx000000000
.param INIT_8 xxxxxxx000000000xxxxxxx000000000xxxxxxx000000000xxxxxxx000000000xxxxxxx000000000xxxxxxx000000000xxxxxxx000000000xxxxxxx000000000xxxxxxx000000000xxxxxxx000000000xxxxxxx000000000xxxxxxx000000000xxxxxxx000000000xxxxxxx000000000xxxxxxx000000000xxxxxxx000000000
.param INIT_9 xxxxxxx000000000xxxxxxx000000000xxxxxxx000000000xxxxxxx000000000xxxxxxx000000000xxxxxxx000000000xxxxxxx000000000xxxxxxx000000000xxxxxxx000000000xxxxxxx000000000xxxxxxx000000000xxxxxxx000000000xxxxxxx000000000xxxxxxx000000000xxxxxxx000000000xxxxxxx000000000
.param INIT_A xxxxxxx000000000xxxxxxx000000000xxxxxxx000000000xxxxxxx000000000xxxxxxx000000000xxxxxxx000000000xxxxxxx000000000xxxxxxx000000000xxxxxxx000000000xxxxxxx000000000xxxxxxx000000000xxxxxxx000000000xxxxxxx000000000xxxxxxx000000000xxxxxxx000000000xxxxxxx000000000
.param INIT_B xxxxxxx000000000xxxxxxx000000000xxxxxxx000000000xxxxxxx000000000xxxxxxx000000000xxxxxxx000000000xxxxxxx000000000xxxxxxx000000000xxxxxxx000000000xxxxxxx000000000xxxxxxx000000000xxxxxxx000000000xxxxxxx000000000xxxxxxx000000000xxxxxxx000000000xxxxxxx000000000
.param INIT_C xxxxxxx000000000xxxxxxx000000000xxxxxxx000000000xxxxxxx000000000xxxxxxx000000000xxxxxxx000000000xxxxxxx000000000xxxxxxx000000000xxxxxxx000000000xxxxxxx000000000xxxxxxx000000000xxxxxxx000000000xxxxxxx000000000xxxxxxx000000000xxxxxxx000000000xxxxxxx000000000
.param INIT_D xxxxxxx000000000xxxxxxx000000000xxxxxxx000000000xxxxxxx000000000xxxxxxx000000000xxxxxxx000000000xxxxxxx000000000xxxxxxx000000000xxxxxxx000000000xxxxxxx000000000xxxxxxx000000000xxxxxxx000000000xxxxxxx000000000xxxxxxx000000000xxxxxxx000000000xxxxxxx000000000
.param INIT_E xxxxxxx000000000xxxxxxx000000000xxxxxxx000000000xxxxxxx000000000xxxxxxx000000000xxxxxxx000000000xxxxxxx000000000xxxxxxx000000000xxxxxxx000000000xxxxxxx000000000xxxxxxx000000000xxxxxxx000000000xxxxxxx000000000xxxxxxx000000000xxxxxxx000000000xxxxxxx000000000
.param INIT_F xxxxxxx000000000xxxxxxx000000000xxxxxxx000000000xxxxxxx000000000xxxxxxx000000000xxxxxxx000000000xxxxxxx000000000xxxxxxx000000000xxxxxxx000000000xxxxxxx000000000xxxxxxx000000000xxxxxxx000000000xxxxxxx000000000xxxxxxx000000000xxxxxxx000000000xxxxxxx000000000
.param READ_MODE 00
.param WRITE_MODE 00
.gate SB_RAM40_4K MASK[0]=$undef MASK[1]=$undef MASK[2]=$undef MASK[3]=$undef MASK[4]=$undef MASK[5]=$undef MASK[6]=$undef MASK[7]=$undef MASK[8]=$undef MASK[9]=$undef MASK[10]=$undef MASK[11]=$undef MASK[12]=$undef MASK[13]=$undef MASK[14]=$undef MASK[15]=$undef RADDR[0]=common.pb.tx_buf_rd_addr[0] RADDR[1]=common.pb.tx_buf_rd_addr[1] RADDR[2]=common.pb.tx_buf_rd_addr[2] RADDR[3]=common.pb.tx_buf_rd_addr[3] RADDR[4]=common.pb.tx_buf_rd_addr[4] RADDR[5]=common.pb.tx_buf_rd_addr[5] RADDR[6]=common.pb.tx_buf_rd_addr[6] RADDR[7]=common.pb.tx_buf_rd_addr[7] RADDR[8]=$false RADDR[9]=$false RADDR[10]=$false RCLK=common.led_blink.clk RCLKE=$true RDATA[0]=common.pb.tx_buf.rd_data1[0] RDATA[1]=$techmap16191\common.pb.tx_buf.mem.0.0.0.A1DATA_16[1] RDATA[2]=common.pb.tx_buf.rd_data1[1] RDATA[3]=$techmap16191\common.pb.tx_buf.mem.0.0.0.A1DATA_16[3] RDATA[4]=common.pb.tx_buf.rd_data1[2] RDATA[5]=$techmap16191\common.pb.tx_buf.mem.0.0.0.A1DATA_16[5] RDATA[6]=common.pb.tx_buf.rd_data1[3] RDATA[7]=$techmap16191\common.pb.tx_buf.mem.0.0.0.A1DATA_16[7] RDATA[8]=common.pb.tx_buf.rd_data1[4] RDATA[9]=$techmap16191\common.pb.tx_buf.mem.0.0.0.A1DATA_16[9] RDATA[10]=common.pb.tx_buf.rd_data1[5] RDATA[11]=$techmap16191\common.pb.tx_buf.mem.0.0.0.A1DATA_16[11] RDATA[12]=common.pb.tx_buf.rd_data1[6] RDATA[13]=$techmap16191\common.pb.tx_buf.mem.0.0.0.A1DATA_16[13] RDATA[14]=common.pb.tx_buf.rd_data1[7] RDATA[15]=$techmap16191\common.pb.tx_buf.mem.0.0.0.A1DATA_16[15] RE=$true WADDR[0]=common.pb.tx_buf_wr_addr[0] WADDR[1]=common.pb.tx_buf_wr_addr[1] WADDR[2]=common.pb.tx_buf_wr_addr[2] WADDR[3]=common.pb.tx_buf_wr_addr[3] WADDR[4]=common.pb.tx_buf_wr_addr[4] WADDR[5]=common.pb.tx_buf_wr_addr[5] WADDR[6]=common.pb.tx_buf_wr_addr[6] WADDR[7]=common.pb.tx_buf_wr_addr[7] WADDR[8]=$false WADDR[9]=$false WADDR[10]=$false WCLK=common.led_blink.clk WCLKE=common.pb.tx_buf_wr WDATA[0]=common.pb.tx_buf_wr_data[0] WDATA[1]=$undef WDATA[2]=common.pb.tx_buf_wr_data[1] WDATA[3]=$undef WDATA[4]=common.pb.tx_buf_wr_data[2] WDATA[5]=$undef WDATA[6]=common.pb.tx_buf_wr_data[3] WDATA[7]=$undef WDATA[8]=common.pb.tx_buf_wr_data[4] WDATA[9]=$undef WDATA[10]=common.pb.tx_buf_wr_data[5] WDATA[11]=$undef WDATA[12]=common.pb.tx_buf_wr_data[6] WDATA[13]=$undef WDATA[14]=common.pb.tx_buf_wr_data[7] WDATA[15]=$undef WE=$true
.attr module_not_derived 00000000000000000000000000000001
.attr src "/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/brams_map.v:277|/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/brams_map.v:35"
.param INIT_0 x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0
.param INIT_1 x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0
.param INIT_2 x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0
.param INIT_3 x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0
.param INIT_4 x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0
.param INIT_5 x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0
.param INIT_6 x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0
.param INIT_7 x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0
.param INIT_8 x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0
.param INIT_9 x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0
.param INIT_A x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0
.param INIT_B x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0
.param INIT_C x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0
.param INIT_D x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0
.param INIT_E x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0
.param INIT_F x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0x0
.param READ_MODE 01
.param WRITE_MODE 01
.gate SB_PLL40_CORE BYPASS=$false LOCK=pll.locked PLLOUTCORE=common.led_blink.clk REFERENCECLK=CLK RESETB=$true
.attr module_not_derived 00000000000000000000000000000001
.attr src "main.v:197|pll_mod.v:19"
.param DIVF 0101111
.param DIVQ 101
.param DIVR 0000
.param FEEDBACK_PATH "SIMPLE"
.param FILTER_RANGE 001
.names $true $auto$alumacc.cc:474:replace_alu$15981.C[0]
1 1
.names $true $auto$alumacc.cc:474:replace_alu$15994.C[0]
1 1
.names $true $auto$alumacc.cc:474:replace_alu$16007.C[0]
1 1
.names $abc$44715$auto$alumacc.cc:474:replace_alu$16007.BB[0] $auto$alumacc.cc:474:replace_alu$16007.C[1]
1 1
.names $true $auto$alumacc.cc:474:replace_alu$16016.C[0]
1 1
.names common.pb.spirx_lencalc_byte[0] $auto$alumacc.cc:474:replace_alu$16016.C[1]
1 1
.names $true $auto$alumacc.cc:474:replace_alu$16025.C[0]
1 1
.names $abc$44715$auto$alumacc.cc:474:replace_alu$16025.BB[0] $auto$alumacc.cc:474:replace_alu$16025.C[1]
1 1
.names $true $auto$alumacc.cc:474:replace_alu$16034.C[0]
1 1
.names $abc$44715$auto$alumacc.cc:474:replace_alu$16034.BB[0] $auto$alumacc.cc:474:replace_alu$16034.C[1]
1 1
.names $true $auto$alumacc.cc:474:replace_alu$16047.C[0]
1 1
.names common.pb.timer_idle[0] $auto$alumacc.cc:474:replace_alu$16047.C[1]
1 1
.names $true $auto$alumacc.cc:474:replace_alu$16052.C[0]
1 1
.names $true $auto$alumacc.cc:474:replace_alu$16052.C[1]
1 1
.names $abc$44715$auto$alumacc.cc:474:replace_alu$16052.BB[1] $auto$alumacc.cc:474:replace_alu$16052.C[2]
1 1
.names $true $auto$alumacc.cc:474:replace_alu$16065.C[0]
1 1
.names $true $auto$alumacc.cc:474:replace_alu$16065.C[1]
1 1
.names $true $auto$alumacc.cc:474:replace_alu$16065.C[2]
1 1
.names $abc$44715$auto$alumacc.cc:474:replace_alu$16052.BB[2] $auto$alumacc.cc:474:replace_alu$16065.C[3]
1 1
.names $true $auto$alumacc.cc:474:replace_alu$16074.C[0]
1 1
.names $abc$44715$auto$alumacc.cc:474:replace_alu$16052.BB[0] $auto$alumacc.cc:474:replace_alu$16074.C[1]
1 1
.names $true $auto$alumacc.cc:474:replace_alu$16083.C[0]
1 1
.names $true $auto$alumacc.cc:474:replace_alu$16083.C[1]
1 1
.names $true $auto$alumacc.cc:474:replace_alu$16083.C[2]
1 1
.names $abc$44715$auto$alumacc.cc:474:replace_alu$16083.BB[2] $auto$alumacc.cc:474:replace_alu$16083.C[3]
1 1
.names $true $auto$alumacc.cc:474:replace_alu$16092.C[0]
1 1
.names $true $auto$alumacc.cc:474:replace_alu$16105.C[0]
1 1
.names $true $auto$alumacc.cc:474:replace_alu$16118.C[0]
1 1
.names common.led_blink.led_on_count[0] $auto$alumacc.cc:474:replace_alu$16118.C[1]
1 1
.names $true $auto$alumacc.cc:474:replace_alu$16121.C[0]
1 1
.names common.led_blink.led_off_count[0] $auto$alumacc.cc:474:replace_alu$16121.C[1]
1 1
.names $false $auto$alumacc.cc:474:replace_alu$16124.C[0]
1 1
.names common.pb.timer_idle[0] $auto$alumacc.cc:474:replace_alu$16124.C[1]
1 1
.names $false $auto$alumacc.cc:474:replace_alu$16127.C[0]
1 1
.names common.pb.tx_buf_wr_addr[0] $auto$alumacc.cc:474:replace_alu$16127.C[1]
1 1
.names $false $auto$alumacc.cc:474:replace_alu$16130.C[0]
1 1
.names common.pb.rx_buf_wr_addr[0] $auto$alumacc.cc:474:replace_alu$16130.C[1]
1 1
.names $false $auto$alumacc.cc:474:replace_alu$16133.C[0]
1 1
.names common.pb.tx_buf_rd_addr[0] $auto$alumacc.cc:474:replace_alu$16133.C[1]
1 1
.names $false $auto$alumacc.cc:474:replace_alu$16136.C[0]
1 1
.names common.pb.spirx_bytecount[0] $auto$alumacc.cc:474:replace_alu$16136.C[1]
1 1
.names $false $auto$alumacc.cc:474:replace_alu$16139.C[0]
1 1
.names $false $auto$alumacc.cc:474:replace_alu$16139.C[1]
1 1
.names $false $auto$alumacc.cc:474:replace_alu$16139.C[2]
1 1
.names $false $auto$alumacc.cc:474:replace_alu$16139.C[3]
1 1
.names $false $auto$alumacc.cc:474:replace_alu$16139.C[4]
1 1
.names $false $auto$alumacc.cc:474:replace_alu$16139.C[5]
1 1
.names $false $auto$alumacc.cc:474:replace_alu$16142.C[0]
1 1
.names common.pb.spitx_bytecount[0] $auto$alumacc.cc:474:replace_alu$16142.C[1]
1 1
.names $false $auto$alumacc.cc:474:replace_alu$16145.C[0]
1 1
.names common.pb.rx_buf_rd_addr[0] $auto$alumacc.cc:474:replace_alu$16145.C[1]
1 1
.names $false $auto$alumacc.cc:474:replace_alu$16148.C[0]
1 1
.names common.pb.spitx_len[0] $auto$alumacc.cc:474:replace_alu$16148.C[1]
1 1
.names $false $auto$alumacc.cc:474:replace_alu$16151.C[0]
1 1
.names common.pb.spi.bit_count[0] $auto$alumacc.cc:474:replace_alu$16151.C[1]
1 1
.names $false $auto$alumacc.cc:474:replace_alu$16154.C[0]
1 1
.names $false $auto$alumacc.cc:474:replace_alu$16154.C[1]
1 1
.names common.pb.spirx_lencalc.byte_le[1] $auto$alumacc.cc:474:replace_alu$16154.C[2]
1 1
.names $false $auto$alumacc.cc:474:replace_alu$16157.C[0]
1 1
.names common.pb.uart.rx_mod.sym_count[0] $auto$alumacc.cc:474:replace_alu$16157.C[1]
1 1
.names $true $auto$alumacc.cc:474:replace_alu$16160.C[0]
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.names $true $auto$alumacc.cc:474:replace_alu$16160.C[1]
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.names common.pb.uart.rx_mod.sym_count[1] $auto$alumacc.cc:474:replace_alu$16160.C[2]
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.names $abc$44715$auto$alumacc.cc:474:replace_alu$16160.C[31] $auto$alumacc.cc:474:replace_alu$16160.C[4]
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.names $abc$44715$auto$alumacc.cc:474:replace_alu$16160.C[31] $auto$alumacc.cc:474:replace_alu$16160.C[19]
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.names $abc$44715$auto$alumacc.cc:474:replace_alu$16160.C[31] $auto$alumacc.cc:474:replace_alu$16160.C[20]
1 1
.names $abc$44715$auto$alumacc.cc:474:replace_alu$16160.C[31] $auto$alumacc.cc:474:replace_alu$16160.C[21]
1 1
.names $abc$44715$auto$alumacc.cc:474:replace_alu$16160.C[31] $auto$alumacc.cc:474:replace_alu$16160.C[22]
1 1
.names $abc$44715$auto$alumacc.cc:474:replace_alu$16160.C[31] $auto$alumacc.cc:474:replace_alu$16160.C[23]
1 1
.names $abc$44715$auto$alumacc.cc:474:replace_alu$16160.C[31] $auto$alumacc.cc:474:replace_alu$16160.C[24]
1 1
.names $abc$44715$auto$alumacc.cc:474:replace_alu$16160.C[31] $auto$alumacc.cc:474:replace_alu$16160.C[25]
1 1
.names $abc$44715$auto$alumacc.cc:474:replace_alu$16160.C[31] $auto$alumacc.cc:474:replace_alu$16160.C[26]
1 1
.names $abc$44715$auto$alumacc.cc:474:replace_alu$16160.C[31] $auto$alumacc.cc:474:replace_alu$16160.C[27]
1 1
.names $abc$44715$auto$alumacc.cc:474:replace_alu$16160.C[31] $auto$alumacc.cc:474:replace_alu$16160.C[28]
1 1
.names $abc$44715$auto$alumacc.cc:474:replace_alu$16160.C[31] $auto$alumacc.cc:474:replace_alu$16160.C[29]
1 1
.names $abc$44715$auto$alumacc.cc:474:replace_alu$16160.C[31] $auto$alumacc.cc:474:replace_alu$16160.C[30]
1 1
.names $abc$44715$auto$alumacc.cc:474:replace_alu$16160.C[31] $auto$alumacc.cc:474:replace_alu$16160.C[31]
1 1
.names $false $auto$alumacc.cc:474:replace_alu$16163.C[0]
1 1
.names common.pb.uart.rx_mod.symclk.count[0] $auto$alumacc.cc:474:replace_alu$16163.C[1]
1 1
.names $true $auto$alumacc.cc:474:replace_alu$16166.C[0]
1 1
.names common.pb.uart.tx_mod.symclk.clks_per_sym_limited[1] $auto$alumacc.cc:474:replace_alu$16166.C[1]
1 1
.names $abc$44715$auto$alumacc.cc:474:replace_alu$16166.C[31] $auto$alumacc.cc:474:replace_alu$16166.C[23]
1 1
.names $abc$44715$auto$alumacc.cc:474:replace_alu$16166.C[31] $auto$alumacc.cc:474:replace_alu$16166.C[24]
1 1
.names $abc$44715$auto$alumacc.cc:474:replace_alu$16166.C[31] $auto$alumacc.cc:474:replace_alu$16166.C[25]
1 1
.names $abc$44715$auto$alumacc.cc:474:replace_alu$16166.C[31] $auto$alumacc.cc:474:replace_alu$16166.C[26]
1 1
.names $abc$44715$auto$alumacc.cc:474:replace_alu$16166.C[31] $auto$alumacc.cc:474:replace_alu$16166.C[27]
1 1
.names $abc$44715$auto$alumacc.cc:474:replace_alu$16166.C[31] $auto$alumacc.cc:474:replace_alu$16166.C[28]
1 1
.names $abc$44715$auto$alumacc.cc:474:replace_alu$16166.C[31] $auto$alumacc.cc:474:replace_alu$16166.C[29]
1 1
.names $abc$44715$auto$alumacc.cc:474:replace_alu$16166.C[31] $auto$alumacc.cc:474:replace_alu$16166.C[30]
1 1
.names $abc$44715$auto$alumacc.cc:474:replace_alu$16166.C[31] $auto$alumacc.cc:474:replace_alu$16166.C[31]
1 1
.names $true $auto$alumacc.cc:474:replace_alu$16169.C[0]
1 1
.names common.pb.uart.rx_mod.symclk.clks_per_sym_limited $auto$alumacc.cc:474:replace_alu$16169.C[1]
1 1
.names $abc$44715$auto$alumacc.cc:474:replace_alu$15981.BB[31] $auto$alumacc.cc:474:replace_alu$16169.C[24]
1 1
.names $abc$44715$auto$alumacc.cc:474:replace_alu$15981.BB[31] $auto$alumacc.cc:474:replace_alu$16169.C[25]
1 1
.names $abc$44715$auto$alumacc.cc:474:replace_alu$15981.BB[31] $auto$alumacc.cc:474:replace_alu$16169.C[26]
1 1
.names $abc$44715$auto$alumacc.cc:474:replace_alu$15981.BB[31] $auto$alumacc.cc:474:replace_alu$16169.C[27]
1 1
.names $abc$44715$auto$alumacc.cc:474:replace_alu$15981.BB[31] $auto$alumacc.cc:474:replace_alu$16169.C[28]
1 1
.names $abc$44715$auto$alumacc.cc:474:replace_alu$15981.BB[31] $auto$alumacc.cc:474:replace_alu$16169.C[29]
1 1
.names $abc$44715$auto$alumacc.cc:474:replace_alu$15981.BB[31] $auto$alumacc.cc:474:replace_alu$16169.C[30]
1 1
.names $abc$44715$auto$alumacc.cc:474:replace_alu$15981.BB[31] $auto$alumacc.cc:474:replace_alu$16169.C[31]
1 1
.names $false $auto$alumacc.cc:474:replace_alu$16172.C[0]
1 1
.names common.pb.uart.tx_mod.sym_count[0] $auto$alumacc.cc:474:replace_alu$16172.C[1]
1 1
.names $false $auto$alumacc.cc:474:replace_alu$16178.C[0]
1 1
.names common.pb.uart.tx_mod.symclk.count[0] $auto$alumacc.cc:474:replace_alu$16178.C[1]
1 1
.names common.pb.rx_buf_rd_data[0] $auto$memory_bram.cc:926:replace_cell$16185[0]
1 1
.names common.pb.rx_buf_rd_data[1] $auto$memory_bram.cc:926:replace_cell$16185[1]
1 1
.names common.pb.rx_buf_rd_data[2] $auto$memory_bram.cc:926:replace_cell$16185[2]
1 1
.names common.pb.rx_buf_rd_data[3] $auto$memory_bram.cc:926:replace_cell$16185[3]
1 1
.names common.pb.rx_buf_rd_data[4] $auto$memory_bram.cc:926:replace_cell$16185[4]
1 1
.names common.pb.rx_buf_rd_data[5] $auto$memory_bram.cc:926:replace_cell$16185[5]
1 1
.names common.pb.rx_buf_rd_data[6] $auto$memory_bram.cc:926:replace_cell$16185[6]
1 1
.names common.pb.rx_buf_rd_data[7] $auto$memory_bram.cc:926:replace_cell$16185[7]
1 1
.names common.pb.rx_buf_rd_data[8] $auto$memory_bram.cc:926:replace_cell$16185[8]
1 1
.names $abc$44715$auto$simplemap.cc:309:simplemap_lut$25661[1] $auto$wreduce.cc:455:run$15906[1]
1 1
.names common.pb.tx_buf.rd_data1[0] $techmap16191\common.pb.tx_buf.mem.0.0.0.A1DATA_16[0]
1 1
.names common.pb.tx_buf.rd_data1[1] $techmap16191\common.pb.tx_buf.mem.0.0.0.A1DATA_16[2]
1 1
.names common.pb.tx_buf.rd_data1[2] $techmap16191\common.pb.tx_buf.mem.0.0.0.A1DATA_16[4]
1 1
.names common.pb.tx_buf.rd_data1[3] $techmap16191\common.pb.tx_buf.mem.0.0.0.A1DATA_16[6]
1 1
.names common.pb.tx_buf.rd_data1[4] $techmap16191\common.pb.tx_buf.mem.0.0.0.A1DATA_16[8]
1 1
.names common.pb.tx_buf.rd_data1[5] $techmap16191\common.pb.tx_buf.mem.0.0.0.A1DATA_16[10]
1 1
.names common.pb.tx_buf.rd_data1[6] $techmap16191\common.pb.tx_buf.mem.0.0.0.A1DATA_16[12]
1 1
.names common.pb.tx_buf.rd_data1[7] $techmap16191\common.pb.tx_buf.mem.0.0.0.A1DATA_16[14]
1 1
.names $abc$44715$auto$simplemap.cc:309:simplemap_lut$25737[1] $techmap\common.pb.$0\rx_buf_rd_addr[7:0][1]
1 1
.names common.pb.spirx_ctrl_data[0] $techmap\common.pb.$0\tsyn_clks[23:0][0]
1 1
.names common.pb.spirx_ctrl_data[1] $techmap\common.pb.$0\tsyn_clks[23:0][1]
1 1
.names common.pb.spirx_ctrl_data[2] $techmap\common.pb.$0\tsyn_clks[23:0][2]
1 1
.names common.pb.spirx_ctrl_data[3] $techmap\common.pb.$0\tsyn_clks[23:0][3]
1 1
.names common.pb.spirx_ctrl_data[4] $techmap\common.pb.$0\tsyn_clks[23:0][4]
1 1
.names $abc$44715$auto$simplemap.cc:309:simplemap_lut$26877[0] $techmap\common.pb.$0\tsyn_clks[23:0][5]
1 1
.names common.led_blink.led LED
1 1
.names common.pb.uart.tx_mod.tx_active PIN_16
1 1
.names common.pb.spirx_lencalc.error PIN_18
1 1
.names common.pb.rx_buf_wr PIN_19
1 1
.names $false USBPU
1 1
.names common.led_blink.clk common.clk
1 1
.names common.led_blink.led common.led
1 1
.names common.pb.n_reset common.led_blink.n_reset
1 1
.names common.led_blink.led common.led_w
1 1
.names common.pb.spi.miso_r common.miso
1 1
.names common.pb.n_reset common.n_reset
1 1
.names common.led_blink.clk common.pb.clk
1 1
.names common.pb.spi.miso_r common.pb.miso
1 1
.names PIN_11 common.pb.mosi
1 1
.names PIN_14 common.pb.rx
1 1
.names common.pb.uart.rx_mod.rx_active common.pb.rx_active
1 1
.names common.pb.rx_buf_wr_addr[0] common.pb.rx_buf.addr0[0]
1 1
.names common.pb.rx_buf_wr_addr[1] common.pb.rx_buf.addr0[1]
1 1
.names common.pb.rx_buf_wr_addr[2] common.pb.rx_buf.addr0[2]
1 1
.names common.pb.rx_buf_wr_addr[3] common.pb.rx_buf.addr0[3]
1 1
.names common.pb.rx_buf_wr_addr[4] common.pb.rx_buf.addr0[4]
1 1
.names common.pb.rx_buf_wr_addr[5] common.pb.rx_buf.addr0[5]
1 1
.names common.pb.rx_buf_wr_addr[6] common.pb.rx_buf.addr0[6]
1 1
.names common.pb.rx_buf_wr_addr[7] common.pb.rx_buf.addr0[7]
1 1
.names common.pb.rx_buf_rd_addr[0] common.pb.rx_buf.addr1[0]
1 1
.names common.pb.rx_buf_rd_addr[1] common.pb.rx_buf.addr1[1]
1 1
.names common.pb.rx_buf_rd_addr[2] common.pb.rx_buf.addr1[2]
1 1
.names common.pb.rx_buf_rd_addr[3] common.pb.rx_buf.addr1[3]
1 1
.names common.pb.rx_buf_rd_addr[4] common.pb.rx_buf.addr1[4]
1 1
.names common.pb.rx_buf_rd_addr[5] common.pb.rx_buf.addr1[5]
1 1
.names common.pb.rx_buf_rd_addr[6] common.pb.rx_buf.addr1[6]
1 1
.names common.pb.rx_buf_rd_addr[7] common.pb.rx_buf.addr1[7]
1 1
.names common.led_blink.clk common.pb.rx_buf.clk
1 1
.names $false common.pb.rx_buf.i[0]
1 1
.names $false common.pb.rx_buf.i[1]
1 1
.names $false common.pb.rx_buf.i[2]
1 1
.names $false common.pb.rx_buf.i[3]
1 1
.names $false common.pb.rx_buf.i[4]
1 1
.names $false common.pb.rx_buf.i[5]
1 1
.names $false common.pb.rx_buf.i[6]
1 1
.names $false common.pb.rx_buf.i[7]
1 1
.names $true common.pb.rx_buf.i[8]
1 1
.names $false common.pb.rx_buf.i[9]
1 1
.names $false common.pb.rx_buf.i[10]
1 1
.names $false common.pb.rx_buf.i[11]
1 1
.names $false common.pb.rx_buf.i[12]
1 1
.names $false common.pb.rx_buf.i[13]
1 1
.names $false common.pb.rx_buf.i[14]
1 1
.names $false common.pb.rx_buf.i[15]
1 1
.names $false common.pb.rx_buf.i[16]
1 1
.names $false common.pb.rx_buf.i[17]
1 1
.names $false common.pb.rx_buf.i[18]
1 1
.names $false common.pb.rx_buf.i[19]
1 1
.names $false common.pb.rx_buf.i[20]
1 1
.names $false common.pb.rx_buf.i[21]
1 1
.names $false common.pb.rx_buf.i[22]
1 1
.names $false common.pb.rx_buf.i[23]
1 1
.names $false common.pb.rx_buf.i[24]
1 1
.names $false common.pb.rx_buf.i[25]
1 1
.names $false common.pb.rx_buf.i[26]
1 1
.names $false common.pb.rx_buf.i[27]
1 1
.names $false common.pb.rx_buf.i[28]
1 1
.names $false common.pb.rx_buf.i[29]
1 1
.names $false common.pb.rx_buf.i[30]
1 1
.names $false common.pb.rx_buf.i[31]
1 1
.names common.pb.rx_buf_rd_data[0] common.pb.rx_buf.rd_data1[0]
1 1
.names common.pb.rx_buf_rd_data[1] common.pb.rx_buf.rd_data1[1]
1 1
.names common.pb.rx_buf_rd_data[2] common.pb.rx_buf.rd_data1[2]
1 1
.names common.pb.rx_buf_wr common.pb.rx_buf.wr0
1 1
.names common.pb.rx_buf_wr_data[0] common.pb.rx_buf.wr_data0[0]
1 1
.names common.pb.rx_buf_wr_data[1] common.pb.rx_buf.wr_data0[1]
1 1
.names common.pb.rx_buf_wr_data[2] common.pb.rx_buf.wr_data0[2]
1 1
.names common.pb.rx_buf_wr_data[3] common.pb.rx_buf.wr_data0[3]
1 1
.names common.pb.rx_buf_wr_data[4] common.pb.rx_buf.wr_data0[4]
1 1
.names common.pb.rx_buf_wr_data[5] common.pb.rx_buf.wr_data0[5]
1 1
.names common.pb.rx_buf_wr_data[6] common.pb.rx_buf.wr_data0[6]
1 1
.names common.pb.rx_buf_wr_data[7] common.pb.rx_buf.wr_data0[7]
1 1
.names common.pb.rx_buf_wr_data[8] common.pb.rx_buf.wr_data0[8]
1 1
.names PIN_17 common.pb.rx_error
1 1
.names common.pb.rx_buf_wr common.pb.rx_irq_edge
1 1
.names PIN_20 common.pb.rx_irq_level
1 1
.names PIN_12 common.pb.sck
1 1
.names common.led_blink.clk common.pb.spi.clk
1 1
.names common.pb.spi.miso_r common.pb.spi.miso
1 1
.names PIN_11 common.pb.spi.mosi
1 1
.names common.pb.spi.rx_data_r[0] common.pb.spi.rx_data[0]
1 1
.names common.pb.spi.rx_data_r[1] common.pb.spi.rx_data[1]
1 1
.names common.pb.spi.rx_data_r[2] common.pb.spi.rx_data[2]
1 1
.names common.pb.spi.rx_data_r[3] common.pb.spi.rx_data[3]
1 1
.names common.pb.spi.rx_data_r[4] common.pb.spi.rx_data[4]
1 1
.names common.pb.spi.rx_data_r[5] common.pb.spi.rx_data[5]
1 1
.names common.pb.spi.rx_data_r[6] common.pb.spi.rx_data[6]
1 1
.names common.pb.spi.rx_data_r[7] common.pb.spi.rx_data[7]
1 1
.names common.pb.spi.rx_irq_r common.pb.spi.rx_irq
1 1
.names PIN_12 common.pb.spi.sck
1 1
.names PIN_13 common.pb.spi.ss
1 1
.names common.led_blink.clk common.pb.spi.sync_mosi.clk
1 1
.names PIN_11 common.pb.spi.sync_mosi.in
1 1
.names common.pb.spi.mosi_s common.pb.spi.sync_mosi.out
1 1
.names common.pb.spi.mosi_s common.pb.spi.sync_mosi.shiftreg[1]
1 1
.names $undef common.pb.spi.sync_mosi.shiftreg[2]
1 1
.names common.led_blink.clk common.pb.spi.sync_sck.clk
1 1
.names PIN_12 common.pb.spi.sync_sck.in
1 1
.names common.pb.spi.sync_sck.out common.pb.spi.sync_sck.shiftreg[1]
1 1
.names common.led_blink.clk common.pb.spi.sync_ss.clk
1 1
.names PIN_13 common.pb.spi.sync_ss.in
1 1
.names common.pb.spi.ss_s common.pb.spi.sync_ss.out
1 1
.names common.pb.spi.ss_s common.pb.spi.sync_ss.shiftreg[1]
1 1
.names $undef common.pb.spi.sync_ss.shiftreg[2]
1 1
.names common.pb.spi_tx_data[0] common.pb.spi.tx_data[0]
1 1
.names common.pb.spi_tx_data[1] common.pb.spi.tx_data[1]
1 1
.names common.pb.spi_tx_data[2] common.pb.spi.tx_data[2]
1 1
.names common.pb.spi_tx_data[3] common.pb.spi.tx_data[3]
1 1
.names common.pb.spi_tx_data[4] common.pb.spi.tx_data[4]
1 1
.names common.pb.spi_tx_data[5] common.pb.spi.tx_data[5]
1 1
.names common.pb.spi_tx_data[6] common.pb.spi.tx_data[6]
1 1
.names common.pb.spi_tx_data[7] common.pb.spi.tx_data[7]
1 1
.names common.pb.spi.rx_data_r[0] common.pb.spi_rx_data[0]
1 1
.names common.pb.spi.rx_data_r[1] common.pb.spi_rx_data[1]
1 1
.names common.pb.spi.rx_data_r[2] common.pb.spi_rx_data[2]
1 1
.names common.pb.spi.rx_data_r[3] common.pb.spi_rx_data[3]
1 1
.names common.pb.spi.rx_data_r[4] common.pb.spi_rx_data[4]
1 1
.names common.pb.spi.rx_data_r[5] common.pb.spi_rx_data[5]
1 1
.names common.pb.spi.rx_data_r[6] common.pb.spi_rx_data[6]
1 1
.names common.pb.spi.rx_data_r[7] common.pb.spi_rx_data[7]
1 1
.names common.pb.spi.rx_irq_r common.pb.spi_rx_irq
1 1
.names common.pb.spi.rx_irq_r common.pb.spi_tx_irq
1 1
.names $false common.pb.spirx_ctrl_data[24]
1 1
.names $false common.pb.spirx_ctrl_data[25]
1 1
.names $false common.pb.spirx_ctrl_data[26]
1 1
.names $false common.pb.spirx_ctrl_data[27]
1 1
.names $false common.pb.spirx_ctrl_data[28]
1 1
.names $false common.pb.spirx_ctrl_data[29]
1 1
.names $false common.pb.spirx_ctrl_data[30]
1 1
.names $false common.pb.spirx_ctrl_data[31]
1 1
.names common.led_blink.clk common.pb.spirx_lencalc.clk
1 1
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1 1
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1 1
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.names PIN_14 common.pb.uart.sync_rx.in
1 1
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1 1
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1 1
.names $undef common.pb.uart.sync_rx.shiftreg[2]
1 1
.names PIN_15 common.pb.uart.tx
1 1
.names common.pb.uart.tx_mod.tx_active common.pb.uart.tx_active
1 1
.names common.pb.uart.tx_mod.tx_active common.pb.uart.tx_active_w
1 1
.names common.pb.uart_tx_data[0] common.pb.uart.tx_data[0]
1 1
.names common.pb.uart_tx_data[1] common.pb.uart.tx_data[1]
1 1
.names common.pb.uart_tx_data[2] common.pb.uart.tx_data[2]
1 1
.names common.pb.uart_tx_data[3] common.pb.uart.tx_data[3]
1 1
.names common.pb.uart_tx_data[4] common.pb.uart.tx_data[4]
1 1
.names common.pb.uart_tx_data[5] common.pb.uart.tx_data[5]
1 1
.names common.pb.uart_tx_data[6] common.pb.uart.tx_data[6]
1 1
.names common.pb.uart_tx_data[7] common.pb.uart.tx_data[7]
1 1
.names common.pb.uart.tx_mod.tx_irq common.pb.uart.tx_irq
1 1
.names common.led_blink.clk common.pb.uart.tx_mod.clk
1 1
.names common.pb.uart_clks_per_sym[0] common.pb.uart.tx_mod.clks_per_sym[0]
1 1
.names common.pb.uart_clks_per_sym[1] common.pb.uart.tx_mod.clks_per_sym[1]
1 1
.names common.pb.uart_clks_per_sym[2] common.pb.uart.tx_mod.clks_per_sym[2]
1 1
.names common.pb.uart_clks_per_sym[3] common.pb.uart.tx_mod.clks_per_sym[3]
1 1
.names common.pb.uart_clks_per_sym[4] common.pb.uart.tx_mod.clks_per_sym[4]
1 1
.names common.pb.uart_clks_per_sym[5] common.pb.uart.tx_mod.clks_per_sym[5]
1 1
.names common.pb.uart_clks_per_sym[6] common.pb.uart.tx_mod.clks_per_sym[6]
1 1
.names common.pb.uart_clks_per_sym[7] common.pb.uart.tx_mod.clks_per_sym[7]
1 1
.names common.pb.uart_clks_per_sym[8] common.pb.uart.tx_mod.clks_per_sym[8]
1 1
.names common.pb.uart_clks_per_sym[9] common.pb.uart.tx_mod.clks_per_sym[9]
1 1
.names common.pb.uart_clks_per_sym[10] common.pb.uart.tx_mod.clks_per_sym[10]
1 1
.names common.pb.uart_clks_per_sym[11] common.pb.uart.tx_mod.clks_per_sym[11]
1 1
.names common.pb.uart_clks_per_sym[12] common.pb.uart.tx_mod.clks_per_sym[12]
1 1
.names common.pb.uart_clks_per_sym[13] common.pb.uart.tx_mod.clks_per_sym[13]
1 1
.names common.pb.uart_clks_per_sym[14] common.pb.uart.tx_mod.clks_per_sym[14]
1 1
.names common.pb.uart_clks_per_sym[15] common.pb.uart.tx_mod.clks_per_sym[15]
1 1
.names common.pb.uart_clks_per_sym[16] common.pb.uart.tx_mod.clks_per_sym[16]
1 1
.names common.pb.uart_clks_per_sym[17] common.pb.uart.tx_mod.clks_per_sym[17]
1 1
.names common.pb.uart_clks_per_sym[18] common.pb.uart.tx_mod.clks_per_sym[18]
1 1
.names common.pb.uart_clks_per_sym[19] common.pb.uart.tx_mod.clks_per_sym[19]
1 1
.names common.pb.uart_clks_per_sym[20] common.pb.uart.tx_mod.clks_per_sym[20]
1 1
.names common.pb.uart_clks_per_sym[21] common.pb.uart.tx_mod.clks_per_sym[21]
1 1
.names common.pb.uart_clks_per_sym[22] common.pb.uart.tx_mod.clks_per_sym[22]
1 1
.names common.pb.uart_clks_per_sym[23] common.pb.uart.tx_mod.clks_per_sym[23]
1 1
.names common.led_blink.clk common.pb.uart.tx_mod.symclk.clk
1 1
.names common.pb.uart_clks_per_sym[0] common.pb.uart.tx_mod.symclk.clks_per_sym[0]
1 1
.names common.pb.uart_clks_per_sym[1] common.pb.uart.tx_mod.symclk.clks_per_sym[1]
1 1
.names common.pb.uart_clks_per_sym[2] common.pb.uart.tx_mod.symclk.clks_per_sym[2]
1 1
.names common.pb.uart_clks_per_sym[3] common.pb.uart.tx_mod.symclk.clks_per_sym[3]
1 1
.names common.pb.uart_clks_per_sym[4] common.pb.uart.tx_mod.symclk.clks_per_sym[4]
1 1
.names common.pb.uart_clks_per_sym[5] common.pb.uart.tx_mod.symclk.clks_per_sym[5]
1 1
.names common.pb.uart_clks_per_sym[6] common.pb.uart.tx_mod.symclk.clks_per_sym[6]
1 1
.names common.pb.uart_clks_per_sym[7] common.pb.uart.tx_mod.symclk.clks_per_sym[7]
1 1
.names common.pb.uart_clks_per_sym[8] common.pb.uart.tx_mod.symclk.clks_per_sym[8]
1 1
.names common.pb.uart_clks_per_sym[9] common.pb.uart.tx_mod.symclk.clks_per_sym[9]
1 1
.names common.pb.uart_clks_per_sym[10] common.pb.uart.tx_mod.symclk.clks_per_sym[10]
1 1
.names common.pb.uart_clks_per_sym[11] common.pb.uart.tx_mod.symclk.clks_per_sym[11]
1 1
.names common.pb.uart_clks_per_sym[12] common.pb.uart.tx_mod.symclk.clks_per_sym[12]
1 1
.names common.pb.uart_clks_per_sym[13] common.pb.uart.tx_mod.symclk.clks_per_sym[13]
1 1
.names common.pb.uart_clks_per_sym[14] common.pb.uart.tx_mod.symclk.clks_per_sym[14]
1 1
.names common.pb.uart_clks_per_sym[15] common.pb.uart.tx_mod.symclk.clks_per_sym[15]
1 1
.names common.pb.uart_clks_per_sym[16] common.pb.uart.tx_mod.symclk.clks_per_sym[16]
1 1
.names common.pb.uart_clks_per_sym[17] common.pb.uart.tx_mod.symclk.clks_per_sym[17]
1 1
.names common.pb.uart_clks_per_sym[18] common.pb.uart.tx_mod.symclk.clks_per_sym[18]
1 1
.names common.pb.uart_clks_per_sym[19] common.pb.uart.tx_mod.symclk.clks_per_sym[19]
1 1
.names common.pb.uart_clks_per_sym[20] common.pb.uart.tx_mod.symclk.clks_per_sym[20]
1 1
.names common.pb.uart_clks_per_sym[21] common.pb.uart.tx_mod.symclk.clks_per_sym[21]
1 1
.names common.pb.uart_clks_per_sym[22] common.pb.uart.tx_mod.symclk.clks_per_sym[22]
1 1
.names common.pb.uart_clks_per_sym[23] common.pb.uart.tx_mod.symclk.clks_per_sym[23]
1 1
.names common.pb.uart.tx_mod.symclk.clks_per_sym_limited[1] common.pb.uart.tx_mod.symclk.clks_per_sym_half[0]
1 1
.names common.pb.uart.tx_mod.symclk.clks_per_sym_limited[2] common.pb.uart.tx_mod.symclk.clks_per_sym_half[1]
1 1
.names common.pb.uart.tx_mod.symclk.clks_per_sym_limited[3] common.pb.uart.tx_mod.symclk.clks_per_sym_half[2]
1 1
.names common.pb.uart.tx_mod.symclk.clks_per_sym_limited[4] common.pb.uart.tx_mod.symclk.clks_per_sym_half[3]
1 1
.names common.pb.uart.tx_mod.symclk.clks_per_sym_limited[5] common.pb.uart.tx_mod.symclk.clks_per_sym_half[4]
1 1
.names common.pb.uart.tx_mod.symclk.clks_per_sym_limited[6] common.pb.uart.tx_mod.symclk.clks_per_sym_half[5]
1 1
.names common.pb.uart.tx_mod.symclk.clks_per_sym_limited[7] common.pb.uart.tx_mod.symclk.clks_per_sym_half[6]
1 1
.names common.pb.uart.tx_mod.symclk.clks_per_sym_limited[8] common.pb.uart.tx_mod.symclk.clks_per_sym_half[7]
1 1
.names common.pb.uart.tx_mod.symclk.clks_per_sym_limited[9] common.pb.uart.tx_mod.symclk.clks_per_sym_half[8]
1 1
.names common.pb.uart.tx_mod.symclk.clks_per_sym_limited[10] common.pb.uart.tx_mod.symclk.clks_per_sym_half[9]
1 1
.names common.pb.uart.tx_mod.symclk.clks_per_sym_limited[11] common.pb.uart.tx_mod.symclk.clks_per_sym_half[10]
1 1
.names common.pb.uart.tx_mod.symclk.clks_per_sym_limited[12] common.pb.uart.tx_mod.symclk.clks_per_sym_half[11]
1 1
.names common.pb.uart.tx_mod.symclk.clks_per_sym_limited[13] common.pb.uart.tx_mod.symclk.clks_per_sym_half[12]
1 1
.names common.pb.uart.tx_mod.symclk.clks_per_sym_limited[14] common.pb.uart.tx_mod.symclk.clks_per_sym_half[13]
1 1
.names common.pb.uart.tx_mod.symclk.clks_per_sym_limited[15] common.pb.uart.tx_mod.symclk.clks_per_sym_half[14]
1 1
.names common.pb.uart.tx_mod.symclk.clks_per_sym_limited[16] common.pb.uart.tx_mod.symclk.clks_per_sym_half[15]
1 1
.names common.pb.uart.tx_mod.symclk.clks_per_sym_limited[17] common.pb.uart.tx_mod.symclk.clks_per_sym_half[16]
1 1
.names common.pb.uart.tx_mod.symclk.clks_per_sym_limited[18] common.pb.uart.tx_mod.symclk.clks_per_sym_half[17]
1 1
.names common.pb.uart.tx_mod.symclk.clks_per_sym_limited[19] common.pb.uart.tx_mod.symclk.clks_per_sym_half[18]
1 1
.names common.pb.uart.tx_mod.symclk.clks_per_sym_limited[20] common.pb.uart.tx_mod.symclk.clks_per_sym_half[19]
1 1
.names common.pb.uart.tx_mod.symclk.clks_per_sym_limited[21] common.pb.uart.tx_mod.symclk.clks_per_sym_half[20]
1 1
.names common.pb.uart.tx_mod.symclk.clks_per_sym_limited[22] common.pb.uart.tx_mod.symclk.clks_per_sym_half[21]
1 1
.names common.pb.uart.tx_mod.symclk.clks_per_sym_limited[23] common.pb.uart.tx_mod.symclk.clks_per_sym_half[22]
1 1
.names $false common.pb.uart.tx_mod.symclk.clks_per_sym_half[23]
1 1
.names common.pb.uart.rx_mod.symclk.clks_per_sym_limited common.pb.uart.tx_mod.symclk.clks_per_sym_limited[0]
1 1
.names common.pb.uart.tx_mod.symclk_n_reset common.pb.uart.tx_mod.symclk.n_reset
1 1
.names $false common.pb.uart.tx_mod.symclk.sample
1 1
.names common.pb.uart.tx_mod.symclk.symend common.pb.uart.tx_mod.symclk_end
1 1
.names $false common.pb.uart.tx_mod.symclk_sample
1 1
.names common.pb.uart.tx_mod.symclk.setup common.pb.uart.tx_mod.symclk_setup
1 1
.names PIN_15 common.pb.uart.tx_mod.tx
1 1
.names common.pb.uart.tx_data_r[0] common.pb.uart.tx_mod.tx_data[0]
1 1
.names common.pb.uart.tx_data_r[1] common.pb.uart.tx_mod.tx_data[1]
1 1
.names common.pb.uart.tx_data_r[2] common.pb.uart.tx_mod.tx_data[2]
1 1
.names common.pb.uart.tx_data_r[3] common.pb.uart.tx_mod.tx_data[3]
1 1
.names common.pb.uart.tx_data_r[4] common.pb.uart.tx_mod.tx_data[4]
1 1
.names common.pb.uart.tx_data_r[5] common.pb.uart.tx_mod.tx_data[5]
1 1
.names common.pb.uart.tx_data_r[6] common.pb.uart.tx_mod.tx_data[6]
1 1
.names common.pb.uart.tx_data_r[7] common.pb.uart.tx_mod.tx_data[7]
1 1
.names PIN_15 common.pb.uart.tx_mod.tx_r
1 1
.names common.pb.uart.tx_trigger_req common.pb.uart.tx_mod.tx_trigger
1 1
.names common.pb.uart.tx_trigger_req common.pb.uart.tx_pending
1 1
.names common.pb.uart_tx_trigger common.pb.uart.tx_trigger
1 1
.names common.pb.uart.rx_mod.rx_active common.pb.uart_rx_active
1 1
.names common.pb.uart.rx_mod.rx_data[0] common.pb.uart_rx_data[0]
1 1
.names common.pb.uart.rx_mod.rx_data[1] common.pb.uart_rx_data[1]
1 1
.names common.pb.uart.rx_mod.rx_data[2] common.pb.uart_rx_data[2]
1 1
.names common.pb.uart.rx_mod.rx_data[3] common.pb.uart_rx_data[3]
1 1
.names common.pb.uart.rx_mod.rx_data[4] common.pb.uart_rx_data[4]
1 1
.names common.pb.uart.rx_mod.rx_data[5] common.pb.uart_rx_data[5]
1 1
.names common.pb.uart.rx_mod.rx_data[6] common.pb.uart_rx_data[6]
1 1
.names common.pb.uart.rx_mod.rx_data[7] common.pb.uart_rx_data[7]
1 1
.names common.pb.uart.rx_mod.rx_frame_error common.pb.uart_rx_frame_error
1 1
.names common.pb.uart.rx_mod.rx_irq common.pb.uart_rx_irq
1 1
.names common.pb.uart.rx_mod.rx_parity_ok common.pb.uart_rx_parity_ok
1 1
.names common.pb.uart.tx_mod.tx_active common.pb.uart_tx_active
1 1
.names common.pb.uart.tx_mod.tx_irq common.pb.uart_tx_irq
1 1
.names common.pb.uart.tx_trigger_req common.pb.uart_tx_pending
1 1
.names PIN_14 common.pb_rx
1 1
.names PIN_17 common.pb_rx_error
1 1
.names common.pb.rx_buf_wr common.pb_rx_irq_edge
1 1
.names PIN_20 common.pb_rx_irq_level
1 1
.names PIN_15 common.pb_tx
1 1
.names common.pb.uart.tx_mod.tx_active common.pb_tx_active
1 1
.names common.pb.spirx_lencalc.error common.pb_tx_error
1 1
.names common.pb.uart.rx_mod.rx_active common.rx_active
1 1
.names PIN_17 common.rx_error
1 1
.names common.pb.rx_buf_wr common.rx_irq_edge
1 1
.names PIN_20 common.rx_irq_level
1 1
.names PIN_10 common.spi_miso
1 1
.names PIN_11 common.spi_mosi
1 1
.names PIN_12 common.spi_sck
1 1
.names PIN_13 common.spi_ss
1 1
.names PIN_15 common.tx
1 1
.names common.pb.uart.tx_mod.tx_active common.tx_active
1 1
.names common.pb.spirx_lencalc.error common.tx_error
1 1
.names common.pb.n_reset n_reset
1 1
.names CLK pll.clock_in
1 1
.names common.led_blink.clk pll.clock_out
1 1
.names common.led_blink.clk pll_clk_out
1 1
.names pll.locked pll_locked
1 1
.end
