
 /----------------------------------------------------------------------------\
 |                                                                            |
 |  yosys -- Yosys Open SYnthesis Suite                                       |
 |                                                                            |
 |  Copyright (C) 2012 - 2018  Clifford Wolf <clifford@clifford.at>           |
 |                                                                            |
 |  Permission to use, copy, modify, and/or distribute this software for any  |
 |  purpose with or without fee is hereby granted, provided that the above    |
 |  copyright notice and this permission notice appear in all copies.         |
 |                                                                            |
 |  THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES  |
 |  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF          |
 |  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR   |
 |  ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES    |
 |  WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN     |
 |  ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF   |
 |  OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.            |
 |                                                                            |
 \----------------------------------------------------------------------------/

 Yosys 0.8+615 (git sha1 6538671c, clang 7.0.1-8 -march=native -mtune=native -O2 -fpermissive -fPIC -Os)


-- Running command `read_verilog -DTARGET_TINYFPGA_BX=1 -DCLK_HZ=16000000 -DPLL_HZ=24000000  main.v' --

1. Executing Verilog-2005 frontend: main.v
Parsing Verilog input from `main.v' to AST representation.
Generating RTLIL representation for module `\sync_signal'.
Generating RTLIL representation for module `\edge_detect'.
Generating RTLIL representation for module `\uart_symclk'.
Generating RTLIL representation for module `\uart_rx'.
Generating RTLIL representation for module `\uart_tx'.
Generating RTLIL representation for module `\uart_full_duplex'.
Generating RTLIL representation for module `\uart_arbiter'.
Generating RTLIL representation for module `\uart_half_duplex'.
Generating RTLIL representation for module `\spi_slave'.
Generating RTLIL representation for module `\block_ram'.
Generating RTLIL representation for module `\profibus_telegram_length'.
Generating RTLIL representation for module `\profibus_phy'.
Generating RTLIL representation for module `\led_blink'.
Generating RTLIL representation for module `\common_main_module'.
Generating RTLIL representation for module `\pll_module'.
Generating RTLIL representation for module `\top_module'.
Successfully finished Verilog frontend.

-- Running command `synth_ice40 -top top_module -json tinyfpga_bx_pyprofibusphy.json -blif tinyfpga_bx_pyprofibusphy.blif' --

2. Executing SYNTH_ICE40 pass.

2.1. Executing Verilog-2005 frontend: /home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_sim.v
Parsing Verilog input from `/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_sim.v' to AST representation.
Generating RTLIL representation for module `\SB_IO'.
Generating RTLIL representation for module `\SB_GB_IO'.
Generating RTLIL representation for module `\SB_GB'.
Generating RTLIL representation for module `\SB_LUT4'.
Generating RTLIL representation for module `\SB_CARRY'.
Generating RTLIL representation for module `$__ICE40_FULL_ADDER'.
Generating RTLIL representation for module `\SB_DFF'.
Generating RTLIL representation for module `\SB_DFFE'.
Generating RTLIL representation for module `\SB_DFFSR'.
Generating RTLIL representation for module `\SB_DFFR'.
Generating RTLIL representation for module `\SB_DFFSS'.
Generating RTLIL representation for module `\SB_DFFS'.
Generating RTLIL representation for module `\SB_DFFESR'.
Generating RTLIL representation for module `\SB_DFFER'.
Generating RTLIL representation for module `\SB_DFFESS'.
Generating RTLIL representation for module `\SB_DFFES'.
Generating RTLIL representation for module `\SB_DFFN'.
Generating RTLIL representation for module `\SB_DFFNE'.
Generating RTLIL representation for module `\SB_DFFNSR'.
Generating RTLIL representation for module `\SB_DFFNR'.
Generating RTLIL representation for module `\SB_DFFNSS'.
Generating RTLIL representation for module `\SB_DFFNS'.
Generating RTLIL representation for module `\SB_DFFNESR'.
Generating RTLIL representation for module `\SB_DFFNER'.
Generating RTLIL representation for module `\SB_DFFNESS'.
Generating RTLIL representation for module `\SB_DFFNES'.
Generating RTLIL representation for module `\SB_RAM40_4K'.
Generating RTLIL representation for module `\SB_RAM40_4KNR'.
Generating RTLIL representation for module `\SB_RAM40_4KNW'.
Generating RTLIL representation for module `\SB_RAM40_4KNRNW'.
Generating RTLIL representation for module `\ICESTORM_LC'.
Generating RTLIL representation for module `\SB_PLL40_CORE'.
Generating RTLIL representation for module `\SB_PLL40_PAD'.
Generating RTLIL representation for module `\SB_PLL40_2_PAD'.
Generating RTLIL representation for module `\SB_PLL40_2F_CORE'.
Generating RTLIL representation for module `\SB_PLL40_2F_PAD'.
Generating RTLIL representation for module `\SB_WARMBOOT'.
Generating RTLIL representation for module `\SB_SPRAM256KA'.
Generating RTLIL representation for module `\SB_HFOSC'.
Generating RTLIL representation for module `\SB_LFOSC'.
Generating RTLIL representation for module `\SB_RGBA_DRV'.
Generating RTLIL representation for module `\SB_LED_DRV_CUR'.
Generating RTLIL representation for module `\SB_RGB_DRV'.
Generating RTLIL representation for module `\SB_I2C'.
Generating RTLIL representation for module `\SB_SPI'.
Generating RTLIL representation for module `\SB_LEDDA_IP'.
Generating RTLIL representation for module `\SB_FILTER_50NS'.
Generating RTLIL representation for module `\SB_IO_I3C'.
Generating RTLIL representation for module `\SB_IO_OD'.
Generating RTLIL representation for module `\SB_MAC16'.
Successfully finished Verilog frontend.

2.2. Executing HIERARCHY pass (managing design hierarchy).

2.2.1. Analyzing design hierarchy..
Top module:  \top_module
Used module:     \common_main_module
Used module:         \led_blink
Used module:         \profibus_phy
Used module:             \profibus_telegram_length
Used module:             \spi_slave
Used module:                 \sync_signal
Used module:             \uart_half_duplex
Used module:                 \uart_tx
Used module:                     \uart_symclk
Used module:                 \uart_rx
Used module:                     \edge_detect
Used module:                 \uart_arbiter
Used module:             \block_ram
Used module:     \pll_module

2.2.2. Executing AST frontend in derive mode using pre-parsed AST for module `\uart_tx'.
Parameter \DATABITS = 8
Parameter \PARITY_EVEN = 0
Parameter \STOP = 2
Parameter \ACTIVE_LOW = 0
Generating RTLIL representation for module `$paramod\uart_tx\DATABITS=8\PARITY_EVEN=0\STOP=2\ACTIVE_LOW=0'.

2.2.3. Executing AST frontend in derive mode using pre-parsed AST for module `\uart_rx'.
Parameter \DATABITS = 8
Parameter \PARITY_EVEN = 0
Parameter \ACTIVE_LOW = 0
Generating RTLIL representation for module `$paramod\uart_rx\DATABITS=8\PARITY_EVEN=0\ACTIVE_LOW=0'.

2.2.4. Executing AST frontend in derive mode using pre-parsed AST for module `\uart_arbiter'.
Parameter \ACTIVE_LOW = 0
Generating RTLIL representation for module `$paramod\uart_arbiter\ACTIVE_LOW=0'.

2.2.5. Executing AST frontend in derive mode using pre-parsed AST for module `\spi_slave'.
Parameter \WORDSIZE = 8
Parameter \CPOL = 0
Parameter \CPHA = 0
Parameter \MSB_FIRST = 1
Generating RTLIL representation for module `$paramod\spi_slave\WORDSIZE=8\CPOL=0\CPHA=0\MSB_FIRST=1'.

2.2.6. Executing AST frontend in derive mode using pre-parsed AST for module `\uart_half_duplex'.
Parameter \DATABITS = 8
Parameter \PARITY_EVEN = 1
Parameter \STOP = 1
Parameter \ACTIVE_LOW = 0
Generating RTLIL representation for module `$paramod\uart_half_duplex\DATABITS=8\PARITY_EVEN=1\STOP=1\ACTIVE_LOW=0'.

2.2.7. Executing AST frontend in derive mode using pre-parsed AST for module `\block_ram'.
Parameter \ADDR_WIDTH = 8
Parameter \DATA_WIDTH = 9
Parameter \MEM_BYTES = 256
Generating RTLIL representation for module `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256'.

2.2.8. Executing AST frontend in derive mode using pre-parsed AST for module `\block_ram'.
Parameter \ADDR_WIDTH = 8
Parameter \DATA_WIDTH = 8
Parameter \MEM_BYTES = 256
Generating RTLIL representation for module `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256'.

2.2.9. Executing AST frontend in derive mode using pre-parsed AST for module `\led_blink'.
Parameter \BLINK_ON_CLKS = 0
Parameter \BLINK_OFF_CLKS = 0
Generating RTLIL representation for module `$paramod\led_blink\BLINK_ON_CLKS=0\BLINK_OFF_CLKS=0'.

2.2.10. Executing AST frontend in derive mode using pre-parsed AST for module `\common_main_module'.
Parameter \CLK_HZ = 24000000
Generating RTLIL representation for module `$paramod\common_main_module\CLK_HZ=24000000'.

2.2.11. Analyzing design hierarchy..
Top module:  \top_module
Used module:     $paramod\common_main_module\CLK_HZ=24000000
Used module:         \led_blink
Used module:         \profibus_phy
Used module:             \profibus_telegram_length
Used module:             $paramod\spi_slave\WORDSIZE=8\CPOL=0\CPHA=0\MSB_FIRST=1
Used module:                 \sync_signal
Used module:             $paramod\uart_half_duplex\DATABITS=8\PARITY_EVEN=1\STOP=1\ACTIVE_LOW=0
Used module:                 \uart_tx
Used module:                     \uart_symclk
Used module:                 \uart_rx
Used module:                     \edge_detect
Used module:                 \uart_arbiter
Used module:             $paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256
Used module:             $paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256
Used module:     \pll_module

2.2.12. Executing AST frontend in derive mode using pre-parsed AST for module `\uart_tx'.
Parameter \DATABITS = 8
Parameter \PARITY_EVEN = 1
Parameter \STOP = 1
Parameter \ACTIVE_LOW = 0
Generating RTLIL representation for module `$paramod\uart_tx\DATABITS=8\PARITY_EVEN=1\STOP=1\ACTIVE_LOW=0'.

2.2.13. Executing AST frontend in derive mode using pre-parsed AST for module `\uart_rx'.
Parameter \DATABITS = 8
Parameter \PARITY_EVEN = 1
Parameter \ACTIVE_LOW = 0
Generating RTLIL representation for module `$paramod\uart_rx\DATABITS=8\PARITY_EVEN=1\ACTIVE_LOW=0'.

2.2.14. Executing AST frontend in derive mode using pre-parsed AST for module `\uart_arbiter'.
Parameter \ACTIVE_LOW = 0
Found cached RTLIL representation for module `$paramod\uart_arbiter\ACTIVE_LOW=0'.

2.2.15. Executing AST frontend in derive mode using pre-parsed AST for module `\led_blink'.
Parameter \BLINK_ON_CLKS = 2400000
Parameter \BLINK_OFF_CLKS = 685714
Generating RTLIL representation for module `$paramod\led_blink\BLINK_ON_CLKS=2400000\BLINK_OFF_CLKS=685714'.

2.2.16. Analyzing design hierarchy..
Top module:  \top_module
Used module:     $paramod\common_main_module\CLK_HZ=24000000
Used module:         $paramod\led_blink\BLINK_ON_CLKS=2400000\BLINK_OFF_CLKS=685714
Used module:         \profibus_phy
Used module:             \profibus_telegram_length
Used module:             $paramod\spi_slave\WORDSIZE=8\CPOL=0\CPHA=0\MSB_FIRST=1
Used module:                 \sync_signal
Used module:             $paramod\uart_half_duplex\DATABITS=8\PARITY_EVEN=1\STOP=1\ACTIVE_LOW=0
Used module:                 $paramod\uart_tx\DATABITS=8\PARITY_EVEN=1\STOP=1\ACTIVE_LOW=0
Used module:                     \uart_symclk
Used module:                 $paramod\uart_rx\DATABITS=8\PARITY_EVEN=1\ACTIVE_LOW=0
Used module:                     \edge_detect
Used module:                 $paramod\uart_arbiter\ACTIVE_LOW=0
Used module:             $paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256
Used module:             $paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256
Used module:     \pll_module

2.2.17. Analyzing design hierarchy..
Top module:  \top_module
Used module:     $paramod\common_main_module\CLK_HZ=24000000
Used module:         $paramod\led_blink\BLINK_ON_CLKS=2400000\BLINK_OFF_CLKS=685714
Used module:         \profibus_phy
Used module:             \profibus_telegram_length
Used module:             $paramod\spi_slave\WORDSIZE=8\CPOL=0\CPHA=0\MSB_FIRST=1
Used module:                 \sync_signal
Used module:             $paramod\uart_half_duplex\DATABITS=8\PARITY_EVEN=1\STOP=1\ACTIVE_LOW=0
Used module:                 $paramod\uart_tx\DATABITS=8\PARITY_EVEN=1\STOP=1\ACTIVE_LOW=0
Used module:                     \uart_symclk
Used module:                 $paramod\uart_rx\DATABITS=8\PARITY_EVEN=1\ACTIVE_LOW=0
Used module:                     \edge_detect
Used module:                 $paramod\uart_arbiter\ACTIVE_LOW=0
Used module:             $paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256
Used module:             $paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256
Used module:     \pll_module
Removing unused module `$paramod\led_blink\BLINK_ON_CLKS=0\BLINK_OFF_CLKS=0'.
Removing unused module `$paramod\uart_rx\DATABITS=8\PARITY_EVEN=0\ACTIVE_LOW=0'.
Removing unused module `$paramod\uart_tx\DATABITS=8\PARITY_EVEN=0\STOP=2\ACTIVE_LOW=0'.
Removing unused module `\common_main_module'.
Removing unused module `\led_blink'.
Removing unused module `\block_ram'.
Removing unused module `\spi_slave'.
Removing unused module `\uart_half_duplex'.
Removing unused module `\uart_arbiter'.
Removing unused module `\uart_full_duplex'.
Removing unused module `\uart_tx'.
Removing unused module `\uart_rx'.
Removed 12 unused modules.

2.3. Executing PROC pass (convert processes to netlists).

2.3.1. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Found and cleaned up 4 empty switches in `$paramod\spi_slave\WORDSIZE=8\CPOL=0\CPHA=0\MSB_FIRST=1.$proc$spi_slave_mod.v:82$6479'.
Found and cleaned up 1 empty switch in `$paramod\uart_tx\DATABITS=8\PARITY_EVEN=1\STOP=1\ACTIVE_LOW=0.$proc$uart_mod.v:330$9102'.
Cleaned up 5 empty switches.

2.3.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees).
Marked 4 switch rules as full_case in process $proc$led_blink_mod.v:44$9246 in module $paramod\led_blink\BLINK_ON_CLKS=2400000\BLINK_OFF_CLKS=685714.
Marked 2 switch rules as full_case in process $proc$profibus_phy_mod.v:1046$6259 in module profibus_phy.
Marked 10 switch rules as full_case in process $proc$profibus_phy_mod.v:881$5661 in module profibus_phy.
Marked 14 switch rules as full_case in process $proc$profibus_phy_mod.v:604$5408 in module profibus_phy.
Marked 2 switch rules as full_case in process $proc$profibus_phy_mod.v:510$5397 in module profibus_phy.
Marked 3 switch rules as full_case in process $proc$profibus_phy_mod.v:476$5389 in module profibus_phy.
Marked 9 switch rules as full_case in process $proc$profibus_phy_mod.v:109$5333 in module profibus_telegram_length.
Marked 2 switch rules as full_case in process $proc$uart_mod.v:582$6492 in module $paramod\uart_half_duplex\DATABITS=8\PARITY_EVEN=1\STOP=1\ACTIVE_LOW=0.
Marked 3 switch rules as full_case in process $proc$spi_slave_mod.v:82$6479 in module $paramod\spi_slave\WORDSIZE=8\CPOL=0\CPHA=0\MSB_FIRST=1.
Marked 10 switch rules as full_case in process $proc$uart_mod.v:190$9177 in module $paramod\uart_rx\DATABITS=8\PARITY_EVEN=1\ACTIVE_LOW=0.
Marked 11 switch rules as full_case in process $proc$uart_mod.v:330$9102 in module $paramod\uart_tx\DATABITS=8\PARITY_EVEN=1\STOP=1\ACTIVE_LOW=0.
Marked 4 switch rules as full_case in process $proc$uart_mod.v:71$16 in module uart_symclk.
Removed a total of 0 dead cases.

2.3.3. Executing PROC_PRUNE pass (remove redundant assignments in processes).
Removed 7 redundant assignments.
Promoted 1231 assignments to connections.

2.3.4. Executing PROC_INIT pass (extract init attributes).
Found init rule in `$paramod\led_blink\BLINK_ON_CLKS=2400000\BLINK_OFF_CLKS=685714.$proc$led_blink_mod.v:38$9251'.
  Set init value: \led = 1'0
  Set init value: \led_on_count = 0
  Set init value: \led_off_count = 0
Found init rule in `\profibus_phy.$proc$profibus_phy_mod.v:1040$6287'.
  Set init value: \timer_idle_active = 1'0
  Set init value: \timer_idle = 24'000000000000000000000000
  Set init value: \timer_idle_saved = 24'111111111111111111111111
Found init rule in `\profibus_phy.$proc$profibus_phy_mod.v:869$6286'.
  Set init value: \spitx_ctrl_reply = 8'00000000
  Set init value: \spitx_ctrl_reply_data = 0
  Set init value: \spitx_ctrl_pending = 1'0
  Set init value: \spitx_ctrl_pending_ack = 1'0
  Set init value: \spitx_bytecount = 8'00000000
  Set init value: \spitx_len = 8'00000000
  Set init value: \spitx_ctrl_running = 1'0
  Set init value: \spitx_data_running = 1'0
  Set init value: \spitx_crc = 8'00000000
Found init rule in `\profibus_phy.$proc$profibus_phy_mod.v:577$6285'.
  Set init value: \spirx_state = 3'000
  Set init value: \spirx_len = 8'00000000
  Set init value: \spirx_len_valid = 1'0
  Set init value: \spirx_bytecount = 8'00000000
  Set init value: \spirx_ctrl = 8'00000000
  Set init value: \spirx_ctrl_data = 0
  Set init value: \spirx_crc = 8'00000000
  Set init value: \spirx_ctrl_crcerr = 2'00
  Set init value: \spirx_lencalc_n_reset = 1'0
  Set init value: \spirx_lencalc_byte = 8'00000000
  Set init value: \spirx_lencalc_new = 1'0
Found init rule in `\profibus_phy.$proc$profibus_phy_mod.v:472$6284'.
  Set init value: \tsyn_clks = 24'000000000000000000000000
Found init rule in `\profibus_phy.$proc$profibus_phy_mod.v:455$6283'.
  Set init value: \spi_tx_data = 8'00000000
Found init rule in `\profibus_phy.$proc$profibus_phy_mod.v:423$6282'.
  Set init value: \uart_tx_data = 8'00000000
  Set init value: \uart_tx_trigger = 1'0
  Set init value: \uart_clks_per_sym = 24'000000000000000000000000
Found init rule in `\profibus_phy.$proc$profibus_phy_mod.v:358$6281'.
  Set init value: \rx_buf_wr_addr = 8'00000000
  Set init value: \rx_buf_wr_data = 9'000000000
  Set init value: \rx_buf_wr = 1'0
  Set init value: \rx_buf_rd_addr = 8'00000000
  Set init value: \rx_buf_overflow = 2'00
Found init rule in `\profibus_phy.$proc$profibus_phy_mod.v:310$6280'.
  Set init value: \tx_buf_wr_addr = 8'00000000
  Set init value: \tx_buf_wr_data = 8'00000000
  Set init value: \tx_buf_wr = 1'0
  Set init value: \tx_buf_rd_addr = 8'00000000
  Set init value: \tx_buf_overflow = 2'00
Found init rule in `\profibus_phy.$proc$profibus_phy_mod.v:277$6279'.
  Set init value: \n_poweronreset_status = 1'0
  Set init value: \n_hardreset_status = 1'0
  Set init value: \softreset_status = 1'0
  Set init value: \softreset = 1'0
Found init rule in `\profibus_telegram_length.$proc$profibus_phy_mod.v:101$5344'.
  Set init value: \length_valid = 1'0
  Set init value: \error = 1'0
  Set init value: \byte_le = 8'00000000
  Set init value: \state = 2'00
  Set init value: \length = 8'00000000
Found init rule in `$paramod\uart_half_duplex\DATABITS=8\PARITY_EVEN=1\STOP=1\ACTIVE_LOW=0.$proc$uart_mod.v:577$6496'.
  Set init value: \tx_trigger_req = 1'0
  Set init value: \tx_data_r = 8'00000000
Found init rule in `$paramod\spi_slave\WORDSIZE=8\CPOL=0\CPHA=0\MSB_FIRST=1.$proc$spi_slave_mod.v:71$6488'.
  Set init value: \miso_r = 1'0
  Set init value: \rx_irq_r = 1'0
  Set init value: \rx_data_r = 8'00000000
  Set init value: \rx_shiftreg = 8'00000000
  Set init value: \tx_shiftreg = 8'00000000
  Set init value: \bit_count = 6'000000
Found init rule in `$paramod\uart_rx\DATABITS=8\PARITY_EVEN=1\ACTIVE_LOW=0.$proc$uart_mod.v:175$9245'.
  Set init value: \rx_parity = 1'0
  Set init value: \rx_active = 1'0
  Set init value: \rx_parity_ok = 1'0
  Set init value: \rx_frame_error = 1'0
  Set init value: \rx_irq = 1'0
  Set init value: \rx_data = 8'00000000
  Set init value: \sym_count = 4'0000
  Set init value: \rx_buf = 8'00000000
  Set init value: \rx_parity_buf = 1'0
  Set init value: \rx_frame_error_start = 1'0
  Set init value: \symclk_n_reset = 1'0
Found init rule in `$paramod\uart_tx\DATABITS=8\PARITY_EVEN=1\STOP=1\ACTIVE_LOW=0.$proc$uart_mod.v:322$9171'.
  Set init value: \symclk_n_reset = 1'0
  Set init value: \tx_irq = 1'0
  Set init value: \tx_r = 1'1
  Set init value: \tx_active = 1'0
Found init rule in `\uart_symclk.$proc$uart_mod.v:64$25'.
  Set init value: \symend = 1'0
  Set init value: \count = 24'000000000000000000000000
  Set init value: \setup = 1'0
  Set init value: \sample = 1'0
Found init rule in `\sync_signal.$proc$sync_signal_mod.v:34$6'.
  Set init value: \shiftreg = 3'000

2.3.5. Executing PROC_ARST pass (detect async resets in processes).

2.3.6. Executing PROC_MUX pass (convert decision trees to multiplexers).
Creating decoders for process `$paramod\led_blink\BLINK_ON_CLKS=2400000\BLINK_OFF_CLKS=685714.$proc$led_blink_mod.v:38$9251'.
Creating decoders for process `$paramod\led_blink\BLINK_ON_CLKS=2400000\BLINK_OFF_CLKS=685714.$proc$led_blink_mod.v:44$9246'.
     1/3: $0\led_off_count[31:0]
     2/3: $0\led_on_count[31:0]
     3/3: $0\led[0:0]
Creating decoders for process `\profibus_phy.$proc$profibus_phy_mod.v:1040$6287'.
Creating decoders for process `\profibus_phy.$proc$profibus_phy_mod.v:869$6286'.
Creating decoders for process `\profibus_phy.$proc$profibus_phy_mod.v:577$6285'.
Creating decoders for process `\profibus_phy.$proc$profibus_phy_mod.v:472$6284'.
Creating decoders for process `\profibus_phy.$proc$profibus_phy_mod.v:455$6283'.
Creating decoders for process `\profibus_phy.$proc$profibus_phy_mod.v:423$6282'.
Creating decoders for process `\profibus_phy.$proc$profibus_phy_mod.v:358$6281'.
Creating decoders for process `\profibus_phy.$proc$profibus_phy_mod.v:310$6280'.
Creating decoders for process `\profibus_phy.$proc$profibus_phy_mod.v:277$6279'.
Creating decoders for process `\profibus_phy.$proc$profibus_phy_mod.v:592$6275'.
Creating decoders for process `\profibus_phy.$proc$profibus_phy_mod.v:366$6271'.
Creating decoders for process `\profibus_phy.$proc$profibus_phy_mod.v:318$6267'.
Creating decoders for process `\profibus_phy.$proc$profibus_phy_mod.v:1046$6259'.
     1/3: $0\timer_idle_active[0:0]
     2/3: $0\timer_idle_saved[23:0]
     3/3: $0\timer_idle[23:0]
Creating decoders for process `\profibus_phy.$proc$profibus_phy_mod.v:881$5661'.
     1/333: $6\spi_tx_data[7:0] [7]
     2/333: $6$func$\parity8$profibus_phy_mod.v:978$5371$\parity8[0:0]$6216
     3/333: $6$func$\parity9$parity_func.v:55$5372$\parity9[0:0]$6226
     4/333: $6$func$\parity9$parity_func.v:55$5372$\i[0:0]$6236
     5/333: $6$func$\parity9$parity_func.v:55$5372$\h[0:0]$6235
     6/333: $6$func$\parity9$parity_func.v:55$5372$\g[0:0]$6234
     7/333: $6$func$\parity9$parity_func.v:55$5372$\f[0:0]$6233
     8/333: $6$func$\parity9$parity_func.v:55$5372$\e[0:0]$6232
     9/333: $6$func$\parity9$parity_func.v:55$5372$\d[0:0]$6231
    10/333: $6$func$\parity9$parity_func.v:55$5372$\c[0:0]$6230
    11/333: $6$func$\parity9$parity_func.v:55$5372$\b[0:0]$6229
    12/333: $6$func$\parity9$parity_func.v:55$5372$\a[0:0]$6228
    13/333: $6$func$\parity9$parity_func.v:55$5372$\odd[0:0]$6227
    14/333: $6$func$\parity8$profibus_phy_mod.v:978$5371$\h[0:0]$6225
    15/333: $6$func$\parity8$profibus_phy_mod.v:978$5371$\g[0:0]$6224
    16/333: $6$func$\parity8$profibus_phy_mod.v:978$5371$\f[0:0]$6223
    17/333: $6$func$\parity8$profibus_phy_mod.v:978$5371$\e[0:0]$6222
    18/333: $6$func$\parity8$profibus_phy_mod.v:978$5371$\d[0:0]$6221
    19/333: $6$func$\parity8$profibus_phy_mod.v:978$5371$\c[0:0]$6220
    20/333: $6$func$\parity8$profibus_phy_mod.v:978$5371$\b[0:0]$6219
    21/333: $6$func$\parity8$profibus_phy_mod.v:978$5371$\a[0:0]$6218
    22/333: $6$func$\parity8$profibus_phy_mod.v:978$5371$\odd[0:0]$6217
    23/333: $6\spi_tx_data[7:0] [3]
    24/333: $6\spi_tx_data[7:0] [2]
    25/333: $6\spi_tx_data[7:0] [1]
    26/333: $6\spi_tx_data[7:0] [0]
    27/333: $6\spi_tx_data[7:0] [6]
    28/333: $6\spi_tx_data[7:0] [5]
    29/333: $6\spi_tx_data[7:0] [4]
    30/333: $5\spi_tx_data[7:0]
    31/333: $5$func$\parity9$parity_func.v:55$5372$\i[0:0]$6213
    32/333: $5$func$\parity9$parity_func.v:55$5372$\h[0:0]$6212
    33/333: $5$func$\parity9$parity_func.v:55$5372$\g[0:0]$6211
    34/333: $5$func$\parity9$parity_func.v:55$5372$\f[0:0]$6210
    35/333: $5$func$\parity9$parity_func.v:55$5372$\e[0:0]$6209
    36/333: $5$func$\parity9$parity_func.v:55$5372$\d[0:0]$6208
    37/333: $5$func$\parity9$parity_func.v:55$5372$\c[0:0]$6207
    38/333: $5$func$\parity9$parity_func.v:55$5372$\b[0:0]$6206
    39/333: $5$func$\parity9$parity_func.v:55$5372$\a[0:0]$6205
    40/333: $5$func$\parity9$parity_func.v:55$5372$\odd[0:0]$6204
    41/333: $5$func$\parity9$parity_func.v:55$5372$\parity9[0:0]$6203
    42/333: $5$func$\parity8$profibus_phy_mod.v:978$5371$\h[0:0]$6202
    43/333: $5$func$\parity8$profibus_phy_mod.v:978$5371$\g[0:0]$6201
    44/333: $5$func$\parity8$profibus_phy_mod.v:978$5371$\f[0:0]$6200
    45/333: $5$func$\parity8$profibus_phy_mod.v:978$5371$\e[0:0]$6199
    46/333: $5$func$\parity8$profibus_phy_mod.v:978$5371$\d[0:0]$6198
    47/333: $5$func$\parity8$profibus_phy_mod.v:978$5371$\c[0:0]$6197
    48/333: $5$func$\parity8$profibus_phy_mod.v:978$5371$\b[0:0]$6196
    49/333: $5$func$\parity8$profibus_phy_mod.v:978$5371$\a[0:0]$6195
    50/333: $5$func$\parity8$profibus_phy_mod.v:978$5371$\odd[0:0]$6194
    51/333: $5$func$\parity8$profibus_phy_mod.v:978$5371$\parity8[0:0]$6193
    52/333: $4$func$\parity9$parity_func.v:55$5372$\i[0:0]$6191
    53/333: $4$func$\parity9$parity_func.v:55$5372$\h[0:0]$6190
    54/333: $4$func$\parity9$parity_func.v:55$5372$\g[0:0]$6189
    55/333: $4$func$\parity9$parity_func.v:55$5372$\f[0:0]$6188
    56/333: $4$func$\parity9$parity_func.v:55$5372$\e[0:0]$6187
    57/333: $4$func$\parity9$parity_func.v:55$5372$\d[0:0]$6186
    58/333: $4$func$\parity9$parity_func.v:55$5372$\c[0:0]$6185
    59/333: $4$func$\parity9$parity_func.v:55$5372$\b[0:0]$6184
    60/333: $4$func$\parity9$parity_func.v:55$5372$\a[0:0]$6183
    61/333: $4$func$\parity9$parity_func.v:55$5372$\odd[0:0]$6182
    62/333: $4$func$\parity9$parity_func.v:55$5372$\parity9[0:0]$6181
    63/333: $4$func$\parity8$profibus_phy_mod.v:978$5371$\h[0:0]$6180
    64/333: $4$func$\parity8$profibus_phy_mod.v:978$5371$\g[0:0]$6179
    65/333: $4$func$\parity8$profibus_phy_mod.v:978$5371$\f[0:0]$6178
    66/333: $4$func$\parity8$profibus_phy_mod.v:978$5371$\e[0:0]$6177
    67/333: $4$func$\parity8$profibus_phy_mod.v:978$5371$\d[0:0]$6176
    68/333: $4$func$\parity8$profibus_phy_mod.v:978$5371$\c[0:0]$6175
    69/333: $4$func$\parity8$profibus_phy_mod.v:978$5371$\b[0:0]$6174
    70/333: $4$func$\parity8$profibus_phy_mod.v:978$5371$\a[0:0]$6173
    71/333: $4$func$\parity8$profibus_phy_mod.v:978$5371$\odd[0:0]$6172
    72/333: $4$func$\parity8$profibus_phy_mod.v:978$5371$\parity8[0:0]$6171
    73/333: $4\spi_tx_data[7:0]
    74/333: $3$func$\parity9$parity_func.v:55$5372$\i[0:0]$6170
    75/333: $3$func$\parity9$parity_func.v:55$5372$\h[0:0]$6169
    76/333: $3$func$\parity9$parity_func.v:55$5372$\g[0:0]$6168
    77/333: $3$func$\parity9$parity_func.v:55$5372$\f[0:0]$6167
    78/333: $3$func$\parity9$parity_func.v:55$5372$\e[0:0]$6166
    79/333: $3$func$\parity9$parity_func.v:55$5372$\d[0:0]$6165
    80/333: $3$func$\parity9$parity_func.v:55$5372$\c[0:0]$6164
    81/333: $3$func$\parity9$parity_func.v:55$5372$\b[0:0]$6163
    82/333: $3$func$\parity9$parity_func.v:55$5372$\a[0:0]$6162
    83/333: $3$func$\parity9$parity_func.v:55$5372$\odd[0:0]$6161
    84/333: $3$func$\parity9$parity_func.v:55$5372$\parity9[0:0]$6160
    85/333: $3$func$\parity8$profibus_phy_mod.v:978$5371$\h[0:0]$6159
    86/333: $3$func$\parity8$profibus_phy_mod.v:978$5371$\g[0:0]$6158
    87/333: $3$func$\parity8$profibus_phy_mod.v:978$5371$\f[0:0]$6157
    88/333: $3$func$\parity8$profibus_phy_mod.v:978$5371$\e[0:0]$6156
    89/333: $3$func$\parity8$profibus_phy_mod.v:978$5371$\d[0:0]$6155
    90/333: $3$func$\parity8$profibus_phy_mod.v:978$5371$\c[0:0]$6154
    91/333: $3$func$\parity8$profibus_phy_mod.v:978$5371$\b[0:0]$6153
    92/333: $3$func$\parity8$profibus_phy_mod.v:978$5371$\a[0:0]$6152
    93/333: $3$func$\parity8$profibus_phy_mod.v:978$5371$\odd[0:0]$6151
    94/333: $3$func$\parity8$profibus_phy_mod.v:978$5371$\parity8[0:0]$6150
    95/333: $3\spi_tx_data[7:0]
    96/333: $2\spi_tx_data[7:0] [7]
    97/333: $4$func$\crc8$profibus_phy_mod.v:940$5370$\crc8[7:0]$5907 [4]
    98/333: $4$func$\crc8$profibus_phy_mod.v:940$5370$\crc8[7:0]$5907 [3]
    99/333: $4$func$\crc8$profibus_phy_mod.v:940$5370$\crc8[7:0]$5907 [2]
   100/333: $4$func$\crc8$profibus_phy_mod.v:940$5370$\crc8[7:0]$5907 [1]
   101/333: $4$func$\crc8$profibus_phy_mod.v:940$5370$\crc8[7:0]$5907 [0]
   102/333: $4$func$\crc8$profibus_phy_mod.v:934$5369$\crc8[7:0]$5904 [7]
   103/333: $4$func$\crc8$profibus_phy_mod.v:934$5369$\crc8[7:0]$5904 [6]
   104/333: $4$func$\crc8$profibus_phy_mod.v:934$5369$\crc8[7:0]$5904 [3]
   105/333: $4$func$\crc8$profibus_phy_mod.v:934$5369$\crc8[7:0]$5904 [2]
   106/333: $4$func$\crc8$profibus_phy_mod.v:934$5369$\crc8[7:0]$5904 [1]
   107/333: $4$func$\crc8$profibus_phy_mod.v:934$5369$\crc8[7:0]$5904 [0]
   108/333: $4$func$\crc8$profibus_phy_mod.v:928$5368$\crc8[7:0]$5901 [7]
   109/333: $4$func$\crc8$profibus_phy_mod.v:928$5368$\crc8[7:0]$5901 [6]
   110/333: $4$func$\crc8$profibus_phy_mod.v:928$5368$\crc8[7:0]$5901 [5]
   111/333: $4$func$\crc8$profibus_phy_mod.v:928$5368$\crc8[7:0]$5901 [2]
   112/333: $4$func$\crc8$profibus_phy_mod.v:928$5368$\crc8[7:0]$5901 [1]
   113/333: $4$func$\crc8$profibus_phy_mod.v:928$5368$\crc8[7:0]$5901 [0]
   114/333: $4$func$\crc8$profibus_phy_mod.v:922$5367$\crc8[7:0]$5898 [7]
   115/333: $4$func$\crc8$profibus_phy_mod.v:922$5367$\crc8[7:0]$5898 [6]
   116/333: $4$func$\crc8$profibus_phy_mod.v:922$5367$\crc8[7:0]$5898 [5]
   117/333: $4$func$\crc8$profibus_phy_mod.v:922$5367$\crc8[7:0]$5898 [4]
   118/333: $4$func$\crc8$profibus_phy_mod.v:922$5367$\crc8[7:0]$5898 [1]
   119/333: $4$func$\crc8$profibus_phy_mod.v:922$5367$\crc8[7:0]$5898 [0]
   120/333: $4$func$\crc8$profibus_phy_mod.v:916$5366$\crc8[7:0]$5895 [7]
   121/333: $4$func$\crc8$profibus_phy_mod.v:916$5366$\crc8[7:0]$5895 [6]
   122/333: $4$func$\crc8$profibus_phy_mod.v:916$5366$\crc8[7:0]$5895 [5]
   123/333: $4$func$\crc8$profibus_phy_mod.v:916$5366$\crc8[7:0]$5895 [4]
   124/333: $4$func$\crc8$profibus_phy_mod.v:916$5366$\crc8[7:0]$5895 [3]
   125/333: $4$func$\crc8$profibus_phy_mod.v:916$5366$\crc8[7:0]$5895 [0]
   126/333: $2\spi_tx_data[7:0] [6]
   127/333: $4$func$\crc8$profibus_phy_mod.v:940$5370$\crc8[7:0]$5907 [5]
   128/333: $4$func$\crc8$profibus_phy_mod.v:934$5369$\crc8[7:0]$5904 [4]
   129/333: $4$func$\crc8$profibus_phy_mod.v:928$5368$\crc8[7:0]$5901 [3]
   130/333: $4$func$\crc8$profibus_phy_mod.v:922$5367$\crc8[7:0]$5898 [2]
   131/333: $4$func$\crc8$profibus_phy_mod.v:916$5366$\crc8[7:0]$5895 [1]
   132/333: $4$func$\crc8$profibus_phy_mod.v:940$5370$\crc8[7:0]$5907 [7]
   133/333: $4$func$\crc8$profibus_phy_mod.v:940$5370$\crc8[7:0]$5907 [6]
   134/333: $4$func$\crc8$profibus_phy_mod.v:934$5369$\crc8[7:0]$5904 [5]
   135/333: $4$func$\crc8$profibus_phy_mod.v:928$5368$\crc8[7:0]$5901 [4]
   136/333: $4$func$\crc8$profibus_phy_mod.v:922$5367$\crc8[7:0]$5898 [3]
   137/333: $4$func$\crc8$profibus_phy_mod.v:916$5366$\crc8[7:0]$5895 [2]
   138/333: $2\spi_tx_data[7:0] [0]
   139/333: $4$func$\crc8$profibus_phy_mod.v:940$5370$\crcIn[7:0]$5908
   140/333: $2\spi_tx_data[7:0] [5]
   141/333: $4$func$\crc8$profibus_phy_mod.v:934$5369$\data[7:0]$5906
   142/333: $4$func$\crc8$profibus_phy_mod.v:934$5369$\crcIn[7:0]$5905
   143/333: $2\spi_tx_data[7:0] [4]
   144/333: $4$func$\crc8$profibus_phy_mod.v:928$5368$\data[7:0]$5903
   145/333: $4$func$\crc8$profibus_phy_mod.v:928$5368$\crcIn[7:0]$5902
   146/333: $2\spi_tx_data[7:0] [3]
   147/333: $4$func$\crc8$profibus_phy_mod.v:922$5367$\data[7:0]$5900
   148/333: $4$func$\crc8$profibus_phy_mod.v:922$5367$\crcIn[7:0]$5899
   149/333: $2\spi_tx_data[7:0] [2]
   150/333: $4$func$\crc8$profibus_phy_mod.v:916$5366$\data[7:0]$5897
   151/333: $4$func$\crc8$profibus_phy_mod.v:916$5366$\crcIn[7:0]$5896
   152/333: $2\spi_tx_data[7:0] [1]
   153/333: $4$func$\parity9$parity_func.v:55$5365$\i[0:0]$5894
   154/333: $4$func$\parity9$parity_func.v:55$5365$\h[0:0]$5893
   155/333: $4$func$\parity9$parity_func.v:55$5365$\g[0:0]$5892
   156/333: $4$func$\parity9$parity_func.v:55$5365$\f[0:0]$5891
   157/333: $4$func$\parity9$parity_func.v:55$5365$\e[0:0]$5890
   158/333: $4$func$\parity9$parity_func.v:55$5365$\d[0:0]$5889
   159/333: $4$func$\parity9$parity_func.v:55$5365$\c[0:0]$5888
   160/333: $4$func$\parity9$parity_func.v:55$5365$\b[0:0]$5887
   161/333: $4$func$\parity9$parity_func.v:55$5365$\a[0:0]$5886
   162/333: $4$func$\parity9$parity_func.v:55$5365$\odd[0:0]$5885
   163/333: $4$func$\parity9$parity_func.v:55$5365$\parity9[0:0]$5884
   164/333: $4$func$\parity8$profibus_phy_mod.v:902$5364$\h[0:0]$5883
   165/333: $4$func$\parity8$profibus_phy_mod.v:902$5364$\g[0:0]$5882
   166/333: $4$func$\parity8$profibus_phy_mod.v:902$5364$\f[0:0]$5881
   167/333: $4$func$\parity8$profibus_phy_mod.v:902$5364$\e[0:0]$5880
   168/333: $4$func$\parity8$profibus_phy_mod.v:902$5364$\d[0:0]$5879
   169/333: $4$func$\parity8$profibus_phy_mod.v:902$5364$\c[0:0]$5878
   170/333: $4$func$\parity8$profibus_phy_mod.v:902$5364$\b[0:0]$5877
   171/333: $4$func$\parity8$profibus_phy_mod.v:902$5364$\a[0:0]$5876
   172/333: $4$func$\parity8$profibus_phy_mod.v:902$5364$\odd[0:0]$5875
   173/333: $4$func$\parity8$profibus_phy_mod.v:902$5364$\parity8[0:0]$5874
   174/333: $3$func$\crc8$profibus_phy_mod.v:940$5370$\data[7:0]$5873
   175/333: $3$func$\crc8$profibus_phy_mod.v:940$5370$\crcIn[7:0]$5872
   176/333: $3$func$\crc8$profibus_phy_mod.v:940$5370$\crc8[7:0]$5871
   177/333: $3$func$\crc8$profibus_phy_mod.v:934$5369$\data[7:0]$5870
   178/333: $3$func$\crc8$profibus_phy_mod.v:934$5369$\crcIn[7:0]$5869
   179/333: $3$func$\crc8$profibus_phy_mod.v:934$5369$\crc8[7:0]$5868
   180/333: $3$func$\crc8$profibus_phy_mod.v:928$5368$\data[7:0]$5867
   181/333: $3$func$\crc8$profibus_phy_mod.v:928$5368$\crcIn[7:0]$5866
   182/333: $3$func$\crc8$profibus_phy_mod.v:928$5368$\crc8[7:0]$5865
   183/333: $3$func$\crc8$profibus_phy_mod.v:922$5367$\data[7:0]$5864
   184/333: $3$func$\crc8$profibus_phy_mod.v:922$5367$\crcIn[7:0]$5863
   185/333: $3$func$\crc8$profibus_phy_mod.v:922$5367$\crc8[7:0]$5862
   186/333: $3$func$\crc8$profibus_phy_mod.v:916$5366$\data[7:0]$5861
   187/333: $3$func$\crc8$profibus_phy_mod.v:916$5366$\crcIn[7:0]$5860
   188/333: $3$func$\crc8$profibus_phy_mod.v:916$5366$\crc8[7:0]$5859
   189/333: $3$func$\parity9$parity_func.v:55$5365$\i[0:0]$5858
   190/333: $3$func$\parity9$parity_func.v:55$5365$\h[0:0]$5857
   191/333: $3$func$\parity9$parity_func.v:55$5365$\g[0:0]$5856
   192/333: $3$func$\parity9$parity_func.v:55$5365$\f[0:0]$5855
   193/333: $3$func$\parity9$parity_func.v:55$5365$\e[0:0]$5854
   194/333: $3$func$\parity9$parity_func.v:55$5365$\d[0:0]$5853
   195/333: $3$func$\parity9$parity_func.v:55$5365$\c[0:0]$5852
   196/333: $3$func$\parity9$parity_func.v:55$5365$\b[0:0]$5851
   197/333: $3$func$\parity9$parity_func.v:55$5365$\a[0:0]$5850
   198/333: $3$func$\parity9$parity_func.v:55$5365$\odd[0:0]$5849
   199/333: $3$func$\parity9$parity_func.v:55$5365$\parity9[0:0]$5848
   200/333: $3$func$\parity8$profibus_phy_mod.v:902$5364$\h[0:0]$5847
   201/333: $3$func$\parity8$profibus_phy_mod.v:902$5364$\g[0:0]$5846
   202/333: $3$func$\parity8$profibus_phy_mod.v:902$5364$\f[0:0]$5845
   203/333: $3$func$\parity8$profibus_phy_mod.v:902$5364$\e[0:0]$5844
   204/333: $3$func$\parity8$profibus_phy_mod.v:902$5364$\d[0:0]$5843
   205/333: $3$func$\parity8$profibus_phy_mod.v:902$5364$\c[0:0]$5842
   206/333: $3$func$\parity8$profibus_phy_mod.v:902$5364$\b[0:0]$5841
   207/333: $3$func$\parity8$profibus_phy_mod.v:902$5364$\a[0:0]$5840
   208/333: $3$func$\parity8$profibus_phy_mod.v:902$5364$\odd[0:0]$5839
   209/333: $3$func$\parity8$profibus_phy_mod.v:902$5364$\parity8[0:0]$5838
   210/333: $2$func$\crc8$profibus_phy_mod.v:940$5370$\data[7:0]$5816
   211/333: $2$func$\crc8$profibus_phy_mod.v:940$5370$\crcIn[7:0]$5815
   212/333: $2$func$\crc8$profibus_phy_mod.v:940$5370$\crc8[7:0]$5814
   213/333: $2$func$\crc8$profibus_phy_mod.v:934$5369$\data[7:0]$5813
   214/333: $2$func$\crc8$profibus_phy_mod.v:934$5369$\crcIn[7:0]$5812
   215/333: $2$func$\crc8$profibus_phy_mod.v:934$5369$\crc8[7:0]$5811
   216/333: $2$func$\crc8$profibus_phy_mod.v:928$5368$\data[7:0]$5810
   217/333: $2$func$\crc8$profibus_phy_mod.v:928$5368$\crcIn[7:0]$5809
   218/333: $2$func$\crc8$profibus_phy_mod.v:928$5368$\crc8[7:0]$5808
   219/333: $2$func$\crc8$profibus_phy_mod.v:922$5367$\data[7:0]$5807
   220/333: $2$func$\crc8$profibus_phy_mod.v:922$5367$\crcIn[7:0]$5806
   221/333: $2$func$\crc8$profibus_phy_mod.v:922$5367$\crc8[7:0]$5805
   222/333: $2$func$\crc8$profibus_phy_mod.v:916$5366$\data[7:0]$5804
   223/333: $2$func$\crc8$profibus_phy_mod.v:916$5366$\crcIn[7:0]$5803
   224/333: $2$func$\crc8$profibus_phy_mod.v:916$5366$\crc8[7:0]$5802
   225/333: $2$func$\parity9$parity_func.v:55$5365$\i[0:0]$5801
   226/333: $2$func$\parity9$parity_func.v:55$5365$\h[0:0]$5800
   227/333: $2$func$\parity9$parity_func.v:55$5365$\g[0:0]$5799
   228/333: $2$func$\parity9$parity_func.v:55$5365$\f[0:0]$5798
   229/333: $2$func$\parity9$parity_func.v:55$5365$\e[0:0]$5797
   230/333: $2$func$\parity9$parity_func.v:55$5365$\d[0:0]$5796
   231/333: $2$func$\parity9$parity_func.v:55$5365$\c[0:0]$5795
   232/333: $2$func$\parity9$parity_func.v:55$5365$\b[0:0]$5794
   233/333: $2$func$\parity9$parity_func.v:55$5365$\a[0:0]$5793
   234/333: $2$func$\parity9$parity_func.v:55$5365$\odd[0:0]$5792
   235/333: $2$func$\parity9$parity_func.v:55$5365$\parity9[0:0]$5791
   236/333: $2$func$\parity8$profibus_phy_mod.v:902$5364$\h[0:0]$5790
   237/333: $2$func$\parity8$profibus_phy_mod.v:902$5364$\g[0:0]$5789
   238/333: $2$func$\parity8$profibus_phy_mod.v:902$5364$\f[0:0]$5788
   239/333: $2$func$\parity8$profibus_phy_mod.v:902$5364$\e[0:0]$5787
   240/333: $2$func$\parity8$profibus_phy_mod.v:902$5364$\d[0:0]$5786
   241/333: $2$func$\parity8$profibus_phy_mod.v:902$5364$\c[0:0]$5785
   242/333: $2$func$\parity8$profibus_phy_mod.v:902$5364$\b[0:0]$5784
   243/333: $2$func$\parity8$profibus_phy_mod.v:902$5364$\a[0:0]$5783
   244/333: $2$func$\parity8$profibus_phy_mod.v:902$5364$\odd[0:0]$5782
   245/333: $2$func$\parity8$profibus_phy_mod.v:902$5364$\parity8[0:0]$5781
   246/333: $2$func$\parity9$parity_func.v:55$5372$\i[0:0]$5837
   247/333: $2$func$\parity9$parity_func.v:55$5372$\h[0:0]$5836
   248/333: $2$func$\parity9$parity_func.v:55$5372$\g[0:0]$5835
   249/333: $2$func$\parity9$parity_func.v:55$5372$\f[0:0]$5834
   250/333: $2$func$\parity9$parity_func.v:55$5372$\e[0:0]$5833
   251/333: $2$func$\parity9$parity_func.v:55$5372$\d[0:0]$5832
   252/333: $2$func$\parity9$parity_func.v:55$5372$\c[0:0]$5831
   253/333: $2$func$\parity9$parity_func.v:55$5372$\b[0:0]$5830
   254/333: $2$func$\parity9$parity_func.v:55$5372$\a[0:0]$5829
   255/333: $2$func$\parity9$parity_func.v:55$5372$\odd[0:0]$5828
   256/333: $2$func$\parity9$parity_func.v:55$5372$\parity9[0:0]$5827
   257/333: $2$func$\parity8$profibus_phy_mod.v:978$5371$\h[0:0]$5826
   258/333: $2$func$\parity8$profibus_phy_mod.v:978$5371$\g[0:0]$5825
   259/333: $2$func$\parity8$profibus_phy_mod.v:978$5371$\f[0:0]$5824
   260/333: $2$func$\parity8$profibus_phy_mod.v:978$5371$\e[0:0]$5823
   261/333: $2$func$\parity8$profibus_phy_mod.v:978$5371$\d[0:0]$5822
   262/333: $2$func$\parity8$profibus_phy_mod.v:978$5371$\c[0:0]$5821
   263/333: $2$func$\parity8$profibus_phy_mod.v:978$5371$\b[0:0]$5820
   264/333: $2$func$\parity8$profibus_phy_mod.v:978$5371$\a[0:0]$5819
   265/333: $2$func$\parity8$profibus_phy_mod.v:978$5371$\odd[0:0]$5818
   266/333: $2$func$\parity8$profibus_phy_mod.v:978$5371$\parity8[0:0]$5817
   267/333: $4$func$\crc8$profibus_phy_mod.v:940$5370$\data[7:0]$5909
   268/333: $1$func$\parity9$parity_func.v:55$5372$\i[0:0]$5777
   269/333: $1$func$\parity9$parity_func.v:55$5372$\h[0:0]$5776
   270/333: $1$func$\parity9$parity_func.v:55$5372$\g[0:0]$5775
   271/333: $1$func$\parity9$parity_func.v:55$5372$\f[0:0]$5774
   272/333: $1$func$\parity9$parity_func.v:55$5372$\e[0:0]$5773
   273/333: $1$func$\parity9$parity_func.v:55$5372$\d[0:0]$5772
   274/333: $1$func$\parity9$parity_func.v:55$5372$\c[0:0]$5771
   275/333: $1$func$\parity9$parity_func.v:55$5372$\b[0:0]$5770
   276/333: $1$func$\parity9$parity_func.v:55$5372$\a[0:0]$5769
   277/333: $1$func$\parity9$parity_func.v:55$5372$\odd[0:0]$5768
   278/333: $1$func$\parity9$parity_func.v:55$5372$\parity9[0:0]$5767
   279/333: $1$func$\parity8$profibus_phy_mod.v:978$5371$\h[0:0]$5766
   280/333: $1$func$\parity8$profibus_phy_mod.v:978$5371$\g[0:0]$5765
   281/333: $1$func$\parity8$profibus_phy_mod.v:978$5371$\f[0:0]$5764
   282/333: $1$func$\parity8$profibus_phy_mod.v:978$5371$\e[0:0]$5763
   283/333: $1$func$\parity8$profibus_phy_mod.v:978$5371$\d[0:0]$5762
   284/333: $1$func$\parity8$profibus_phy_mod.v:978$5371$\c[0:0]$5761
   285/333: $1$func$\parity8$profibus_phy_mod.v:978$5371$\b[0:0]$5760
   286/333: $1$func$\parity8$profibus_phy_mod.v:978$5371$\a[0:0]$5759
   287/333: $1$func$\parity8$profibus_phy_mod.v:978$5371$\odd[0:0]$5758
   288/333: $1$func$\parity8$profibus_phy_mod.v:978$5371$\parity8[0:0]$5757
   289/333: $1$func$\crc8$profibus_phy_mod.v:940$5370$\data[7:0]$5756
   290/333: $1$func$\crc8$profibus_phy_mod.v:940$5370$\crcIn[7:0]$5755
   291/333: $1$func$\crc8$profibus_phy_mod.v:940$5370$\crc8[7:0]$5754
   292/333: $1$func$\crc8$profibus_phy_mod.v:934$5369$\data[7:0]$5753
   293/333: $1$func$\crc8$profibus_phy_mod.v:934$5369$\crcIn[7:0]$5752
   294/333: $1$func$\crc8$profibus_phy_mod.v:934$5369$\crc8[7:0]$5751
   295/333: $1$func$\crc8$profibus_phy_mod.v:928$5368$\data[7:0]$5750
   296/333: $1$func$\crc8$profibus_phy_mod.v:928$5368$\crcIn[7:0]$5749
   297/333: $1$func$\crc8$profibus_phy_mod.v:928$5368$\crc8[7:0]$5748
   298/333: $1$func$\crc8$profibus_phy_mod.v:922$5367$\data[7:0]$5747
   299/333: $1$func$\crc8$profibus_phy_mod.v:922$5367$\crcIn[7:0]$5746
   300/333: $1$func$\crc8$profibus_phy_mod.v:922$5367$\crc8[7:0]$5745
   301/333: $1$func$\crc8$profibus_phy_mod.v:916$5366$\data[7:0]$5744
   302/333: $1$func$\crc8$profibus_phy_mod.v:916$5366$\crcIn[7:0]$5743
   303/333: $1$func$\crc8$profibus_phy_mod.v:916$5366$\crc8[7:0]$5742
   304/333: $1$func$\parity9$parity_func.v:55$5365$\i[0:0]$5741
   305/333: $1$func$\parity9$parity_func.v:55$5365$\h[0:0]$5740
   306/333: $1$func$\parity9$parity_func.v:55$5365$\g[0:0]$5739
   307/333: $1$func$\parity9$parity_func.v:55$5365$\f[0:0]$5738
   308/333: $1$func$\parity9$parity_func.v:55$5365$\e[0:0]$5737
   309/333: $1$func$\parity9$parity_func.v:55$5365$\d[0:0]$5736
   310/333: $1$func$\parity9$parity_func.v:55$5365$\c[0:0]$5735
   311/333: $1$func$\parity9$parity_func.v:55$5365$\b[0:0]$5734
   312/333: $1$func$\parity9$parity_func.v:55$5365$\a[0:0]$5733
   313/333: $1$func$\parity9$parity_func.v:55$5365$\odd[0:0]$5732
   314/333: $1$func$\parity9$parity_func.v:55$5365$\parity9[0:0]$5731
   315/333: $1$func$\parity8$profibus_phy_mod.v:902$5364$\h[0:0]$5730
   316/333: $1$func$\parity8$profibus_phy_mod.v:902$5364$\g[0:0]$5729
   317/333: $1$func$\parity8$profibus_phy_mod.v:902$5364$\f[0:0]$5728
   318/333: $1$func$\parity8$profibus_phy_mod.v:902$5364$\e[0:0]$5727
   319/333: $1$func$\parity8$profibus_phy_mod.v:902$5364$\d[0:0]$5726
   320/333: $1$func$\parity8$profibus_phy_mod.v:902$5364$\c[0:0]$5725
   321/333: $1$func$\parity8$profibus_phy_mod.v:902$5364$\b[0:0]$5724
   322/333: $1$func$\parity8$profibus_phy_mod.v:902$5364$\a[0:0]$5723
   323/333: $1$func$\parity8$profibus_phy_mod.v:902$5364$\odd[0:0]$5722
   324/333: $1$func$\parity8$profibus_phy_mod.v:902$5364$\parity8[0:0]$5721
   325/333: $1\spi_tx_data[7:0]
   326/333: $0\spitx_crc[7:0]
   327/333: $0\spitx_data_running[0:0]
   328/333: $0\spitx_ctrl_running[0:0]
   329/333: $0\spitx_tail[0:0]
   330/333: $0\spitx_len[7:0]
   331/333: $0\spitx_bytecount[7:0]
   332/333: $0\spitx_ctrl_pending_ack[0:0]
   333/333: $0\rx_buf_rd_addr[7:0]
Creating decoders for process `\profibus_phy.$proc$profibus_phy_mod.v:604$5408'.
     1/141: $0\spitx_ctrl_reply_data[31:0] [23:6]
     2/141: $0\spitx_ctrl_reply_data[31:0] [4]
     3/141: $0\spitx_ctrl_reply_data[31:0] [3]
     4/141: $4$func$\spirx_ctrl_crcerr_get$profibus_phy_mod.v:764$5357$\spirx_ctrl_crcerr_get[0:0]$5648
     5/141: $0\spitx_ctrl_reply_data[31:0] [2]
     6/141: $4$func$\rx_buf_overflow_get$profibus_phy_mod.v:763$5356$\rx_buf_overflow_get[0:0]$5647
     7/141: $0\spitx_ctrl_reply_data[31:0] [1]
     8/141: $4$func$\tx_buf_overflow_get$profibus_phy_mod.v:762$5355$\tx_buf_overflow_get[0:0]$5646
     9/141: $0\spitx_ctrl_reply_data[31:0] [0]
    10/141: $0\spitx_ctrl_reply_data[31:0] [5]
    11/141: $0\spitx_ctrl_reply_data[31:0] [31:24]
    12/141: $3$func$\rx_buf_overflow_get$profibus_phy_mod.v:763$5356$\rx_buf_overflow_get[0:0]$5641
    13/141: $3$func$\tx_buf_overflow_get$profibus_phy_mod.v:762$5355$\tx_buf_overflow_get[0:0]$5640
    14/141: $0\spirx_ctrl_crcerr[1:0] [1]
    15/141: $0\spirx_ctrl_crcerr[1:0] [0]
    16/141: $3$func$\crc8$profibus_phy_mod.v:711$5353$\crc8[7:0]$5587 [5]
    17/141: $3$func$\crc8$profibus_phy_mod.v:711$5353$\crc8[7:0]$5587 [4]
    18/141: $3$func$\crc8$profibus_phy_mod.v:711$5353$\crc8[7:0]$5587 [3]
    19/141: $3$func$\crc8$profibus_phy_mod.v:711$5353$\crc8[7:0]$5587 [2]
    20/141: $3$func$\crc8$profibus_phy_mod.v:711$5353$\crc8[7:0]$5587 [1]
    21/141: $3$func$\crc8$profibus_phy_mod.v:711$5353$\crc8[7:0]$5587 [0]
    22/141: $3$func$\crc8$profibus_phy_mod.v:711$5353$\crc8[7:0]$5587 [6]
    23/141: $3$func$\crc8$profibus_phy_mod.v:711$5353$\data[7:0]$5589
    24/141: $3$func$\crc8$profibus_phy_mod.v:711$5353$\crcIn[7:0]$5588
    25/141: $3$func$\crc8$profibus_phy_mod.v:703$5352$\crc8[7:0]$5540 [7]
    26/141: $3$func$\crc8$profibus_phy_mod.v:703$5352$\crc8[7:0]$5540 [5]
    27/141: $3$func$\crc8$profibus_phy_mod.v:703$5352$\crc8[7:0]$5540 [4]
    28/141: $3$func$\crc8$profibus_phy_mod.v:703$5352$\crc8[7:0]$5540 [3]
    29/141: $3$func$\crc8$profibus_phy_mod.v:703$5352$\crc8[7:0]$5540 [2]
    30/141: $3$func$\crc8$profibus_phy_mod.v:703$5352$\crc8[7:0]$5540 [1]
    31/141: $3$func$\crc8$profibus_phy_mod.v:703$5352$\crc8[7:0]$5540 [0]
    32/141: $3$func$\crc8$profibus_phy_mod.v:703$5352$\crc8[7:0]$5540 [6]
    33/141: $3$func$\crc8$profibus_phy_mod.v:703$5352$\data[7:0]$5542
    34/141: $3$func$\crc8$profibus_phy_mod.v:703$5352$\crcIn[7:0]$5541
    35/141: $0\tx_buf_overflow[1:0] [1]
    36/141: $0\tx_buf_overflow[1:0] [0]
    37/141: $3$func$\parity9$parity_func.v:55$5350$\parity9[0:0]$5513
    38/141: $3$func$\parity9$parity_func.v:55$5350$\i[0:0]$5523
    39/141: $3$func$\parity9$parity_func.v:55$5350$\h[0:0]$5522
    40/141: $3$func$\parity9$parity_func.v:55$5350$\g[0:0]$5521
    41/141: $3$func$\parity9$parity_func.v:55$5350$\f[0:0]$5520
    42/141: $3$func$\parity9$parity_func.v:55$5350$\e[0:0]$5519
    43/141: $3$func$\parity9$parity_func.v:55$5350$\d[0:0]$5518
    44/141: $3$func$\parity9$parity_func.v:55$5350$\c[0:0]$5517
    45/141: $3$func$\parity9$parity_func.v:55$5350$\b[0:0]$5516
    46/141: $3$func$\parity9$parity_func.v:55$5350$\a[0:0]$5515
    47/141: $3$func$\parity9$parity_func.v:55$5350$\odd[0:0]$5514
    48/141: $3$func$\parity8$profibus_phy_mod.v:631$5349$\h[0:0]$5512
    49/141: $3$func$\parity8$profibus_phy_mod.v:631$5349$\g[0:0]$5511
    50/141: $3$func$\parity8$profibus_phy_mod.v:631$5349$\f[0:0]$5510
    51/141: $3$func$\parity8$profibus_phy_mod.v:631$5349$\e[0:0]$5509
    52/141: $3$func$\parity8$profibus_phy_mod.v:631$5349$\d[0:0]$5508
    53/141: $3$func$\parity8$profibus_phy_mod.v:631$5349$\c[0:0]$5507
    54/141: $3$func$\parity8$profibus_phy_mod.v:631$5349$\b[0:0]$5506
    55/141: $3$func$\parity8$profibus_phy_mod.v:631$5349$\a[0:0]$5505
    56/141: $3$func$\parity8$profibus_phy_mod.v:631$5349$\odd[0:0]$5504
    57/141: $2$func$\spirx_ctrl_crcerr_get$profibus_phy_mod.v:764$5357$\spirx_ctrl_crcerr_get[0:0]$5500
    58/141: $2$func$\rx_buf_overflow_get$profibus_phy_mod.v:763$5356$\rx_buf_overflow_get[0:0]$5499
    59/141: $2$func$\tx_buf_overflow_get$profibus_phy_mod.v:762$5355$\tx_buf_overflow_get[0:0]$5498
    60/141: $2$func$\crc8$profibus_phy_mod.v:711$5353$\data[7:0]$5497
    61/141: $2$func$\crc8$profibus_phy_mod.v:711$5353$\crcIn[7:0]$5496
    62/141: $2$func$\crc8$profibus_phy_mod.v:711$5353$\crc8[7:0]$5495
    63/141: $2$func$\crc8$profibus_phy_mod.v:703$5352$\data[7:0]$5494
    64/141: $2$func$\crc8$profibus_phy_mod.v:703$5352$\crcIn[7:0]$5493
    65/141: $2$func$\crc8$profibus_phy_mod.v:703$5352$\crc8[7:0]$5492
    66/141: $2$func$\parity9$parity_func.v:55$5350$\i[0:0]$5491
    67/141: $2$func$\parity9$parity_func.v:55$5350$\h[0:0]$5490
    68/141: $2$func$\parity9$parity_func.v:55$5350$\g[0:0]$5489
    69/141: $2$func$\parity9$parity_func.v:55$5350$\f[0:0]$5488
    70/141: $2$func$\parity9$parity_func.v:55$5350$\e[0:0]$5487
    71/141: $2$func$\parity9$parity_func.v:55$5350$\d[0:0]$5486
    72/141: $2$func$\parity9$parity_func.v:55$5350$\c[0:0]$5485
    73/141: $2$func$\parity9$parity_func.v:55$5350$\b[0:0]$5484
    74/141: $2$func$\parity9$parity_func.v:55$5350$\a[0:0]$5483
    75/141: $2$func$\parity9$parity_func.v:55$5350$\odd[0:0]$5482
    76/141: $2$func$\parity9$parity_func.v:55$5350$\parity9[0:0]$5481
    77/141: $2$func$\parity8$profibus_phy_mod.v:631$5349$\h[0:0]$5480
    78/141: $2$func$\parity8$profibus_phy_mod.v:631$5349$\g[0:0]$5479
    79/141: $2$func$\parity8$profibus_phy_mod.v:631$5349$\f[0:0]$5478
    80/141: $2$func$\parity8$profibus_phy_mod.v:631$5349$\e[0:0]$5477
    81/141: $2$func$\parity8$profibus_phy_mod.v:631$5349$\d[0:0]$5476
    82/141: $2$func$\parity8$profibus_phy_mod.v:631$5349$\c[0:0]$5475
    83/141: $2$func$\parity8$profibus_phy_mod.v:631$5349$\b[0:0]$5474
    84/141: $2$func$\parity8$profibus_phy_mod.v:631$5349$\a[0:0]$5473
    85/141: $2$func$\parity8$profibus_phy_mod.v:631$5349$\odd[0:0]$5472
    86/141: $2$func$\parity8$profibus_phy_mod.v:631$5349$\parity8[0:0]$5471
    87/141: $1$func$\spirx_ctrl_crcerr_get$profibus_phy_mod.v:764$5357$\spirx_ctrl_crcerr_get[0:0]$5470
    88/141: $1$func$\rx_buf_overflow_get$profibus_phy_mod.v:763$5356$\rx_buf_overflow_get[0:0]$5469
    89/141: $1$func$\tx_buf_overflow_get$profibus_phy_mod.v:762$5355$\tx_buf_overflow_get[0:0]$5468
    90/141: $1$func$\crc8$profibus_phy_mod.v:711$5353$\data[7:0]$5467
    91/141: $1$func$\crc8$profibus_phy_mod.v:711$5353$\crcIn[7:0]$5466
    92/141: $1$func$\crc8$profibus_phy_mod.v:711$5353$\crc8[7:0]$5465
    93/141: $1$func$\crc8$profibus_phy_mod.v:703$5352$\data[7:0]$5464
    94/141: $1$func$\crc8$profibus_phy_mod.v:703$5352$\crcIn[7:0]$5463
    95/141: $1$func$\crc8$profibus_phy_mod.v:703$5352$\crc8[7:0]$5462
    96/141: $1$func$\parity9$parity_func.v:55$5350$\i[0:0]$5461
    97/141: $1$func$\parity9$parity_func.v:55$5350$\h[0:0]$5460
    98/141: $1$func$\parity9$parity_func.v:55$5350$\g[0:0]$5459
    99/141: $1$func$\parity9$parity_func.v:55$5350$\f[0:0]$5458
   100/141: $1$func$\parity9$parity_func.v:55$5350$\e[0:0]$5457
   101/141: $1$func$\parity9$parity_func.v:55$5350$\d[0:0]$5456
   102/141: $1$func$\parity9$parity_func.v:55$5350$\c[0:0]$5455
   103/141: $1$func$\parity9$parity_func.v:55$5350$\b[0:0]$5454
   104/141: $1$func$\parity9$parity_func.v:55$5350$\a[0:0]$5453
   105/141: $1$func$\parity9$parity_func.v:55$5350$\odd[0:0]$5452
   106/141: $1$func$\parity9$parity_func.v:55$5350$\parity9[0:0]$5451
   107/141: $1$func$\parity8$profibus_phy_mod.v:631$5349$\h[0:0]$5450
   108/141: $1$func$\parity8$profibus_phy_mod.v:631$5349$\g[0:0]$5449
   109/141: $1$func$\parity8$profibus_phy_mod.v:631$5349$\f[0:0]$5448
   110/141: $1$func$\parity8$profibus_phy_mod.v:631$5349$\e[0:0]$5447
   111/141: $1$func$\parity8$profibus_phy_mod.v:631$5349$\d[0:0]$5446
   112/141: $1$func$\parity8$profibus_phy_mod.v:631$5349$\c[0:0]$5445
   113/141: $1$func$\parity8$profibus_phy_mod.v:631$5349$\b[0:0]$5444
   114/141: $1$func$\parity8$profibus_phy_mod.v:631$5349$\a[0:0]$5443
   115/141: $1$func$\parity8$profibus_phy_mod.v:631$5349$\odd[0:0]$5442
   116/141: $1$func$\parity8$profibus_phy_mod.v:631$5349$\parity8[0:0]$5441
   117/141: $0\spitx_ctrl_pending[0:0]
   118/141: $3$func$\spirx_ctrl_crcerr_get$profibus_phy_mod.v:764$5357$\spirx_ctrl_crcerr_get[0:0]$5642
   119/141: $0\spitx_ctrl_reply[7:0]
   120/141: $0\spirx_lencalc_new[0:0]
   121/141: $0\spirx_lencalc_byte[7:0]
   122/141: $0\spirx_lencalc_n_reset[0:0]
   123/141: $3$func$\crc8$profibus_phy_mod.v:711$5353$\crc8[7:0]$5587 [7]
   124/141: $0\spirx_crc[7:0]
   125/141: $0\spirx_ctrl_data[31:0]
   126/141: $0\spirx_ctrl[7:0]
   127/141: $0\spirx_bytecount[7:0]
   128/141: $0\spirx_len_valid[0:0]
   129/141: $0\spirx_len[7:0]
   130/141: $0\spirx_state[2:0]
   131/141: $0\tsyn_clks[23:0]
   132/141: $0\uart_clks_per_sym[23:0]
   133/141: $0\rx_buf_overflow[1:1]
   134/141: $3$func$\parity8$profibus_phy_mod.v:631$5349$\parity8[0:0]$5503
   135/141: $0\tx_buf_wr[0:0]
   136/141: $0\tx_buf_wr_data[7:0]
   137/141: $0\tx_buf_wr_addr[7:0]
   138/141: $0\softreset[0:0]
   139/141: $0\softreset_status[0:0]
   140/141: $0\n_hardreset_status[0:0]
   141/141: $0\n_poweronreset_status[0:0]
Creating decoders for process `\profibus_phy.$proc$profibus_phy_mod.v:510$5397'.
     1/3: $0\uart_tx_trigger[0:0]
     2/3: $0\uart_tx_data[7:0]
     3/3: $0\tx_buf_rd_addr[7:0]
Creating decoders for process `\profibus_phy.$proc$profibus_phy_mod.v:476$5389'.
     1/5: $0\rx_buf_wr_data[8:0] [8]
     2/5: $0\rx_buf_wr_data[8:0] [7:0]
     3/5: $0\rx_buf_wr[0:0]
     4/5: $0\rx_buf_overflow[0:0]
     5/5: $0\rx_buf_wr_addr[7:0]
Creating decoders for process `\profibus_telegram_length.$proc$profibus_phy_mod.v:101$5344'.
Creating decoders for process `\profibus_telegram_length.$proc$profibus_phy_mod.v:109$5333'.
     1/5: $0\length[7:0]
     2/5: $0\state[1:0]
     3/5: $0\byte_le[7:0]
     4/5: $0\error[0:0]
     5/5: $0\length_valid[0:0]
Creating decoders for process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$proc$block_ram_mod.v:44$8562'.
Creating decoders for process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$proc$block_ram_mod.v:50$8299'.
     1/3: $0$memwr$\mem$block_ram_mod.v:52$8298_EN[7:0]$8302
     2/3: $0$memwr$\mem$block_ram_mod.v:52$8298_DATA[7:0]$8301
     3/3: $0$memwr$\mem$block_ram_mod.v:52$8298_ADDR[7:0]$8300
Creating decoders for process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$proc$block_ram_mod.v:44$7273'.
Creating decoders for process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$proc$block_ram_mod.v:50$7010'.
     1/3: $0$memwr$\mem$block_ram_mod.v:52$7009_EN[8:0]$7013
     2/3: $0$memwr$\mem$block_ram_mod.v:52$7009_DATA[8:0]$7012
     3/3: $0$memwr$\mem$block_ram_mod.v:52$7009_ADDR[7:0]$7011
Creating decoders for process `$paramod\uart_half_duplex\DATABITS=8\PARITY_EVEN=1\STOP=1\ACTIVE_LOW=0.$proc$uart_mod.v:577$6496'.
Creating decoders for process `$paramod\uart_half_duplex\DATABITS=8\PARITY_EVEN=1\STOP=1\ACTIVE_LOW=0.$proc$uart_mod.v:582$6492'.
     1/2: $0\tx_data_r[7:0]
     2/2: $0\tx_trigger_req[0:0]
Creating decoders for process `$paramod\spi_slave\WORDSIZE=8\CPOL=0\CPHA=0\MSB_FIRST=1.$proc$spi_slave_mod.v:71$6488'.
Creating decoders for process `$paramod\spi_slave\WORDSIZE=8\CPOL=0\CPHA=0\MSB_FIRST=1.$proc$spi_slave_mod.v:82$6479'.
     1/7: $0\rx_shiftreg[7:0] [7:1]
     2/7: $0\rx_shiftreg[7:0] [0]
     3/7: $0\bit_count[5:0]
     4/7: $0\tx_shiftreg[7:0]
     5/7: $0\rx_irq_r[0:0]
     6/7: $0\rx_data_r[7:0]
     7/7: $0\miso_r[0:0]
Creating decoders for process `$paramod\uart_rx\DATABITS=8\PARITY_EVEN=1\ACTIVE_LOW=0.$proc$uart_mod.v:175$9245'.
Creating decoders for process `$paramod\uart_rx\DATABITS=8\PARITY_EVEN=1\ACTIVE_LOW=0.$proc$parity_func.v:26$9207'.
Creating decoders for process `$paramod\uart_rx\DATABITS=8\PARITY_EVEN=1\ACTIVE_LOW=0.$proc$uart_mod.v:190$9177'.
     1/28: $6\rx_parity_buf[0:0]
     2/28: $5\rx_parity_buf[0:0]
     3/28: $6\rx_buf[7:0] [7]
     4/28: $6\rx_buf[7:0] [4]
     5/28: $6\rx_buf[7:0] [2]
     6/28: $6\rx_buf[7:0] [0]
     7/28: $6\rx_buf[7:0] [6]
     8/28: $6\rx_buf[7:0] [1]
     9/28: $6\rx_buf[7:0] [3]
    10/28: $6\rx_buf[7:0] [5]
    11/28: $5\rx_buf[7:0]
    12/28: $4\rx_buf[7:0]
    13/28: $4\rx_parity_buf[0:0]
    14/28: $3\rx_parity_buf[0:0]
    15/28: $3\rx_buf[7:0]
    16/28: $2\rx_parity_buf[0:0]
    17/28: $2\rx_buf[7:0]
    18/28: $1\rx_parity_buf[0:0]
    19/28: $1\rx_buf[7:0]
    20/28: $0\symclk_n_reset[0:0]
    21/28: $0\rx_frame_error_start[0:0]
    22/28: $0\sym_count[3:0]
    23/28: $0\rx_data[7:0]
    24/28: $0\rx_irq[0:0]
    25/28: $0\rx_frame_error[0:0]
    26/28: $0\rx_parity_ok[0:0]
    27/28: $0\rx_active[0:0]
    28/28: $0\rx_parity[0:0]
Creating decoders for process `$paramod\uart_tx\DATABITS=8\PARITY_EVEN=1\STOP=1\ACTIVE_LOW=0.$proc$uart_mod.v:322$9171'.
Creating decoders for process `$paramod\uart_tx\DATABITS=8\PARITY_EVEN=1\STOP=1\ACTIVE_LOW=0.$proc$parity_func.v:26$9133'.
Creating decoders for process `$paramod\uart_tx\DATABITS=8\PARITY_EVEN=1\STOP=1\ACTIVE_LOW=0.$proc$uart_mod.v:330$9102'.
     1/6: $0\tx_active[0:0]
     2/6: $0\tx_buf[7:0]
     3/6: $0\tx_r[0:0]
     4/6: $0\tx_irq[0:0]
     5/6: $0\symclk_n_reset[0:0]
     6/6: $0\sym_count[3:0]
Creating decoders for process `\uart_symclk.$proc$uart_mod.v:64$25'.
Creating decoders for process `\uart_symclk.$proc$uart_mod.v:71$16'.
     1/4: $0\symend[0:0]
     2/4: $0\sample[0:0]
     3/4: $0\setup[0:0]
     4/4: $0\count[23:0]
Creating decoders for process `\edge_detect.$proc$edge_detect_mod.v:36$7'.
Creating decoders for process `\sync_signal.$proc$sync_signal_mod.v:34$6'.
Creating decoders for process `\sync_signal.$proc$sync_signal_mod.v:38$1'.

2.3.7. Executing PROC_DLATCH pass (convert process syncs to latches).
No latch inferred for signal `\profibus_phy.$func$\spirx_ctrl_crcerr_get$profibus_phy_mod.v:275$5347$\spirx_ctrl_crcerr_get' from process `\profibus_phy.$proc$profibus_phy_mod.v:592$6275'.
No latch inferred for signal `\profibus_phy.$func$\spirx_ctrl_crcerr_get$profibus_phy_mod.v:275$5375$\spirx_ctrl_crcerr_get' from process `\profibus_phy.$proc$profibus_phy_mod.v:592$6275'.
No latch inferred for signal `\profibus_phy.$func$\rx_buf_overflow_get$profibus_phy_mod.v:275$5346$\rx_buf_overflow_get' from process `\profibus_phy.$proc$profibus_phy_mod.v:366$6271'.
No latch inferred for signal `\profibus_phy.$func$\rx_buf_overflow_get$profibus_phy_mod.v:275$5374$\rx_buf_overflow_get' from process `\profibus_phy.$proc$profibus_phy_mod.v:366$6271'.
No latch inferred for signal `\profibus_phy.$func$\tx_buf_overflow_get$profibus_phy_mod.v:274$5345$\tx_buf_overflow_get' from process `\profibus_phy.$proc$profibus_phy_mod.v:318$6267'.
No latch inferred for signal `\profibus_phy.$func$\tx_buf_overflow_get$profibus_phy_mod.v:274$5373$\tx_buf_overflow_get' from process `\profibus_phy.$proc$profibus_phy_mod.v:318$6267'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.\i' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$proc$block_ram_mod.v:44$8562'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$8042_DATA' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$proc$block_ram_mod.v:44$8562'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$8043_ADDR' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$proc$block_ram_mod.v:44$8562'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$8043_DATA' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$proc$block_ram_mod.v:44$8562'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$8044_DATA' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$proc$block_ram_mod.v:44$8562'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$8045_ADDR' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$proc$block_ram_mod.v:44$8562'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$8045_DATA' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$proc$block_ram_mod.v:44$8562'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$8046_ADDR' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$proc$block_ram_mod.v:44$8562'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$8042_ADDR' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$proc$block_ram_mod.v:44$8562'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$8044_ADDR' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$proc$block_ram_mod.v:44$8562'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$8046_DATA' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$proc$block_ram_mod.v:44$8562'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$8047_ADDR' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$proc$block_ram_mod.v:44$8562'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$8047_DATA' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$proc$block_ram_mod.v:44$8562'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$8048_ADDR' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$proc$block_ram_mod.v:44$8562'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$8048_DATA' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$proc$block_ram_mod.v:44$8562'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$8049_ADDR' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$proc$block_ram_mod.v:44$8562'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$8049_DATA' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$proc$block_ram_mod.v:44$8562'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$8050_ADDR' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$proc$block_ram_mod.v:44$8562'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$8050_DATA' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$proc$block_ram_mod.v:44$8562'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$8051_ADDR' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$proc$block_ram_mod.v:44$8562'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$8051_DATA' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$proc$block_ram_mod.v:44$8562'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$8052_ADDR' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$proc$block_ram_mod.v:44$8562'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$8052_DATA' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$proc$block_ram_mod.v:44$8562'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$8053_ADDR' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$proc$block_ram_mod.v:44$8562'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$8053_DATA' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$proc$block_ram_mod.v:44$8562'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$8054_ADDR' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$proc$block_ram_mod.v:44$8562'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$8054_DATA' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$proc$block_ram_mod.v:44$8562'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$8055_ADDR' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$proc$block_ram_mod.v:44$8562'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$8055_DATA' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$proc$block_ram_mod.v:44$8562'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$8056_ADDR' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$proc$block_ram_mod.v:44$8562'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$8056_DATA' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$proc$block_ram_mod.v:44$8562'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$8057_ADDR' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$proc$block_ram_mod.v:44$8562'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$8057_DATA' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$proc$block_ram_mod.v:44$8562'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$8058_ADDR' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$proc$block_ram_mod.v:44$8562'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$8058_DATA' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$proc$block_ram_mod.v:44$8562'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$8059_ADDR' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$proc$block_ram_mod.v:44$8562'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$8059_DATA' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$proc$block_ram_mod.v:44$8562'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$8060_ADDR' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$proc$block_ram_mod.v:44$8562'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$8060_DATA' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$proc$block_ram_mod.v:44$8562'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$8061_ADDR' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$proc$block_ram_mod.v:44$8562'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$8061_DATA' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$proc$block_ram_mod.v:44$8562'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$8062_ADDR' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$proc$block_ram_mod.v:44$8562'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$8062_DATA' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$proc$block_ram_mod.v:44$8562'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$8063_ADDR' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$proc$block_ram_mod.v:44$8562'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$8063_DATA' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$proc$block_ram_mod.v:44$8562'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$8064_ADDR' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$proc$block_ram_mod.v:44$8562'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$8064_DATA' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$proc$block_ram_mod.v:44$8562'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$8065_ADDR' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$proc$block_ram_mod.v:44$8562'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$8065_DATA' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$proc$block_ram_mod.v:44$8562'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$8066_ADDR' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$proc$block_ram_mod.v:44$8562'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$8066_DATA' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$proc$block_ram_mod.v:44$8562'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$8067_ADDR' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$proc$block_ram_mod.v:44$8562'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$8067_DATA' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$proc$block_ram_mod.v:44$8562'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$8068_ADDR' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$proc$block_ram_mod.v:44$8562'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$8068_DATA' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$proc$block_ram_mod.v:44$8562'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$8069_ADDR' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$proc$block_ram_mod.v:44$8562'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$8069_DATA' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$proc$block_ram_mod.v:44$8562'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$8070_ADDR' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$proc$block_ram_mod.v:44$8562'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$8070_DATA' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$proc$block_ram_mod.v:44$8562'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$8071_ADDR' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$proc$block_ram_mod.v:44$8562'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$8071_DATA' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$proc$block_ram_mod.v:44$8562'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$8072_ADDR' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$proc$block_ram_mod.v:44$8562'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$8072_DATA' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$proc$block_ram_mod.v:44$8562'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$8073_ADDR' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$proc$block_ram_mod.v:44$8562'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$8073_DATA' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$proc$block_ram_mod.v:44$8562'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$8074_ADDR' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$proc$block_ram_mod.v:44$8562'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$8074_DATA' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$proc$block_ram_mod.v:44$8562'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$8075_ADDR' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$proc$block_ram_mod.v:44$8562'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$8075_DATA' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$proc$block_ram_mod.v:44$8562'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$8076_ADDR' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$proc$block_ram_mod.v:44$8562'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$8076_DATA' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$proc$block_ram_mod.v:44$8562'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$8077_ADDR' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$proc$block_ram_mod.v:44$8562'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$8077_DATA' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$proc$block_ram_mod.v:44$8562'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$8078_ADDR' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$proc$block_ram_mod.v:44$8562'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$8078_DATA' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$proc$block_ram_mod.v:44$8562'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$8079_ADDR' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$proc$block_ram_mod.v:44$8562'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$8079_DATA' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$proc$block_ram_mod.v:44$8562'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$8080_ADDR' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$proc$block_ram_mod.v:44$8562'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$8080_DATA' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$proc$block_ram_mod.v:44$8562'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$8081_ADDR' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$proc$block_ram_mod.v:44$8562'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$8081_DATA' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$proc$block_ram_mod.v:44$8562'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$8082_ADDR' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$proc$block_ram_mod.v:44$8562'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$8082_DATA' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$proc$block_ram_mod.v:44$8562'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$8083_ADDR' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$proc$block_ram_mod.v:44$8562'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$8083_DATA' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$proc$block_ram_mod.v:44$8562'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$8084_ADDR' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$proc$block_ram_mod.v:44$8562'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$8084_DATA' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$proc$block_ram_mod.v:44$8562'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$8085_ADDR' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$proc$block_ram_mod.v:44$8562'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$8085_DATA' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$proc$block_ram_mod.v:44$8562'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$8086_ADDR' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$proc$block_ram_mod.v:44$8562'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$8086_DATA' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$proc$block_ram_mod.v:44$8562'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$8087_ADDR' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$proc$block_ram_mod.v:44$8562'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$8087_DATA' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$proc$block_ram_mod.v:44$8562'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$8088_ADDR' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$proc$block_ram_mod.v:44$8562'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$8088_DATA' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$proc$block_ram_mod.v:44$8562'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$8089_ADDR' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$proc$block_ram_mod.v:44$8562'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$8089_DATA' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$proc$block_ram_mod.v:44$8562'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$8090_ADDR' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$proc$block_ram_mod.v:44$8562'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$8090_DATA' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$proc$block_ram_mod.v:44$8562'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$8091_ADDR' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$proc$block_ram_mod.v:44$8562'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$8091_DATA' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$proc$block_ram_mod.v:44$8562'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$8092_ADDR' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$proc$block_ram_mod.v:44$8562'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$8092_DATA' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$proc$block_ram_mod.v:44$8562'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$8093_ADDR' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$proc$block_ram_mod.v:44$8562'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$8093_DATA' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$proc$block_ram_mod.v:44$8562'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$8094_ADDR' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$proc$block_ram_mod.v:44$8562'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$8094_DATA' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$proc$block_ram_mod.v:44$8562'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$8095_ADDR' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$proc$block_ram_mod.v:44$8562'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$8095_DATA' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$proc$block_ram_mod.v:44$8562'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$8096_ADDR' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$proc$block_ram_mod.v:44$8562'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$8096_DATA' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$proc$block_ram_mod.v:44$8562'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$8097_ADDR' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$proc$block_ram_mod.v:44$8562'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$8097_DATA' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$proc$block_ram_mod.v:44$8562'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$8098_ADDR' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$proc$block_ram_mod.v:44$8562'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$8098_DATA' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$proc$block_ram_mod.v:44$8562'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$8099_ADDR' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$proc$block_ram_mod.v:44$8562'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$8099_DATA' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$proc$block_ram_mod.v:44$8562'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$8100_ADDR' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$proc$block_ram_mod.v:44$8562'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$8100_DATA' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$proc$block_ram_mod.v:44$8562'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$8101_ADDR' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$proc$block_ram_mod.v:44$8562'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$8101_DATA' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$proc$block_ram_mod.v:44$8562'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$8102_ADDR' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$proc$block_ram_mod.v:44$8562'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$8102_DATA' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$proc$block_ram_mod.v:44$8562'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$8103_ADDR' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$proc$block_ram_mod.v:44$8562'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$8103_DATA' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$proc$block_ram_mod.v:44$8562'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$8104_ADDR' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$proc$block_ram_mod.v:44$8562'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$8104_DATA' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$proc$block_ram_mod.v:44$8562'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$8105_ADDR' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$proc$block_ram_mod.v:44$8562'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$8105_DATA' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$proc$block_ram_mod.v:44$8562'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$8106_ADDR' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$proc$block_ram_mod.v:44$8562'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$8106_DATA' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$proc$block_ram_mod.v:44$8562'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$8107_ADDR' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$proc$block_ram_mod.v:44$8562'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$8107_DATA' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$proc$block_ram_mod.v:44$8562'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$8108_ADDR' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$proc$block_ram_mod.v:44$8562'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$8108_DATA' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$proc$block_ram_mod.v:44$8562'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$8109_ADDR' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$proc$block_ram_mod.v:44$8562'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$8109_DATA' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$proc$block_ram_mod.v:44$8562'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$8110_ADDR' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$proc$block_ram_mod.v:44$8562'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$8110_DATA' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$proc$block_ram_mod.v:44$8562'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$8111_ADDR' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$proc$block_ram_mod.v:44$8562'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$8111_DATA' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$proc$block_ram_mod.v:44$8562'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$8112_ADDR' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$proc$block_ram_mod.v:44$8562'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$8112_DATA' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$proc$block_ram_mod.v:44$8562'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$8113_ADDR' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$proc$block_ram_mod.v:44$8562'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$8113_DATA' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$proc$block_ram_mod.v:44$8562'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$8114_ADDR' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$proc$block_ram_mod.v:44$8562'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$8114_DATA' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$proc$block_ram_mod.v:44$8562'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$8115_ADDR' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$proc$block_ram_mod.v:44$8562'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$8115_DATA' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$proc$block_ram_mod.v:44$8562'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$8116_ADDR' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$proc$block_ram_mod.v:44$8562'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$8116_DATA' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$proc$block_ram_mod.v:44$8562'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$8117_ADDR' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$proc$block_ram_mod.v:44$8562'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$8117_DATA' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$proc$block_ram_mod.v:44$8562'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$8118_ADDR' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$proc$block_ram_mod.v:44$8562'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$8118_DATA' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$proc$block_ram_mod.v:44$8562'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$8119_ADDR' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$proc$block_ram_mod.v:44$8562'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$8119_DATA' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$proc$block_ram_mod.v:44$8562'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$8120_ADDR' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$proc$block_ram_mod.v:44$8562'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$8120_DATA' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$proc$block_ram_mod.v:44$8562'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$8121_ADDR' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$proc$block_ram_mod.v:44$8562'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$8121_DATA' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$proc$block_ram_mod.v:44$8562'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$8122_ADDR' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$proc$block_ram_mod.v:44$8562'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$8122_DATA' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$proc$block_ram_mod.v:44$8562'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$8123_ADDR' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$proc$block_ram_mod.v:44$8562'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$8123_DATA' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$proc$block_ram_mod.v:44$8562'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$8124_ADDR' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$proc$block_ram_mod.v:44$8562'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$8124_DATA' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$proc$block_ram_mod.v:44$8562'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$8125_ADDR' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$proc$block_ram_mod.v:44$8562'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$8125_DATA' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$proc$block_ram_mod.v:44$8562'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$8126_ADDR' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$proc$block_ram_mod.v:44$8562'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$8126_DATA' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$proc$block_ram_mod.v:44$8562'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$8127_ADDR' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$proc$block_ram_mod.v:44$8562'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$8127_DATA' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$proc$block_ram_mod.v:44$8562'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$8128_ADDR' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$proc$block_ram_mod.v:44$8562'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$8128_DATA' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$proc$block_ram_mod.v:44$8562'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$8129_ADDR' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$proc$block_ram_mod.v:44$8562'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$8129_DATA' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$proc$block_ram_mod.v:44$8562'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$8130_ADDR' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$proc$block_ram_mod.v:44$8562'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$8130_DATA' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$proc$block_ram_mod.v:44$8562'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$8131_ADDR' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$proc$block_ram_mod.v:44$8562'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$8131_DATA' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$proc$block_ram_mod.v:44$8562'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$8132_ADDR' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$proc$block_ram_mod.v:44$8562'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$8132_DATA' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$proc$block_ram_mod.v:44$8562'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$8133_ADDR' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$proc$block_ram_mod.v:44$8562'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$8133_DATA' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$proc$block_ram_mod.v:44$8562'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$8134_ADDR' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$proc$block_ram_mod.v:44$8562'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$8134_DATA' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$proc$block_ram_mod.v:44$8562'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$8135_ADDR' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$proc$block_ram_mod.v:44$8562'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$8135_DATA' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$proc$block_ram_mod.v:44$8562'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$8136_ADDR' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$proc$block_ram_mod.v:44$8562'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$8136_DATA' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$proc$block_ram_mod.v:44$8562'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$8137_ADDR' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$proc$block_ram_mod.v:44$8562'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$8137_DATA' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$proc$block_ram_mod.v:44$8562'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$8138_ADDR' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$proc$block_ram_mod.v:44$8562'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$8138_DATA' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$proc$block_ram_mod.v:44$8562'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$8139_ADDR' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$proc$block_ram_mod.v:44$8562'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$8139_DATA' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$proc$block_ram_mod.v:44$8562'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$8140_ADDR' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$proc$block_ram_mod.v:44$8562'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$8140_DATA' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$proc$block_ram_mod.v:44$8562'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$8141_ADDR' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$proc$block_ram_mod.v:44$8562'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$8141_DATA' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$proc$block_ram_mod.v:44$8562'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$8142_ADDR' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$proc$block_ram_mod.v:44$8562'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$8142_DATA' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$proc$block_ram_mod.v:44$8562'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$8143_ADDR' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$proc$block_ram_mod.v:44$8562'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$8143_DATA' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$proc$block_ram_mod.v:44$8562'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$8144_ADDR' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$proc$block_ram_mod.v:44$8562'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$8144_DATA' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$proc$block_ram_mod.v:44$8562'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$8145_ADDR' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$proc$block_ram_mod.v:44$8562'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$8145_DATA' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$proc$block_ram_mod.v:44$8562'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$8146_ADDR' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$proc$block_ram_mod.v:44$8562'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$8146_DATA' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$proc$block_ram_mod.v:44$8562'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$8147_ADDR' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$proc$block_ram_mod.v:44$8562'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$8147_DATA' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$proc$block_ram_mod.v:44$8562'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$8148_ADDR' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$proc$block_ram_mod.v:44$8562'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$8148_DATA' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$proc$block_ram_mod.v:44$8562'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$8149_ADDR' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$proc$block_ram_mod.v:44$8562'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$8149_DATA' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$proc$block_ram_mod.v:44$8562'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$8150_ADDR' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$proc$block_ram_mod.v:44$8562'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$8150_DATA' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$proc$block_ram_mod.v:44$8562'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$8151_ADDR' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$proc$block_ram_mod.v:44$8562'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$8151_DATA' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$proc$block_ram_mod.v:44$8562'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$8152_ADDR' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$proc$block_ram_mod.v:44$8562'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$8152_DATA' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$proc$block_ram_mod.v:44$8562'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$8153_ADDR' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$proc$block_ram_mod.v:44$8562'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$8153_DATA' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$proc$block_ram_mod.v:44$8562'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$8154_ADDR' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$proc$block_ram_mod.v:44$8562'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$8154_DATA' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$proc$block_ram_mod.v:44$8562'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$8155_ADDR' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$proc$block_ram_mod.v:44$8562'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$8155_DATA' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$proc$block_ram_mod.v:44$8562'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$8156_ADDR' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$proc$block_ram_mod.v:44$8562'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$8156_DATA' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$proc$block_ram_mod.v:44$8562'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$8157_ADDR' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$proc$block_ram_mod.v:44$8562'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$8157_DATA' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$proc$block_ram_mod.v:44$8562'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$8158_ADDR' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$proc$block_ram_mod.v:44$8562'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$8158_DATA' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$proc$block_ram_mod.v:44$8562'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$8159_ADDR' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$proc$block_ram_mod.v:44$8562'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$8159_DATA' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$proc$block_ram_mod.v:44$8562'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$8160_ADDR' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$proc$block_ram_mod.v:44$8562'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$8160_DATA' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$proc$block_ram_mod.v:44$8562'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$8161_ADDR' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$proc$block_ram_mod.v:44$8562'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$8161_DATA' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$proc$block_ram_mod.v:44$8562'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$8162_ADDR' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$proc$block_ram_mod.v:44$8562'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$8162_DATA' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$proc$block_ram_mod.v:44$8562'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$8163_ADDR' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$proc$block_ram_mod.v:44$8562'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$8163_DATA' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$proc$block_ram_mod.v:44$8562'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$8164_ADDR' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$proc$block_ram_mod.v:44$8562'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$8164_DATA' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$proc$block_ram_mod.v:44$8562'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$8165_ADDR' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$proc$block_ram_mod.v:44$8562'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$8165_DATA' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$proc$block_ram_mod.v:44$8562'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$8166_ADDR' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$proc$block_ram_mod.v:44$8562'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$8166_DATA' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$proc$block_ram_mod.v:44$8562'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$8167_ADDR' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$proc$block_ram_mod.v:44$8562'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$8167_DATA' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$proc$block_ram_mod.v:44$8562'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$8168_ADDR' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$proc$block_ram_mod.v:44$8562'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$8168_DATA' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$proc$block_ram_mod.v:44$8562'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$8169_ADDR' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$proc$block_ram_mod.v:44$8562'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$8169_DATA' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$proc$block_ram_mod.v:44$8562'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$8170_ADDR' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$proc$block_ram_mod.v:44$8562'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$8170_DATA' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$proc$block_ram_mod.v:44$8562'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$8171_ADDR' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$proc$block_ram_mod.v:44$8562'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$8171_DATA' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$proc$block_ram_mod.v:44$8562'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$8172_ADDR' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$proc$block_ram_mod.v:44$8562'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$8172_DATA' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$proc$block_ram_mod.v:44$8562'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$8173_ADDR' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$proc$block_ram_mod.v:44$8562'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$8173_DATA' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$proc$block_ram_mod.v:44$8562'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$8174_ADDR' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$proc$block_ram_mod.v:44$8562'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$8174_DATA' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$proc$block_ram_mod.v:44$8562'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$8175_ADDR' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$proc$block_ram_mod.v:44$8562'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$8175_DATA' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$proc$block_ram_mod.v:44$8562'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$8176_ADDR' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$proc$block_ram_mod.v:44$8562'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$8176_DATA' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$proc$block_ram_mod.v:44$8562'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$8177_ADDR' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$proc$block_ram_mod.v:44$8562'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$8177_DATA' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$proc$block_ram_mod.v:44$8562'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$8178_ADDR' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$proc$block_ram_mod.v:44$8562'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$8178_DATA' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$proc$block_ram_mod.v:44$8562'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$8179_ADDR' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$proc$block_ram_mod.v:44$8562'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$8179_DATA' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$proc$block_ram_mod.v:44$8562'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$8180_ADDR' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$proc$block_ram_mod.v:44$8562'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$8180_DATA' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$proc$block_ram_mod.v:44$8562'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$8181_ADDR' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$proc$block_ram_mod.v:44$8562'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$8181_DATA' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$proc$block_ram_mod.v:44$8562'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$8182_ADDR' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$proc$block_ram_mod.v:44$8562'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$8182_DATA' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$proc$block_ram_mod.v:44$8562'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$8183_ADDR' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$proc$block_ram_mod.v:44$8562'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$8183_DATA' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$proc$block_ram_mod.v:44$8562'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$8184_ADDR' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$proc$block_ram_mod.v:44$8562'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$8184_DATA' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$proc$block_ram_mod.v:44$8562'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$8185_ADDR' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$proc$block_ram_mod.v:44$8562'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$8185_DATA' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$proc$block_ram_mod.v:44$8562'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$8186_ADDR' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$proc$block_ram_mod.v:44$8562'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$8186_DATA' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$proc$block_ram_mod.v:44$8562'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$8187_ADDR' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$proc$block_ram_mod.v:44$8562'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$8187_DATA' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$proc$block_ram_mod.v:44$8562'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$8188_ADDR' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$proc$block_ram_mod.v:44$8562'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$8188_DATA' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$proc$block_ram_mod.v:44$8562'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$8189_ADDR' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$proc$block_ram_mod.v:44$8562'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$8189_DATA' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$proc$block_ram_mod.v:44$8562'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$8190_ADDR' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$proc$block_ram_mod.v:44$8562'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$8190_DATA' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$proc$block_ram_mod.v:44$8562'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$8191_ADDR' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$proc$block_ram_mod.v:44$8562'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$8191_DATA' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$proc$block_ram_mod.v:44$8562'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$8192_ADDR' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$proc$block_ram_mod.v:44$8562'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$8192_DATA' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$proc$block_ram_mod.v:44$8562'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$8193_ADDR' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$proc$block_ram_mod.v:44$8562'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$8193_DATA' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$proc$block_ram_mod.v:44$8562'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$8194_ADDR' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$proc$block_ram_mod.v:44$8562'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$8194_DATA' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$proc$block_ram_mod.v:44$8562'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$8195_ADDR' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$proc$block_ram_mod.v:44$8562'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$8195_DATA' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$proc$block_ram_mod.v:44$8562'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$8196_ADDR' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$proc$block_ram_mod.v:44$8562'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$8196_DATA' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$proc$block_ram_mod.v:44$8562'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$8197_ADDR' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$proc$block_ram_mod.v:44$8562'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$8197_DATA' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$proc$block_ram_mod.v:44$8562'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$8198_ADDR' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$proc$block_ram_mod.v:44$8562'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$8198_DATA' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$proc$block_ram_mod.v:44$8562'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$8199_ADDR' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$proc$block_ram_mod.v:44$8562'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$8199_DATA' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$proc$block_ram_mod.v:44$8562'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$8200_ADDR' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$proc$block_ram_mod.v:44$8562'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$8200_DATA' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$proc$block_ram_mod.v:44$8562'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$8201_ADDR' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$proc$block_ram_mod.v:44$8562'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$8201_DATA' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$proc$block_ram_mod.v:44$8562'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$8202_ADDR' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$proc$block_ram_mod.v:44$8562'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$8202_DATA' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$proc$block_ram_mod.v:44$8562'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$8203_ADDR' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$proc$block_ram_mod.v:44$8562'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$8203_DATA' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$proc$block_ram_mod.v:44$8562'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$8204_ADDR' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$proc$block_ram_mod.v:44$8562'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$8204_DATA' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$proc$block_ram_mod.v:44$8562'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$8205_ADDR' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$proc$block_ram_mod.v:44$8562'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$8205_DATA' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$proc$block_ram_mod.v:44$8562'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$8206_ADDR' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$proc$block_ram_mod.v:44$8562'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$8206_DATA' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$proc$block_ram_mod.v:44$8562'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$8207_ADDR' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$proc$block_ram_mod.v:44$8562'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$8207_DATA' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$proc$block_ram_mod.v:44$8562'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$8208_ADDR' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$proc$block_ram_mod.v:44$8562'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$8208_DATA' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$proc$block_ram_mod.v:44$8562'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$8209_ADDR' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$proc$block_ram_mod.v:44$8562'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$8209_DATA' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$proc$block_ram_mod.v:44$8562'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$8210_ADDR' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$proc$block_ram_mod.v:44$8562'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$8210_DATA' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$proc$block_ram_mod.v:44$8562'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$8211_ADDR' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$proc$block_ram_mod.v:44$8562'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$8211_DATA' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$proc$block_ram_mod.v:44$8562'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$8212_ADDR' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$proc$block_ram_mod.v:44$8562'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$8212_DATA' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$proc$block_ram_mod.v:44$8562'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$8213_ADDR' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$proc$block_ram_mod.v:44$8562'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$8213_DATA' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$proc$block_ram_mod.v:44$8562'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$8214_ADDR' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$proc$block_ram_mod.v:44$8562'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$8214_DATA' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$proc$block_ram_mod.v:44$8562'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$8215_ADDR' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$proc$block_ram_mod.v:44$8562'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$8215_DATA' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$proc$block_ram_mod.v:44$8562'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$8216_ADDR' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$proc$block_ram_mod.v:44$8562'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$8216_DATA' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$proc$block_ram_mod.v:44$8562'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$8217_ADDR' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$proc$block_ram_mod.v:44$8562'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$8217_DATA' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$proc$block_ram_mod.v:44$8562'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$8218_ADDR' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$proc$block_ram_mod.v:44$8562'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$8218_DATA' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$proc$block_ram_mod.v:44$8562'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$8219_ADDR' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$proc$block_ram_mod.v:44$8562'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$8219_DATA' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$proc$block_ram_mod.v:44$8562'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$8220_ADDR' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$proc$block_ram_mod.v:44$8562'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$8220_DATA' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$proc$block_ram_mod.v:44$8562'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$8221_ADDR' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$proc$block_ram_mod.v:44$8562'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$8221_DATA' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$proc$block_ram_mod.v:44$8562'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$8222_ADDR' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$proc$block_ram_mod.v:44$8562'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$8222_DATA' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$proc$block_ram_mod.v:44$8562'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$8223_ADDR' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$proc$block_ram_mod.v:44$8562'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$8223_DATA' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$proc$block_ram_mod.v:44$8562'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$8224_ADDR' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$proc$block_ram_mod.v:44$8562'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$8224_DATA' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$proc$block_ram_mod.v:44$8562'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$8225_ADDR' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$proc$block_ram_mod.v:44$8562'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$8225_DATA' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$proc$block_ram_mod.v:44$8562'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$8226_ADDR' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$proc$block_ram_mod.v:44$8562'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$8226_DATA' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$proc$block_ram_mod.v:44$8562'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$8227_ADDR' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$proc$block_ram_mod.v:44$8562'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$8227_DATA' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$proc$block_ram_mod.v:44$8562'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$8228_ADDR' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$proc$block_ram_mod.v:44$8562'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$8228_DATA' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$proc$block_ram_mod.v:44$8562'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$8229_ADDR' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$proc$block_ram_mod.v:44$8562'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$8229_DATA' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$proc$block_ram_mod.v:44$8562'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$8230_ADDR' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$proc$block_ram_mod.v:44$8562'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$8230_DATA' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$proc$block_ram_mod.v:44$8562'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$8231_ADDR' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$proc$block_ram_mod.v:44$8562'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$8231_DATA' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$proc$block_ram_mod.v:44$8562'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$8232_ADDR' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$proc$block_ram_mod.v:44$8562'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$8232_DATA' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$proc$block_ram_mod.v:44$8562'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$8233_ADDR' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$proc$block_ram_mod.v:44$8562'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$8233_DATA' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$proc$block_ram_mod.v:44$8562'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$8234_ADDR' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$proc$block_ram_mod.v:44$8562'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$8234_DATA' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$proc$block_ram_mod.v:44$8562'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$8235_ADDR' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$proc$block_ram_mod.v:44$8562'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$8235_DATA' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$proc$block_ram_mod.v:44$8562'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$8236_ADDR' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$proc$block_ram_mod.v:44$8562'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$8236_DATA' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$proc$block_ram_mod.v:44$8562'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$8237_ADDR' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$proc$block_ram_mod.v:44$8562'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$8237_DATA' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$proc$block_ram_mod.v:44$8562'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$8238_ADDR' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$proc$block_ram_mod.v:44$8562'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$8238_DATA' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$proc$block_ram_mod.v:44$8562'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$8239_ADDR' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$proc$block_ram_mod.v:44$8562'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$8239_DATA' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$proc$block_ram_mod.v:44$8562'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$8240_ADDR' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$proc$block_ram_mod.v:44$8562'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$8240_DATA' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$proc$block_ram_mod.v:44$8562'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$8241_ADDR' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$proc$block_ram_mod.v:44$8562'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$8241_DATA' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$proc$block_ram_mod.v:44$8562'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$8242_ADDR' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$proc$block_ram_mod.v:44$8562'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$8242_DATA' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$proc$block_ram_mod.v:44$8562'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$8243_ADDR' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$proc$block_ram_mod.v:44$8562'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$8243_DATA' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$proc$block_ram_mod.v:44$8562'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$8244_ADDR' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$proc$block_ram_mod.v:44$8562'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$8244_DATA' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$proc$block_ram_mod.v:44$8562'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$8245_ADDR' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$proc$block_ram_mod.v:44$8562'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$8245_DATA' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$proc$block_ram_mod.v:44$8562'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$8246_ADDR' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$proc$block_ram_mod.v:44$8562'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$8246_DATA' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$proc$block_ram_mod.v:44$8562'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$8247_ADDR' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$proc$block_ram_mod.v:44$8562'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$8247_DATA' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$proc$block_ram_mod.v:44$8562'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$8248_ADDR' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$proc$block_ram_mod.v:44$8562'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$8248_DATA' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$proc$block_ram_mod.v:44$8562'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$8249_ADDR' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$proc$block_ram_mod.v:44$8562'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$8249_DATA' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$proc$block_ram_mod.v:44$8562'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$8250_ADDR' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$proc$block_ram_mod.v:44$8562'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$8250_DATA' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$proc$block_ram_mod.v:44$8562'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$8251_ADDR' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$proc$block_ram_mod.v:44$8562'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$8251_DATA' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$proc$block_ram_mod.v:44$8562'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$8252_ADDR' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$proc$block_ram_mod.v:44$8562'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$8252_DATA' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$proc$block_ram_mod.v:44$8562'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$8253_ADDR' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$proc$block_ram_mod.v:44$8562'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$8253_DATA' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$proc$block_ram_mod.v:44$8562'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$8254_ADDR' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$proc$block_ram_mod.v:44$8562'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$8254_DATA' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$proc$block_ram_mod.v:44$8562'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$8255_ADDR' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$proc$block_ram_mod.v:44$8562'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$8255_DATA' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$proc$block_ram_mod.v:44$8562'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$8256_ADDR' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$proc$block_ram_mod.v:44$8562'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$8256_DATA' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$proc$block_ram_mod.v:44$8562'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$8257_ADDR' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$proc$block_ram_mod.v:44$8562'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$8257_DATA' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$proc$block_ram_mod.v:44$8562'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$8258_ADDR' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$proc$block_ram_mod.v:44$8562'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$8258_DATA' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$proc$block_ram_mod.v:44$8562'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$8259_ADDR' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$proc$block_ram_mod.v:44$8562'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$8259_DATA' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$proc$block_ram_mod.v:44$8562'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$8260_ADDR' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$proc$block_ram_mod.v:44$8562'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$8260_DATA' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$proc$block_ram_mod.v:44$8562'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$8261_ADDR' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$proc$block_ram_mod.v:44$8562'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$8261_DATA' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$proc$block_ram_mod.v:44$8562'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$8262_ADDR' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$proc$block_ram_mod.v:44$8562'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$8262_DATA' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$proc$block_ram_mod.v:44$8562'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$8263_ADDR' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$proc$block_ram_mod.v:44$8562'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$8263_DATA' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$proc$block_ram_mod.v:44$8562'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$8264_ADDR' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$proc$block_ram_mod.v:44$8562'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$8264_DATA' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$proc$block_ram_mod.v:44$8562'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$8265_ADDR' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$proc$block_ram_mod.v:44$8562'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$8265_DATA' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$proc$block_ram_mod.v:44$8562'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$8266_ADDR' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$proc$block_ram_mod.v:44$8562'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$8266_DATA' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$proc$block_ram_mod.v:44$8562'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$8267_ADDR' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$proc$block_ram_mod.v:44$8562'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$8267_DATA' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$proc$block_ram_mod.v:44$8562'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$8268_ADDR' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$proc$block_ram_mod.v:44$8562'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$8268_DATA' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$proc$block_ram_mod.v:44$8562'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$8269_ADDR' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$proc$block_ram_mod.v:44$8562'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$8269_DATA' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$proc$block_ram_mod.v:44$8562'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$8270_ADDR' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$proc$block_ram_mod.v:44$8562'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$8270_DATA' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$proc$block_ram_mod.v:44$8562'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$8271_ADDR' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$proc$block_ram_mod.v:44$8562'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$8271_DATA' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$proc$block_ram_mod.v:44$8562'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$8272_ADDR' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$proc$block_ram_mod.v:44$8562'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$8272_DATA' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$proc$block_ram_mod.v:44$8562'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$8273_ADDR' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$proc$block_ram_mod.v:44$8562'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$8273_DATA' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$proc$block_ram_mod.v:44$8562'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$8274_ADDR' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$proc$block_ram_mod.v:44$8562'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$8274_DATA' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$proc$block_ram_mod.v:44$8562'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$8275_ADDR' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$proc$block_ram_mod.v:44$8562'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$8275_DATA' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$proc$block_ram_mod.v:44$8562'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$8276_ADDR' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$proc$block_ram_mod.v:44$8562'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$8276_DATA' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$proc$block_ram_mod.v:44$8562'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$8277_ADDR' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$proc$block_ram_mod.v:44$8562'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$8277_DATA' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$proc$block_ram_mod.v:44$8562'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$8278_ADDR' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$proc$block_ram_mod.v:44$8562'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$8278_DATA' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$proc$block_ram_mod.v:44$8562'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$8279_ADDR' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$proc$block_ram_mod.v:44$8562'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$8279_DATA' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$proc$block_ram_mod.v:44$8562'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$8280_ADDR' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$proc$block_ram_mod.v:44$8562'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$8280_DATA' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$proc$block_ram_mod.v:44$8562'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$8281_ADDR' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$proc$block_ram_mod.v:44$8562'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$8281_DATA' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$proc$block_ram_mod.v:44$8562'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$8282_ADDR' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$proc$block_ram_mod.v:44$8562'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$8282_DATA' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$proc$block_ram_mod.v:44$8562'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$8283_ADDR' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$proc$block_ram_mod.v:44$8562'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$8283_DATA' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$proc$block_ram_mod.v:44$8562'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$8284_ADDR' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$proc$block_ram_mod.v:44$8562'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$8284_DATA' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$proc$block_ram_mod.v:44$8562'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$8285_ADDR' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$proc$block_ram_mod.v:44$8562'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$8285_DATA' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$proc$block_ram_mod.v:44$8562'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$8286_ADDR' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$proc$block_ram_mod.v:44$8562'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$8286_DATA' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$proc$block_ram_mod.v:44$8562'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$8287_ADDR' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$proc$block_ram_mod.v:44$8562'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$8287_DATA' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$proc$block_ram_mod.v:44$8562'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$8288_ADDR' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$proc$block_ram_mod.v:44$8562'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$8288_DATA' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$proc$block_ram_mod.v:44$8562'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$8289_ADDR' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$proc$block_ram_mod.v:44$8562'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$8289_DATA' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$proc$block_ram_mod.v:44$8562'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$8290_ADDR' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$proc$block_ram_mod.v:44$8562'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$8290_DATA' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$proc$block_ram_mod.v:44$8562'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$8291_ADDR' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$proc$block_ram_mod.v:44$8562'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$8291_DATA' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$proc$block_ram_mod.v:44$8562'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$8292_ADDR' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$proc$block_ram_mod.v:44$8562'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$8292_DATA' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$proc$block_ram_mod.v:44$8562'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$8293_ADDR' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$proc$block_ram_mod.v:44$8562'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$8293_DATA' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$proc$block_ram_mod.v:44$8562'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$8294_ADDR' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$proc$block_ram_mod.v:44$8562'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$8294_DATA' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$proc$block_ram_mod.v:44$8562'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$8295_ADDR' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$proc$block_ram_mod.v:44$8562'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$8295_DATA' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$proc$block_ram_mod.v:44$8562'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$8296_ADDR' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$proc$block_ram_mod.v:44$8562'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$8296_DATA' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$proc$block_ram_mod.v:44$8562'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$8297_ADDR' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$proc$block_ram_mod.v:44$8562'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$8297_DATA' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$proc$block_ram_mod.v:44$8562'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.\i' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$proc$block_ram_mod.v:44$7273'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$6753_ADDR' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$proc$block_ram_mod.v:44$7273'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$6756_ADDR' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$proc$block_ram_mod.v:44$7273'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$6754_ADDR' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$proc$block_ram_mod.v:44$7273'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$6754_DATA' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$proc$block_ram_mod.v:44$7273'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$6755_DATA' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$proc$block_ram_mod.v:44$7273'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$6756_DATA' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$proc$block_ram_mod.v:44$7273'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$6757_ADDR' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$proc$block_ram_mod.v:44$7273'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$6753_DATA' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$proc$block_ram_mod.v:44$7273'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$6755_ADDR' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$proc$block_ram_mod.v:44$7273'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$6757_DATA' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$proc$block_ram_mod.v:44$7273'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$6758_ADDR' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$proc$block_ram_mod.v:44$7273'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$6758_DATA' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$proc$block_ram_mod.v:44$7273'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$6759_ADDR' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$proc$block_ram_mod.v:44$7273'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$6759_DATA' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$proc$block_ram_mod.v:44$7273'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$6760_ADDR' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$proc$block_ram_mod.v:44$7273'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$6760_DATA' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$proc$block_ram_mod.v:44$7273'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$6761_ADDR' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$proc$block_ram_mod.v:44$7273'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$6761_DATA' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$proc$block_ram_mod.v:44$7273'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$6762_ADDR' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$proc$block_ram_mod.v:44$7273'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$6762_DATA' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$proc$block_ram_mod.v:44$7273'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$6763_ADDR' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$proc$block_ram_mod.v:44$7273'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$6763_DATA' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$proc$block_ram_mod.v:44$7273'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$6764_ADDR' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$proc$block_ram_mod.v:44$7273'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$6764_DATA' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$proc$block_ram_mod.v:44$7273'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$6765_ADDR' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$proc$block_ram_mod.v:44$7273'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$6765_DATA' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$proc$block_ram_mod.v:44$7273'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$6766_ADDR' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$proc$block_ram_mod.v:44$7273'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$6766_DATA' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$proc$block_ram_mod.v:44$7273'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$6767_ADDR' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$proc$block_ram_mod.v:44$7273'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$6767_DATA' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$proc$block_ram_mod.v:44$7273'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$6768_ADDR' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$proc$block_ram_mod.v:44$7273'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$6768_DATA' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$proc$block_ram_mod.v:44$7273'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$6769_ADDR' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$proc$block_ram_mod.v:44$7273'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$6769_DATA' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$proc$block_ram_mod.v:44$7273'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$6770_ADDR' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$proc$block_ram_mod.v:44$7273'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$6770_DATA' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$proc$block_ram_mod.v:44$7273'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$6771_ADDR' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$proc$block_ram_mod.v:44$7273'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$6771_DATA' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$proc$block_ram_mod.v:44$7273'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$6772_ADDR' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$proc$block_ram_mod.v:44$7273'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$6772_DATA' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$proc$block_ram_mod.v:44$7273'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$6773_ADDR' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$proc$block_ram_mod.v:44$7273'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$6773_DATA' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$proc$block_ram_mod.v:44$7273'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$6774_ADDR' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$proc$block_ram_mod.v:44$7273'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$6774_DATA' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$proc$block_ram_mod.v:44$7273'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$6775_ADDR' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$proc$block_ram_mod.v:44$7273'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$6775_DATA' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$proc$block_ram_mod.v:44$7273'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$6776_ADDR' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$proc$block_ram_mod.v:44$7273'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$6776_DATA' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$proc$block_ram_mod.v:44$7273'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$6777_ADDR' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$proc$block_ram_mod.v:44$7273'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$6777_DATA' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$proc$block_ram_mod.v:44$7273'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$6778_ADDR' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$proc$block_ram_mod.v:44$7273'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$6778_DATA' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$proc$block_ram_mod.v:44$7273'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$6779_ADDR' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$proc$block_ram_mod.v:44$7273'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$6779_DATA' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$proc$block_ram_mod.v:44$7273'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$6780_ADDR' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$proc$block_ram_mod.v:44$7273'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$6780_DATA' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$proc$block_ram_mod.v:44$7273'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$6781_ADDR' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$proc$block_ram_mod.v:44$7273'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$6781_DATA' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$proc$block_ram_mod.v:44$7273'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$6782_ADDR' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$proc$block_ram_mod.v:44$7273'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$6782_DATA' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$proc$block_ram_mod.v:44$7273'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$6783_ADDR' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$proc$block_ram_mod.v:44$7273'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$6783_DATA' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$proc$block_ram_mod.v:44$7273'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$6784_ADDR' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$proc$block_ram_mod.v:44$7273'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$6784_DATA' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$proc$block_ram_mod.v:44$7273'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$6785_ADDR' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$proc$block_ram_mod.v:44$7273'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$6785_DATA' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$proc$block_ram_mod.v:44$7273'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$6786_ADDR' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$proc$block_ram_mod.v:44$7273'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$6786_DATA' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$proc$block_ram_mod.v:44$7273'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$6787_ADDR' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$proc$block_ram_mod.v:44$7273'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$6787_DATA' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$proc$block_ram_mod.v:44$7273'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$6788_ADDR' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$proc$block_ram_mod.v:44$7273'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$6788_DATA' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$proc$block_ram_mod.v:44$7273'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$6789_ADDR' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$proc$block_ram_mod.v:44$7273'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$6789_DATA' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$proc$block_ram_mod.v:44$7273'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$6790_ADDR' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$proc$block_ram_mod.v:44$7273'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$6790_DATA' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$proc$block_ram_mod.v:44$7273'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$6791_ADDR' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$proc$block_ram_mod.v:44$7273'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$6791_DATA' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$proc$block_ram_mod.v:44$7273'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$6792_ADDR' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$proc$block_ram_mod.v:44$7273'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$6792_DATA' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$proc$block_ram_mod.v:44$7273'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$6793_ADDR' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$proc$block_ram_mod.v:44$7273'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$6793_DATA' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$proc$block_ram_mod.v:44$7273'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$6794_ADDR' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$proc$block_ram_mod.v:44$7273'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$6794_DATA' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$proc$block_ram_mod.v:44$7273'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$6795_ADDR' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$proc$block_ram_mod.v:44$7273'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$6795_DATA' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$proc$block_ram_mod.v:44$7273'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$6796_ADDR' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$proc$block_ram_mod.v:44$7273'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$6796_DATA' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$proc$block_ram_mod.v:44$7273'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$6797_ADDR' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$proc$block_ram_mod.v:44$7273'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$6797_DATA' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$proc$block_ram_mod.v:44$7273'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$6798_ADDR' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$proc$block_ram_mod.v:44$7273'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$6798_DATA' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$proc$block_ram_mod.v:44$7273'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$6799_ADDR' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$proc$block_ram_mod.v:44$7273'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$6799_DATA' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$proc$block_ram_mod.v:44$7273'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$6800_ADDR' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$proc$block_ram_mod.v:44$7273'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$6800_DATA' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$proc$block_ram_mod.v:44$7273'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$6801_ADDR' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$proc$block_ram_mod.v:44$7273'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$6801_DATA' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$proc$block_ram_mod.v:44$7273'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$6802_ADDR' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$proc$block_ram_mod.v:44$7273'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$6802_DATA' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$proc$block_ram_mod.v:44$7273'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$6803_ADDR' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$proc$block_ram_mod.v:44$7273'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$6803_DATA' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$proc$block_ram_mod.v:44$7273'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$6804_ADDR' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$proc$block_ram_mod.v:44$7273'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$6804_DATA' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$proc$block_ram_mod.v:44$7273'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$6805_ADDR' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$proc$block_ram_mod.v:44$7273'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$6805_DATA' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$proc$block_ram_mod.v:44$7273'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$6806_ADDR' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$proc$block_ram_mod.v:44$7273'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$6806_DATA' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$proc$block_ram_mod.v:44$7273'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$6807_ADDR' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$proc$block_ram_mod.v:44$7273'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$6807_DATA' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$proc$block_ram_mod.v:44$7273'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$6808_ADDR' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$proc$block_ram_mod.v:44$7273'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$6808_DATA' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$proc$block_ram_mod.v:44$7273'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$6809_ADDR' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$proc$block_ram_mod.v:44$7273'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$6809_DATA' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$proc$block_ram_mod.v:44$7273'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$6810_ADDR' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$proc$block_ram_mod.v:44$7273'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$6810_DATA' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$proc$block_ram_mod.v:44$7273'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$6811_ADDR' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$proc$block_ram_mod.v:44$7273'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$6811_DATA' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$proc$block_ram_mod.v:44$7273'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$6812_ADDR' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$proc$block_ram_mod.v:44$7273'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$6812_DATA' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$proc$block_ram_mod.v:44$7273'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$6813_ADDR' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$proc$block_ram_mod.v:44$7273'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$6813_DATA' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$proc$block_ram_mod.v:44$7273'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$6814_ADDR' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$proc$block_ram_mod.v:44$7273'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$6814_DATA' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$proc$block_ram_mod.v:44$7273'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$6815_ADDR' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$proc$block_ram_mod.v:44$7273'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$6815_DATA' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$proc$block_ram_mod.v:44$7273'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$6816_ADDR' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$proc$block_ram_mod.v:44$7273'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$6816_DATA' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$proc$block_ram_mod.v:44$7273'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$6817_ADDR' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$proc$block_ram_mod.v:44$7273'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$6817_DATA' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$proc$block_ram_mod.v:44$7273'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$6818_ADDR' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$proc$block_ram_mod.v:44$7273'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$6818_DATA' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$proc$block_ram_mod.v:44$7273'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$6819_ADDR' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$proc$block_ram_mod.v:44$7273'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$6819_DATA' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$proc$block_ram_mod.v:44$7273'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$6820_ADDR' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$proc$block_ram_mod.v:44$7273'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$6820_DATA' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$proc$block_ram_mod.v:44$7273'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$6821_ADDR' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$proc$block_ram_mod.v:44$7273'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$6821_DATA' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$proc$block_ram_mod.v:44$7273'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$6822_ADDR' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$proc$block_ram_mod.v:44$7273'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$6822_DATA' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$proc$block_ram_mod.v:44$7273'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$6823_ADDR' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$proc$block_ram_mod.v:44$7273'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$6823_DATA' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$proc$block_ram_mod.v:44$7273'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$6824_ADDR' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$proc$block_ram_mod.v:44$7273'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$6824_DATA' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$proc$block_ram_mod.v:44$7273'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$6825_ADDR' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$proc$block_ram_mod.v:44$7273'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$6825_DATA' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$proc$block_ram_mod.v:44$7273'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$6826_ADDR' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$proc$block_ram_mod.v:44$7273'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$6826_DATA' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$proc$block_ram_mod.v:44$7273'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$6827_ADDR' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$proc$block_ram_mod.v:44$7273'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$6827_DATA' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$proc$block_ram_mod.v:44$7273'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$6828_ADDR' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$proc$block_ram_mod.v:44$7273'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$6828_DATA' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$proc$block_ram_mod.v:44$7273'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$6829_ADDR' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$proc$block_ram_mod.v:44$7273'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$6829_DATA' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$proc$block_ram_mod.v:44$7273'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$6830_ADDR' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$proc$block_ram_mod.v:44$7273'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$6830_DATA' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$proc$block_ram_mod.v:44$7273'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$6831_ADDR' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$proc$block_ram_mod.v:44$7273'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$6831_DATA' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$proc$block_ram_mod.v:44$7273'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$6832_ADDR' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$proc$block_ram_mod.v:44$7273'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$6832_DATA' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$proc$block_ram_mod.v:44$7273'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$6833_ADDR' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$proc$block_ram_mod.v:44$7273'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$6833_DATA' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$proc$block_ram_mod.v:44$7273'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$6834_ADDR' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$proc$block_ram_mod.v:44$7273'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$6834_DATA' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$proc$block_ram_mod.v:44$7273'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$6835_ADDR' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$proc$block_ram_mod.v:44$7273'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$6835_DATA' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$proc$block_ram_mod.v:44$7273'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$6836_ADDR' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$proc$block_ram_mod.v:44$7273'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$6836_DATA' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$proc$block_ram_mod.v:44$7273'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$6837_ADDR' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$proc$block_ram_mod.v:44$7273'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$6837_DATA' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$proc$block_ram_mod.v:44$7273'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$6838_ADDR' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$proc$block_ram_mod.v:44$7273'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$6838_DATA' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$proc$block_ram_mod.v:44$7273'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$6839_ADDR' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$proc$block_ram_mod.v:44$7273'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$6839_DATA' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$proc$block_ram_mod.v:44$7273'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$6840_ADDR' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$proc$block_ram_mod.v:44$7273'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$6840_DATA' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$proc$block_ram_mod.v:44$7273'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$6841_ADDR' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$proc$block_ram_mod.v:44$7273'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$6841_DATA' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$proc$block_ram_mod.v:44$7273'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$6842_ADDR' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$proc$block_ram_mod.v:44$7273'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$6842_DATA' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$proc$block_ram_mod.v:44$7273'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$6843_ADDR' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$proc$block_ram_mod.v:44$7273'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$6843_DATA' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$proc$block_ram_mod.v:44$7273'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$6844_ADDR' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$proc$block_ram_mod.v:44$7273'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$6844_DATA' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$proc$block_ram_mod.v:44$7273'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$6845_ADDR' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$proc$block_ram_mod.v:44$7273'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$6845_DATA' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$proc$block_ram_mod.v:44$7273'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$6846_ADDR' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$proc$block_ram_mod.v:44$7273'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$6846_DATA' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$proc$block_ram_mod.v:44$7273'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$6847_ADDR' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$proc$block_ram_mod.v:44$7273'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$6847_DATA' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$proc$block_ram_mod.v:44$7273'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$6848_ADDR' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$proc$block_ram_mod.v:44$7273'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$6848_DATA' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$proc$block_ram_mod.v:44$7273'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$6849_ADDR' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$proc$block_ram_mod.v:44$7273'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$6849_DATA' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$proc$block_ram_mod.v:44$7273'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$6850_ADDR' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$proc$block_ram_mod.v:44$7273'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$6850_DATA' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$proc$block_ram_mod.v:44$7273'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$6851_ADDR' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$proc$block_ram_mod.v:44$7273'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$6851_DATA' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$proc$block_ram_mod.v:44$7273'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$6852_ADDR' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$proc$block_ram_mod.v:44$7273'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$6852_DATA' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$proc$block_ram_mod.v:44$7273'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$6853_ADDR' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$proc$block_ram_mod.v:44$7273'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$6853_DATA' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$proc$block_ram_mod.v:44$7273'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$6854_ADDR' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$proc$block_ram_mod.v:44$7273'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$6854_DATA' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$proc$block_ram_mod.v:44$7273'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$6855_ADDR' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$proc$block_ram_mod.v:44$7273'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$6855_DATA' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$proc$block_ram_mod.v:44$7273'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$6856_ADDR' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$proc$block_ram_mod.v:44$7273'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$6856_DATA' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$proc$block_ram_mod.v:44$7273'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$6857_ADDR' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$proc$block_ram_mod.v:44$7273'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$6857_DATA' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$proc$block_ram_mod.v:44$7273'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$6858_ADDR' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$proc$block_ram_mod.v:44$7273'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$6858_DATA' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$proc$block_ram_mod.v:44$7273'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$6859_ADDR' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$proc$block_ram_mod.v:44$7273'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$6859_DATA' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$proc$block_ram_mod.v:44$7273'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$6860_ADDR' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$proc$block_ram_mod.v:44$7273'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$6860_DATA' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$proc$block_ram_mod.v:44$7273'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$6861_ADDR' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$proc$block_ram_mod.v:44$7273'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$6861_DATA' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$proc$block_ram_mod.v:44$7273'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$6862_ADDR' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$proc$block_ram_mod.v:44$7273'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$6862_DATA' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$proc$block_ram_mod.v:44$7273'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$6863_ADDR' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$proc$block_ram_mod.v:44$7273'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$6863_DATA' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$proc$block_ram_mod.v:44$7273'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$6864_ADDR' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$proc$block_ram_mod.v:44$7273'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$6864_DATA' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$proc$block_ram_mod.v:44$7273'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$6865_ADDR' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$proc$block_ram_mod.v:44$7273'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$6865_DATA' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$proc$block_ram_mod.v:44$7273'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$6866_ADDR' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$proc$block_ram_mod.v:44$7273'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$6866_DATA' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$proc$block_ram_mod.v:44$7273'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$6867_ADDR' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$proc$block_ram_mod.v:44$7273'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$6867_DATA' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$proc$block_ram_mod.v:44$7273'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$6868_ADDR' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$proc$block_ram_mod.v:44$7273'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$6868_DATA' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$proc$block_ram_mod.v:44$7273'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$6869_ADDR' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$proc$block_ram_mod.v:44$7273'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$6869_DATA' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$proc$block_ram_mod.v:44$7273'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$6870_ADDR' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$proc$block_ram_mod.v:44$7273'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$6870_DATA' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$proc$block_ram_mod.v:44$7273'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$6871_ADDR' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$proc$block_ram_mod.v:44$7273'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$6871_DATA' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$proc$block_ram_mod.v:44$7273'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$6872_ADDR' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$proc$block_ram_mod.v:44$7273'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$6872_DATA' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$proc$block_ram_mod.v:44$7273'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$6873_ADDR' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$proc$block_ram_mod.v:44$7273'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$6873_DATA' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$proc$block_ram_mod.v:44$7273'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$6874_ADDR' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$proc$block_ram_mod.v:44$7273'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$6874_DATA' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$proc$block_ram_mod.v:44$7273'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$6875_ADDR' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$proc$block_ram_mod.v:44$7273'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$6875_DATA' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$proc$block_ram_mod.v:44$7273'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$6876_ADDR' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$proc$block_ram_mod.v:44$7273'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$6876_DATA' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$proc$block_ram_mod.v:44$7273'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$6877_ADDR' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$proc$block_ram_mod.v:44$7273'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$6877_DATA' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$proc$block_ram_mod.v:44$7273'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$6878_ADDR' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$proc$block_ram_mod.v:44$7273'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$6878_DATA' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$proc$block_ram_mod.v:44$7273'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$6879_ADDR' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$proc$block_ram_mod.v:44$7273'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$6879_DATA' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$proc$block_ram_mod.v:44$7273'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$6880_ADDR' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$proc$block_ram_mod.v:44$7273'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$6880_DATA' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$proc$block_ram_mod.v:44$7273'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$6881_ADDR' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$proc$block_ram_mod.v:44$7273'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$6881_DATA' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$proc$block_ram_mod.v:44$7273'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$6882_ADDR' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$proc$block_ram_mod.v:44$7273'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$6882_DATA' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$proc$block_ram_mod.v:44$7273'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$6883_ADDR' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$proc$block_ram_mod.v:44$7273'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$6883_DATA' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$proc$block_ram_mod.v:44$7273'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$6884_ADDR' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$proc$block_ram_mod.v:44$7273'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$6884_DATA' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$proc$block_ram_mod.v:44$7273'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$6885_ADDR' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$proc$block_ram_mod.v:44$7273'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$6885_DATA' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$proc$block_ram_mod.v:44$7273'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$6886_ADDR' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$proc$block_ram_mod.v:44$7273'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$6886_DATA' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$proc$block_ram_mod.v:44$7273'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$6887_ADDR' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$proc$block_ram_mod.v:44$7273'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$6887_DATA' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$proc$block_ram_mod.v:44$7273'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$6888_ADDR' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$proc$block_ram_mod.v:44$7273'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$6888_DATA' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$proc$block_ram_mod.v:44$7273'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$6889_ADDR' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$proc$block_ram_mod.v:44$7273'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$6889_DATA' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$proc$block_ram_mod.v:44$7273'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$6890_ADDR' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$proc$block_ram_mod.v:44$7273'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$6890_DATA' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$proc$block_ram_mod.v:44$7273'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$6891_ADDR' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$proc$block_ram_mod.v:44$7273'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$6891_DATA' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$proc$block_ram_mod.v:44$7273'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$6892_ADDR' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$proc$block_ram_mod.v:44$7273'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$6892_DATA' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$proc$block_ram_mod.v:44$7273'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$6893_ADDR' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$proc$block_ram_mod.v:44$7273'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$6893_DATA' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$proc$block_ram_mod.v:44$7273'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$6894_ADDR' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$proc$block_ram_mod.v:44$7273'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$6894_DATA' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$proc$block_ram_mod.v:44$7273'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$6895_ADDR' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$proc$block_ram_mod.v:44$7273'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$6895_DATA' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$proc$block_ram_mod.v:44$7273'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$6896_ADDR' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$proc$block_ram_mod.v:44$7273'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$6896_DATA' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$proc$block_ram_mod.v:44$7273'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$6897_ADDR' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$proc$block_ram_mod.v:44$7273'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$6897_DATA' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$proc$block_ram_mod.v:44$7273'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$6898_ADDR' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$proc$block_ram_mod.v:44$7273'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$6898_DATA' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$proc$block_ram_mod.v:44$7273'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$6899_ADDR' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$proc$block_ram_mod.v:44$7273'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$6899_DATA' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$proc$block_ram_mod.v:44$7273'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$6900_ADDR' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$proc$block_ram_mod.v:44$7273'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$6900_DATA' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$proc$block_ram_mod.v:44$7273'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$6901_ADDR' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$proc$block_ram_mod.v:44$7273'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$6901_DATA' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$proc$block_ram_mod.v:44$7273'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$6902_ADDR' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$proc$block_ram_mod.v:44$7273'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$6902_DATA' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$proc$block_ram_mod.v:44$7273'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$6903_ADDR' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$proc$block_ram_mod.v:44$7273'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$6903_DATA' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$proc$block_ram_mod.v:44$7273'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$6904_ADDR' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$proc$block_ram_mod.v:44$7273'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$6904_DATA' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$proc$block_ram_mod.v:44$7273'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$6905_ADDR' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$proc$block_ram_mod.v:44$7273'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$6905_DATA' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$proc$block_ram_mod.v:44$7273'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$6906_ADDR' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$proc$block_ram_mod.v:44$7273'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$6906_DATA' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$proc$block_ram_mod.v:44$7273'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$6907_ADDR' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$proc$block_ram_mod.v:44$7273'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$6907_DATA' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$proc$block_ram_mod.v:44$7273'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$6908_ADDR' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$proc$block_ram_mod.v:44$7273'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$6908_DATA' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$proc$block_ram_mod.v:44$7273'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$6909_ADDR' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$proc$block_ram_mod.v:44$7273'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$6909_DATA' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$proc$block_ram_mod.v:44$7273'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$6910_ADDR' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$proc$block_ram_mod.v:44$7273'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$6910_DATA' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$proc$block_ram_mod.v:44$7273'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$6911_ADDR' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$proc$block_ram_mod.v:44$7273'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$6911_DATA' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$proc$block_ram_mod.v:44$7273'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$6912_ADDR' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$proc$block_ram_mod.v:44$7273'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$6912_DATA' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$proc$block_ram_mod.v:44$7273'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$6913_ADDR' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$proc$block_ram_mod.v:44$7273'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$6913_DATA' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$proc$block_ram_mod.v:44$7273'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$6914_ADDR' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$proc$block_ram_mod.v:44$7273'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$6914_DATA' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$proc$block_ram_mod.v:44$7273'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$6915_ADDR' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$proc$block_ram_mod.v:44$7273'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$6915_DATA' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$proc$block_ram_mod.v:44$7273'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$6916_ADDR' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$proc$block_ram_mod.v:44$7273'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$6916_DATA' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$proc$block_ram_mod.v:44$7273'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$6917_ADDR' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$proc$block_ram_mod.v:44$7273'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$6917_DATA' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$proc$block_ram_mod.v:44$7273'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$6918_ADDR' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$proc$block_ram_mod.v:44$7273'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$6918_DATA' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$proc$block_ram_mod.v:44$7273'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$6919_ADDR' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$proc$block_ram_mod.v:44$7273'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$6919_DATA' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$proc$block_ram_mod.v:44$7273'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$6920_ADDR' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$proc$block_ram_mod.v:44$7273'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$6920_DATA' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$proc$block_ram_mod.v:44$7273'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$6921_ADDR' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$proc$block_ram_mod.v:44$7273'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$6921_DATA' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$proc$block_ram_mod.v:44$7273'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$6922_ADDR' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$proc$block_ram_mod.v:44$7273'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$6922_DATA' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$proc$block_ram_mod.v:44$7273'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$6923_ADDR' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$proc$block_ram_mod.v:44$7273'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$6923_DATA' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$proc$block_ram_mod.v:44$7273'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$6924_ADDR' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$proc$block_ram_mod.v:44$7273'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$6924_DATA' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$proc$block_ram_mod.v:44$7273'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$6925_ADDR' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$proc$block_ram_mod.v:44$7273'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$6925_DATA' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$proc$block_ram_mod.v:44$7273'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$6926_ADDR' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$proc$block_ram_mod.v:44$7273'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$6926_DATA' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$proc$block_ram_mod.v:44$7273'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$6927_ADDR' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$proc$block_ram_mod.v:44$7273'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$6927_DATA' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$proc$block_ram_mod.v:44$7273'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$6928_ADDR' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$proc$block_ram_mod.v:44$7273'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$6928_DATA' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$proc$block_ram_mod.v:44$7273'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$6929_ADDR' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$proc$block_ram_mod.v:44$7273'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$6929_DATA' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$proc$block_ram_mod.v:44$7273'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$6930_ADDR' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$proc$block_ram_mod.v:44$7273'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$6930_DATA' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$proc$block_ram_mod.v:44$7273'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$6931_ADDR' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$proc$block_ram_mod.v:44$7273'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$6931_DATA' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$proc$block_ram_mod.v:44$7273'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$6932_ADDR' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$proc$block_ram_mod.v:44$7273'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$6932_DATA' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$proc$block_ram_mod.v:44$7273'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$6933_ADDR' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$proc$block_ram_mod.v:44$7273'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$6933_DATA' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$proc$block_ram_mod.v:44$7273'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$6934_ADDR' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$proc$block_ram_mod.v:44$7273'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$6934_DATA' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$proc$block_ram_mod.v:44$7273'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$6935_ADDR' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$proc$block_ram_mod.v:44$7273'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$6935_DATA' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$proc$block_ram_mod.v:44$7273'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$6936_ADDR' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$proc$block_ram_mod.v:44$7273'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$6936_DATA' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$proc$block_ram_mod.v:44$7273'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$6937_ADDR' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$proc$block_ram_mod.v:44$7273'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$6937_DATA' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$proc$block_ram_mod.v:44$7273'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$6938_ADDR' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$proc$block_ram_mod.v:44$7273'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$6938_DATA' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$proc$block_ram_mod.v:44$7273'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$6939_ADDR' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$proc$block_ram_mod.v:44$7273'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$6939_DATA' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$proc$block_ram_mod.v:44$7273'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$6940_ADDR' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$proc$block_ram_mod.v:44$7273'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$6940_DATA' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$proc$block_ram_mod.v:44$7273'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$6941_ADDR' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$proc$block_ram_mod.v:44$7273'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$6941_DATA' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$proc$block_ram_mod.v:44$7273'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$6942_ADDR' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$proc$block_ram_mod.v:44$7273'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$6942_DATA' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$proc$block_ram_mod.v:44$7273'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$6943_ADDR' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$proc$block_ram_mod.v:44$7273'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$6943_DATA' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$proc$block_ram_mod.v:44$7273'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$6944_ADDR' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$proc$block_ram_mod.v:44$7273'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$6944_DATA' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$proc$block_ram_mod.v:44$7273'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$6945_ADDR' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$proc$block_ram_mod.v:44$7273'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$6945_DATA' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$proc$block_ram_mod.v:44$7273'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$6946_ADDR' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$proc$block_ram_mod.v:44$7273'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$6946_DATA' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$proc$block_ram_mod.v:44$7273'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$6947_ADDR' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$proc$block_ram_mod.v:44$7273'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$6947_DATA' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$proc$block_ram_mod.v:44$7273'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$6948_ADDR' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$proc$block_ram_mod.v:44$7273'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$6948_DATA' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$proc$block_ram_mod.v:44$7273'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$6949_ADDR' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$proc$block_ram_mod.v:44$7273'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$6949_DATA' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$proc$block_ram_mod.v:44$7273'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$6950_ADDR' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$proc$block_ram_mod.v:44$7273'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$6950_DATA' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$proc$block_ram_mod.v:44$7273'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$6951_ADDR' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$proc$block_ram_mod.v:44$7273'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$6951_DATA' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$proc$block_ram_mod.v:44$7273'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$6952_ADDR' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$proc$block_ram_mod.v:44$7273'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$6952_DATA' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$proc$block_ram_mod.v:44$7273'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$6953_ADDR' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$proc$block_ram_mod.v:44$7273'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$6953_DATA' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$proc$block_ram_mod.v:44$7273'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$6954_ADDR' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$proc$block_ram_mod.v:44$7273'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$6954_DATA' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$proc$block_ram_mod.v:44$7273'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$6955_ADDR' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$proc$block_ram_mod.v:44$7273'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$6955_DATA' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$proc$block_ram_mod.v:44$7273'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$6956_ADDR' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$proc$block_ram_mod.v:44$7273'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$6956_DATA' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$proc$block_ram_mod.v:44$7273'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$6957_ADDR' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$proc$block_ram_mod.v:44$7273'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$6957_DATA' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$proc$block_ram_mod.v:44$7273'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$6958_ADDR' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$proc$block_ram_mod.v:44$7273'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$6958_DATA' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$proc$block_ram_mod.v:44$7273'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$6959_ADDR' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$proc$block_ram_mod.v:44$7273'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$6959_DATA' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$proc$block_ram_mod.v:44$7273'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$6960_ADDR' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$proc$block_ram_mod.v:44$7273'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$6960_DATA' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$proc$block_ram_mod.v:44$7273'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$6961_ADDR' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$proc$block_ram_mod.v:44$7273'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$6961_DATA' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$proc$block_ram_mod.v:44$7273'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$6962_ADDR' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$proc$block_ram_mod.v:44$7273'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$6962_DATA' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$proc$block_ram_mod.v:44$7273'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$6963_ADDR' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$proc$block_ram_mod.v:44$7273'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$6963_DATA' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$proc$block_ram_mod.v:44$7273'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$6964_ADDR' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$proc$block_ram_mod.v:44$7273'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$6964_DATA' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$proc$block_ram_mod.v:44$7273'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$6965_ADDR' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$proc$block_ram_mod.v:44$7273'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$6965_DATA' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$proc$block_ram_mod.v:44$7273'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$6966_ADDR' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$proc$block_ram_mod.v:44$7273'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$6966_DATA' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$proc$block_ram_mod.v:44$7273'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$6967_ADDR' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$proc$block_ram_mod.v:44$7273'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$6967_DATA' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$proc$block_ram_mod.v:44$7273'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$6968_ADDR' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$proc$block_ram_mod.v:44$7273'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$6968_DATA' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$proc$block_ram_mod.v:44$7273'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$6969_ADDR' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$proc$block_ram_mod.v:44$7273'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$6969_DATA' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$proc$block_ram_mod.v:44$7273'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$6970_ADDR' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$proc$block_ram_mod.v:44$7273'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$6970_DATA' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$proc$block_ram_mod.v:44$7273'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$6971_ADDR' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$proc$block_ram_mod.v:44$7273'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$6971_DATA' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$proc$block_ram_mod.v:44$7273'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$6972_ADDR' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$proc$block_ram_mod.v:44$7273'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$6972_DATA' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$proc$block_ram_mod.v:44$7273'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$6973_ADDR' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$proc$block_ram_mod.v:44$7273'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$6973_DATA' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$proc$block_ram_mod.v:44$7273'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$6974_ADDR' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$proc$block_ram_mod.v:44$7273'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$6974_DATA' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$proc$block_ram_mod.v:44$7273'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$6975_ADDR' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$proc$block_ram_mod.v:44$7273'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$6975_DATA' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$proc$block_ram_mod.v:44$7273'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$6976_ADDR' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$proc$block_ram_mod.v:44$7273'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$6976_DATA' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$proc$block_ram_mod.v:44$7273'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$6977_ADDR' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$proc$block_ram_mod.v:44$7273'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$6977_DATA' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$proc$block_ram_mod.v:44$7273'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$6978_ADDR' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$proc$block_ram_mod.v:44$7273'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$6978_DATA' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$proc$block_ram_mod.v:44$7273'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$6979_ADDR' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$proc$block_ram_mod.v:44$7273'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$6979_DATA' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$proc$block_ram_mod.v:44$7273'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$6980_ADDR' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$proc$block_ram_mod.v:44$7273'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$6980_DATA' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$proc$block_ram_mod.v:44$7273'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$6981_ADDR' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$proc$block_ram_mod.v:44$7273'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$6981_DATA' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$proc$block_ram_mod.v:44$7273'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$6982_ADDR' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$proc$block_ram_mod.v:44$7273'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$6982_DATA' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$proc$block_ram_mod.v:44$7273'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$6983_ADDR' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$proc$block_ram_mod.v:44$7273'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$6983_DATA' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$proc$block_ram_mod.v:44$7273'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$6984_ADDR' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$proc$block_ram_mod.v:44$7273'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$6984_DATA' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$proc$block_ram_mod.v:44$7273'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$6985_ADDR' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$proc$block_ram_mod.v:44$7273'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$6985_DATA' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$proc$block_ram_mod.v:44$7273'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$6986_ADDR' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$proc$block_ram_mod.v:44$7273'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$6986_DATA' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$proc$block_ram_mod.v:44$7273'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$6987_ADDR' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$proc$block_ram_mod.v:44$7273'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$6987_DATA' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$proc$block_ram_mod.v:44$7273'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$6988_ADDR' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$proc$block_ram_mod.v:44$7273'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$6988_DATA' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$proc$block_ram_mod.v:44$7273'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$6989_ADDR' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$proc$block_ram_mod.v:44$7273'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$6989_DATA' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$proc$block_ram_mod.v:44$7273'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$6990_ADDR' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$proc$block_ram_mod.v:44$7273'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$6990_DATA' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$proc$block_ram_mod.v:44$7273'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$6991_ADDR' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$proc$block_ram_mod.v:44$7273'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$6991_DATA' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$proc$block_ram_mod.v:44$7273'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$6992_ADDR' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$proc$block_ram_mod.v:44$7273'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$6992_DATA' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$proc$block_ram_mod.v:44$7273'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$6993_ADDR' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$proc$block_ram_mod.v:44$7273'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$6993_DATA' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$proc$block_ram_mod.v:44$7273'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$6994_ADDR' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$proc$block_ram_mod.v:44$7273'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$6994_DATA' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$proc$block_ram_mod.v:44$7273'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$6995_ADDR' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$proc$block_ram_mod.v:44$7273'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$6995_DATA' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$proc$block_ram_mod.v:44$7273'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$6996_ADDR' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$proc$block_ram_mod.v:44$7273'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$6996_DATA' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$proc$block_ram_mod.v:44$7273'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$6997_ADDR' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$proc$block_ram_mod.v:44$7273'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$6997_DATA' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$proc$block_ram_mod.v:44$7273'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$6998_ADDR' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$proc$block_ram_mod.v:44$7273'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$6998_DATA' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$proc$block_ram_mod.v:44$7273'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$6999_ADDR' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$proc$block_ram_mod.v:44$7273'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$6999_DATA' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$proc$block_ram_mod.v:44$7273'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$7000_ADDR' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$proc$block_ram_mod.v:44$7273'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$7000_DATA' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$proc$block_ram_mod.v:44$7273'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$7001_ADDR' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$proc$block_ram_mod.v:44$7273'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$7001_DATA' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$proc$block_ram_mod.v:44$7273'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$7002_ADDR' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$proc$block_ram_mod.v:44$7273'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$7002_DATA' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$proc$block_ram_mod.v:44$7273'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$7003_ADDR' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$proc$block_ram_mod.v:44$7273'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$7003_DATA' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$proc$block_ram_mod.v:44$7273'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$7004_ADDR' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$proc$block_ram_mod.v:44$7273'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$7004_DATA' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$proc$block_ram_mod.v:44$7273'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$7005_ADDR' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$proc$block_ram_mod.v:44$7273'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$7005_DATA' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$proc$block_ram_mod.v:44$7273'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$7006_ADDR' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$proc$block_ram_mod.v:44$7273'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$7006_DATA' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$proc$block_ram_mod.v:44$7273'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$7007_ADDR' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$proc$block_ram_mod.v:44$7273'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$7007_DATA' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$proc$block_ram_mod.v:44$7273'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$7008_ADDR' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$proc$block_ram_mod.v:44$7273'.
No latch inferred for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:46$7008_DATA' from process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$proc$block_ram_mod.v:44$7273'.
No latch inferred for signal `$paramod\uart_rx\DATABITS=8\PARITY_EVEN=1\ACTIVE_LOW=0.$func$\parity9$uart_mod.v:164$9173$\d' from process `$paramod\uart_rx\DATABITS=8\PARITY_EVEN=1\ACTIVE_LOW=0.$proc$parity_func.v:26$9207'.
No latch inferred for signal `$paramod\uart_rx\DATABITS=8\PARITY_EVEN=1\ACTIVE_LOW=0.$func$\parity9$uart_mod.v:164$9173$\parity9' from process `$paramod\uart_rx\DATABITS=8\PARITY_EVEN=1\ACTIVE_LOW=0.$proc$parity_func.v:26$9207'.
No latch inferred for signal `$paramod\uart_rx\DATABITS=8\PARITY_EVEN=1\ACTIVE_LOW=0.$func$\parity9$uart_mod.v:164$9173$\odd' from process `$paramod\uart_rx\DATABITS=8\PARITY_EVEN=1\ACTIVE_LOW=0.$proc$parity_func.v:26$9207'.
No latch inferred for signal `$paramod\uart_rx\DATABITS=8\PARITY_EVEN=1\ACTIVE_LOW=0.$func$\parity9$uart_mod.v:164$9173$\a' from process `$paramod\uart_rx\DATABITS=8\PARITY_EVEN=1\ACTIVE_LOW=0.$proc$parity_func.v:26$9207'.
No latch inferred for signal `$paramod\uart_rx\DATABITS=8\PARITY_EVEN=1\ACTIVE_LOW=0.$func$\parity9$uart_mod.v:164$9173$\c' from process `$paramod\uart_rx\DATABITS=8\PARITY_EVEN=1\ACTIVE_LOW=0.$proc$parity_func.v:26$9207'.
No latch inferred for signal `$paramod\uart_rx\DATABITS=8\PARITY_EVEN=1\ACTIVE_LOW=0.$func$\parity9$uart_mod.v:164$9173$\e' from process `$paramod\uart_rx\DATABITS=8\PARITY_EVEN=1\ACTIVE_LOW=0.$proc$parity_func.v:26$9207'.
No latch inferred for signal `$paramod\uart_rx\DATABITS=8\PARITY_EVEN=1\ACTIVE_LOW=0.$func$\parity9$uart_mod.v:164$9173$\f' from process `$paramod\uart_rx\DATABITS=8\PARITY_EVEN=1\ACTIVE_LOW=0.$proc$parity_func.v:26$9207'.
No latch inferred for signal `$paramod\uart_rx\DATABITS=8\PARITY_EVEN=1\ACTIVE_LOW=0.$func$\parity9$uart_mod.v:164$9172$\parity9' from process `$paramod\uart_rx\DATABITS=8\PARITY_EVEN=1\ACTIVE_LOW=0.$proc$parity_func.v:26$9207'.
No latch inferred for signal `$paramod\uart_rx\DATABITS=8\PARITY_EVEN=1\ACTIVE_LOW=0.$func$\parity9$uart_mod.v:164$9173$\b' from process `$paramod\uart_rx\DATABITS=8\PARITY_EVEN=1\ACTIVE_LOW=0.$proc$parity_func.v:26$9207'.
No latch inferred for signal `$paramod\uart_rx\DATABITS=8\PARITY_EVEN=1\ACTIVE_LOW=0.$func$\parity9$uart_mod.v:164$9173$\g' from process `$paramod\uart_rx\DATABITS=8\PARITY_EVEN=1\ACTIVE_LOW=0.$proc$parity_func.v:26$9207'.
No latch inferred for signal `$paramod\uart_rx\DATABITS=8\PARITY_EVEN=1\ACTIVE_LOW=0.$func$\parity9$uart_mod.v:164$9173$\h' from process `$paramod\uart_rx\DATABITS=8\PARITY_EVEN=1\ACTIVE_LOW=0.$proc$parity_func.v:26$9207'.
No latch inferred for signal `$paramod\uart_rx\DATABITS=8\PARITY_EVEN=1\ACTIVE_LOW=0.$func$\parity9$uart_mod.v:164$9173$\i' from process `$paramod\uart_rx\DATABITS=8\PARITY_EVEN=1\ACTIVE_LOW=0.$proc$parity_func.v:26$9207'.
No latch inferred for signal `$paramod\uart_tx\DATABITS=8\PARITY_EVEN=1\STOP=1\ACTIVE_LOW=0.$func$\parity9$uart_mod.v:311$9098$\parity9' from process `$paramod\uart_tx\DATABITS=8\PARITY_EVEN=1\STOP=1\ACTIVE_LOW=0.$proc$parity_func.v:26$9133'.
No latch inferred for signal `$paramod\uart_tx\DATABITS=8\PARITY_EVEN=1\STOP=1\ACTIVE_LOW=0.$func$\parity9$uart_mod.v:311$9098$\odd' from process `$paramod\uart_tx\DATABITS=8\PARITY_EVEN=1\STOP=1\ACTIVE_LOW=0.$proc$parity_func.v:26$9133'.
No latch inferred for signal `$paramod\uart_tx\DATABITS=8\PARITY_EVEN=1\STOP=1\ACTIVE_LOW=0.$func$\parity9$uart_mod.v:311$9098$\a' from process `$paramod\uart_tx\DATABITS=8\PARITY_EVEN=1\STOP=1\ACTIVE_LOW=0.$proc$parity_func.v:26$9133'.
No latch inferred for signal `$paramod\uart_tx\DATABITS=8\PARITY_EVEN=1\STOP=1\ACTIVE_LOW=0.$func$\parity9$uart_mod.v:311$9098$\c' from process `$paramod\uart_tx\DATABITS=8\PARITY_EVEN=1\STOP=1\ACTIVE_LOW=0.$proc$parity_func.v:26$9133'.
No latch inferred for signal `$paramod\uart_tx\DATABITS=8\PARITY_EVEN=1\STOP=1\ACTIVE_LOW=0.$func$\parity9$uart_mod.v:311$9098$\d' from process `$paramod\uart_tx\DATABITS=8\PARITY_EVEN=1\STOP=1\ACTIVE_LOW=0.$proc$parity_func.v:26$9133'.
No latch inferred for signal `$paramod\uart_tx\DATABITS=8\PARITY_EVEN=1\STOP=1\ACTIVE_LOW=0.$func$\parity9$uart_mod.v:311$9098$\e' from process `$paramod\uart_tx\DATABITS=8\PARITY_EVEN=1\STOP=1\ACTIVE_LOW=0.$proc$parity_func.v:26$9133'.
No latch inferred for signal `$paramod\uart_tx\DATABITS=8\PARITY_EVEN=1\STOP=1\ACTIVE_LOW=0.$func$\parity9$uart_mod.v:311$9098$\f' from process `$paramod\uart_tx\DATABITS=8\PARITY_EVEN=1\STOP=1\ACTIVE_LOW=0.$proc$parity_func.v:26$9133'.
No latch inferred for signal `$paramod\uart_tx\DATABITS=8\PARITY_EVEN=1\STOP=1\ACTIVE_LOW=0.$func$\parity9$uart_mod.v:311$9097$\parity9' from process `$paramod\uart_tx\DATABITS=8\PARITY_EVEN=1\STOP=1\ACTIVE_LOW=0.$proc$parity_func.v:26$9133'.
No latch inferred for signal `$paramod\uart_tx\DATABITS=8\PARITY_EVEN=1\STOP=1\ACTIVE_LOW=0.$func$\parity9$uart_mod.v:311$9098$\b' from process `$paramod\uart_tx\DATABITS=8\PARITY_EVEN=1\STOP=1\ACTIVE_LOW=0.$proc$parity_func.v:26$9133'.
No latch inferred for signal `$paramod\uart_tx\DATABITS=8\PARITY_EVEN=1\STOP=1\ACTIVE_LOW=0.$func$\parity9$uart_mod.v:311$9098$\g' from process `$paramod\uart_tx\DATABITS=8\PARITY_EVEN=1\STOP=1\ACTIVE_LOW=0.$proc$parity_func.v:26$9133'.
No latch inferred for signal `$paramod\uart_tx\DATABITS=8\PARITY_EVEN=1\STOP=1\ACTIVE_LOW=0.$func$\parity9$uart_mod.v:311$9098$\h' from process `$paramod\uart_tx\DATABITS=8\PARITY_EVEN=1\STOP=1\ACTIVE_LOW=0.$proc$parity_func.v:26$9133'.
No latch inferred for signal `$paramod\uart_tx\DATABITS=8\PARITY_EVEN=1\STOP=1\ACTIVE_LOW=0.$func$\parity9$uart_mod.v:311$9098$\i' from process `$paramod\uart_tx\DATABITS=8\PARITY_EVEN=1\STOP=1\ACTIVE_LOW=0.$proc$parity_func.v:26$9133'.

2.3.8. Executing PROC_DFF pass (convert process syncs to FFs).
Creating register for signal `$paramod\led_blink\BLINK_ON_CLKS=2400000\BLINK_OFF_CLKS=685714.\led' using process `$paramod\led_blink\BLINK_ON_CLKS=2400000\BLINK_OFF_CLKS=685714.$proc$led_blink_mod.v:44$9246'.
  created $dff cell `$procdff$15659' with positive edge clock.
Creating register for signal `$paramod\led_blink\BLINK_ON_CLKS=2400000\BLINK_OFF_CLKS=685714.\led_on_count' using process `$paramod\led_blink\BLINK_ON_CLKS=2400000\BLINK_OFF_CLKS=685714.$proc$led_blink_mod.v:44$9246'.
  created $dff cell `$procdff$15660' with positive edge clock.
Creating register for signal `$paramod\led_blink\BLINK_ON_CLKS=2400000\BLINK_OFF_CLKS=685714.\led_off_count' using process `$paramod\led_blink\BLINK_ON_CLKS=2400000\BLINK_OFF_CLKS=685714.$proc$led_blink_mod.v:44$9246'.
  created $dff cell `$procdff$15661' with positive edge clock.
Creating register for signal `\profibus_phy.\timer_idle_active' using process `\profibus_phy.$proc$profibus_phy_mod.v:1046$6259'.
  created $dff cell `$procdff$15662' with positive edge clock.
Creating register for signal `\profibus_phy.\timer_idle' using process `\profibus_phy.$proc$profibus_phy_mod.v:1046$6259'.
  created $dff cell `$procdff$15663' with positive edge clock.
Creating register for signal `\profibus_phy.\timer_idle_saved' using process `\profibus_phy.$proc$profibus_phy_mod.v:1046$6259'.
  created $dff cell `$procdff$15664' with positive edge clock.
Creating register for signal `\profibus_phy.\rx_buf_rd_addr' using process `\profibus_phy.$proc$profibus_phy_mod.v:881$5661'.
  created $dff cell `$procdff$15665' with positive edge clock.
Creating register for signal `\profibus_phy.\spi_tx_data' using process `\profibus_phy.$proc$profibus_phy_mod.v:881$5661'.
  created $dff cell `$procdff$15666' with positive edge clock.
Creating register for signal `\profibus_phy.\spitx_ctrl_pending_ack' using process `\profibus_phy.$proc$profibus_phy_mod.v:881$5661'.
  created $dff cell `$procdff$15667' with positive edge clock.
Creating register for signal `\profibus_phy.\spitx_bytecount' using process `\profibus_phy.$proc$profibus_phy_mod.v:881$5661'.
  created $dff cell `$procdff$15668' with positive edge clock.
Creating register for signal `\profibus_phy.\spitx_len' using process `\profibus_phy.$proc$profibus_phy_mod.v:881$5661'.
  created $dff cell `$procdff$15669' with positive edge clock.
Creating register for signal `\profibus_phy.\spitx_tail' using process `\profibus_phy.$proc$profibus_phy_mod.v:881$5661'.
  created $dff cell `$procdff$15670' with positive edge clock.
Creating register for signal `\profibus_phy.\spitx_ctrl_running' using process `\profibus_phy.$proc$profibus_phy_mod.v:881$5661'.
  created $dff cell `$procdff$15671' with positive edge clock.
Creating register for signal `\profibus_phy.\spitx_data_running' using process `\profibus_phy.$proc$profibus_phy_mod.v:881$5661'.
  created $dff cell `$procdff$15672' with positive edge clock.
Creating register for signal `\profibus_phy.\spitx_crc' using process `\profibus_phy.$proc$profibus_phy_mod.v:881$5661'.
  created $dff cell `$procdff$15673' with positive edge clock.
Creating register for signal `\profibus_phy.$func$\parity8$profibus_phy_mod.v:902$5364$\parity8' using process `\profibus_phy.$proc$profibus_phy_mod.v:881$5661'.
  created $dff cell `$procdff$15674' with positive edge clock.
Creating register for signal `\profibus_phy.$func$\parity8$profibus_phy_mod.v:902$5364$\odd' using process `\profibus_phy.$proc$profibus_phy_mod.v:881$5661'.
  created $dff cell `$procdff$15675' with positive edge clock.
Creating register for signal `\profibus_phy.$func$\parity8$profibus_phy_mod.v:902$5364$\a' using process `\profibus_phy.$proc$profibus_phy_mod.v:881$5661'.
  created $dff cell `$procdff$15676' with positive edge clock.
Creating register for signal `\profibus_phy.$func$\parity8$profibus_phy_mod.v:902$5364$\b' using process `\profibus_phy.$proc$profibus_phy_mod.v:881$5661'.
  created $dff cell `$procdff$15677' with positive edge clock.
Creating register for signal `\profibus_phy.$func$\parity8$profibus_phy_mod.v:902$5364$\c' using process `\profibus_phy.$proc$profibus_phy_mod.v:881$5661'.
  created $dff cell `$procdff$15678' with positive edge clock.
Creating register for signal `\profibus_phy.$func$\parity8$profibus_phy_mod.v:902$5364$\d' using process `\profibus_phy.$proc$profibus_phy_mod.v:881$5661'.
  created $dff cell `$procdff$15679' with positive edge clock.
Creating register for signal `\profibus_phy.$func$\parity8$profibus_phy_mod.v:902$5364$\e' using process `\profibus_phy.$proc$profibus_phy_mod.v:881$5661'.
  created $dff cell `$procdff$15680' with positive edge clock.
Creating register for signal `\profibus_phy.$func$\parity8$profibus_phy_mod.v:902$5364$\f' using process `\profibus_phy.$proc$profibus_phy_mod.v:881$5661'.
  created $dff cell `$procdff$15681' with positive edge clock.
Creating register for signal `\profibus_phy.$func$\parity8$profibus_phy_mod.v:902$5364$\g' using process `\profibus_phy.$proc$profibus_phy_mod.v:881$5661'.
  created $dff cell `$procdff$15682' with positive edge clock.
Creating register for signal `\profibus_phy.$func$\parity8$profibus_phy_mod.v:902$5364$\h' using process `\profibus_phy.$proc$profibus_phy_mod.v:881$5661'.
  created $dff cell `$procdff$15683' with positive edge clock.
Creating register for signal `\profibus_phy.$func$\parity9$parity_func.v:55$5365$\parity9' using process `\profibus_phy.$proc$profibus_phy_mod.v:881$5661'.
  created $dff cell `$procdff$15684' with positive edge clock.
Creating register for signal `\profibus_phy.$func$\parity9$parity_func.v:55$5365$\odd' using process `\profibus_phy.$proc$profibus_phy_mod.v:881$5661'.
  created $dff cell `$procdff$15685' with positive edge clock.
Creating register for signal `\profibus_phy.$func$\parity9$parity_func.v:55$5365$\a' using process `\profibus_phy.$proc$profibus_phy_mod.v:881$5661'.
  created $dff cell `$procdff$15686' with positive edge clock.
Creating register for signal `\profibus_phy.$func$\parity9$parity_func.v:55$5365$\b' using process `\profibus_phy.$proc$profibus_phy_mod.v:881$5661'.
  created $dff cell `$procdff$15687' with positive edge clock.
Creating register for signal `\profibus_phy.$func$\parity9$parity_func.v:55$5365$\c' using process `\profibus_phy.$proc$profibus_phy_mod.v:881$5661'.
  created $dff cell `$procdff$15688' with positive edge clock.
Creating register for signal `\profibus_phy.$func$\parity9$parity_func.v:55$5365$\d' using process `\profibus_phy.$proc$profibus_phy_mod.v:881$5661'.
  created $dff cell `$procdff$15689' with positive edge clock.
Creating register for signal `\profibus_phy.$func$\parity9$parity_func.v:55$5365$\e' using process `\profibus_phy.$proc$profibus_phy_mod.v:881$5661'.
  created $dff cell `$procdff$15690' with positive edge clock.
Creating register for signal `\profibus_phy.$func$\parity9$parity_func.v:55$5365$\f' using process `\profibus_phy.$proc$profibus_phy_mod.v:881$5661'.
  created $dff cell `$procdff$15691' with positive edge clock.
Creating register for signal `\profibus_phy.$func$\parity9$parity_func.v:55$5365$\g' using process `\profibus_phy.$proc$profibus_phy_mod.v:881$5661'.
  created $dff cell `$procdff$15692' with positive edge clock.
Creating register for signal `\profibus_phy.$func$\parity9$parity_func.v:55$5365$\h' using process `\profibus_phy.$proc$profibus_phy_mod.v:881$5661'.
  created $dff cell `$procdff$15693' with positive edge clock.
Creating register for signal `\profibus_phy.$func$\parity9$parity_func.v:55$5365$\i' using process `\profibus_phy.$proc$profibus_phy_mod.v:881$5661'.
  created $dff cell `$procdff$15694' with positive edge clock.
Creating register for signal `\profibus_phy.$func$\crc8$profibus_phy_mod.v:916$5366$\crc8' using process `\profibus_phy.$proc$profibus_phy_mod.v:881$5661'.
  created $dff cell `$procdff$15695' with positive edge clock.
Creating register for signal `\profibus_phy.$func$\crc8$profibus_phy_mod.v:916$5366$\crcIn' using process `\profibus_phy.$proc$profibus_phy_mod.v:881$5661'.
  created $dff cell `$procdff$15696' with positive edge clock.
Creating register for signal `\profibus_phy.$func$\crc8$profibus_phy_mod.v:916$5366$\data' using process `\profibus_phy.$proc$profibus_phy_mod.v:881$5661'.
  created $dff cell `$procdff$15697' with positive edge clock.
Creating register for signal `\profibus_phy.$func$\crc8$profibus_phy_mod.v:922$5367$\crc8' using process `\profibus_phy.$proc$profibus_phy_mod.v:881$5661'.
  created $dff cell `$procdff$15698' with positive edge clock.
Creating register for signal `\profibus_phy.$func$\crc8$profibus_phy_mod.v:922$5367$\crcIn' using process `\profibus_phy.$proc$profibus_phy_mod.v:881$5661'.
  created $dff cell `$procdff$15699' with positive edge clock.
Creating register for signal `\profibus_phy.$func$\crc8$profibus_phy_mod.v:922$5367$\data' using process `\profibus_phy.$proc$profibus_phy_mod.v:881$5661'.
  created $dff cell `$procdff$15700' with positive edge clock.
Creating register for signal `\profibus_phy.$func$\crc8$profibus_phy_mod.v:928$5368$\crc8' using process `\profibus_phy.$proc$profibus_phy_mod.v:881$5661'.
  created $dff cell `$procdff$15701' with positive edge clock.
Creating register for signal `\profibus_phy.$func$\crc8$profibus_phy_mod.v:928$5368$\crcIn' using process `\profibus_phy.$proc$profibus_phy_mod.v:881$5661'.
  created $dff cell `$procdff$15702' with positive edge clock.
Creating register for signal `\profibus_phy.$func$\crc8$profibus_phy_mod.v:928$5368$\data' using process `\profibus_phy.$proc$profibus_phy_mod.v:881$5661'.
  created $dff cell `$procdff$15703' with positive edge clock.
Creating register for signal `\profibus_phy.$func$\crc8$profibus_phy_mod.v:934$5369$\crc8' using process `\profibus_phy.$proc$profibus_phy_mod.v:881$5661'.
  created $dff cell `$procdff$15704' with positive edge clock.
Creating register for signal `\profibus_phy.$func$\crc8$profibus_phy_mod.v:934$5369$\crcIn' using process `\profibus_phy.$proc$profibus_phy_mod.v:881$5661'.
  created $dff cell `$procdff$15705' with positive edge clock.
Creating register for signal `\profibus_phy.$func$\crc8$profibus_phy_mod.v:934$5369$\data' using process `\profibus_phy.$proc$profibus_phy_mod.v:881$5661'.
  created $dff cell `$procdff$15706' with positive edge clock.
Creating register for signal `\profibus_phy.$func$\crc8$profibus_phy_mod.v:940$5370$\crc8' using process `\profibus_phy.$proc$profibus_phy_mod.v:881$5661'.
  created $dff cell `$procdff$15707' with positive edge clock.
Creating register for signal `\profibus_phy.$func$\crc8$profibus_phy_mod.v:940$5370$\crcIn' using process `\profibus_phy.$proc$profibus_phy_mod.v:881$5661'.
  created $dff cell `$procdff$15708' with positive edge clock.
Creating register for signal `\profibus_phy.$func$\crc8$profibus_phy_mod.v:940$5370$\data' using process `\profibus_phy.$proc$profibus_phy_mod.v:881$5661'.
  created $dff cell `$procdff$15709' with positive edge clock.
Creating register for signal `\profibus_phy.$func$\parity8$profibus_phy_mod.v:978$5371$\parity8' using process `\profibus_phy.$proc$profibus_phy_mod.v:881$5661'.
  created $dff cell `$procdff$15710' with positive edge clock.
Creating register for signal `\profibus_phy.$func$\parity8$profibus_phy_mod.v:978$5371$\odd' using process `\profibus_phy.$proc$profibus_phy_mod.v:881$5661'.
  created $dff cell `$procdff$15711' with positive edge clock.
Creating register for signal `\profibus_phy.$func$\parity8$profibus_phy_mod.v:978$5371$\a' using process `\profibus_phy.$proc$profibus_phy_mod.v:881$5661'.
  created $dff cell `$procdff$15712' with positive edge clock.
Creating register for signal `\profibus_phy.$func$\parity8$profibus_phy_mod.v:978$5371$\b' using process `\profibus_phy.$proc$profibus_phy_mod.v:881$5661'.
  created $dff cell `$procdff$15713' with positive edge clock.
Creating register for signal `\profibus_phy.$func$\parity8$profibus_phy_mod.v:978$5371$\c' using process `\profibus_phy.$proc$profibus_phy_mod.v:881$5661'.
  created $dff cell `$procdff$15714' with positive edge clock.
Creating register for signal `\profibus_phy.$func$\parity8$profibus_phy_mod.v:978$5371$\d' using process `\profibus_phy.$proc$profibus_phy_mod.v:881$5661'.
  created $dff cell `$procdff$15715' with positive edge clock.
Creating register for signal `\profibus_phy.$func$\parity8$profibus_phy_mod.v:978$5371$\e' using process `\profibus_phy.$proc$profibus_phy_mod.v:881$5661'.
  created $dff cell `$procdff$15716' with positive edge clock.
Creating register for signal `\profibus_phy.$func$\parity8$profibus_phy_mod.v:978$5371$\f' using process `\profibus_phy.$proc$profibus_phy_mod.v:881$5661'.
  created $dff cell `$procdff$15717' with positive edge clock.
Creating register for signal `\profibus_phy.$func$\parity8$profibus_phy_mod.v:978$5371$\g' using process `\profibus_phy.$proc$profibus_phy_mod.v:881$5661'.
  created $dff cell `$procdff$15718' with positive edge clock.
Creating register for signal `\profibus_phy.$func$\parity8$profibus_phy_mod.v:978$5371$\h' using process `\profibus_phy.$proc$profibus_phy_mod.v:881$5661'.
  created $dff cell `$procdff$15719' with positive edge clock.
Creating register for signal `\profibus_phy.$func$\parity9$parity_func.v:55$5372$\parity9' using process `\profibus_phy.$proc$profibus_phy_mod.v:881$5661'.
  created $dff cell `$procdff$15720' with positive edge clock.
Creating register for signal `\profibus_phy.$func$\parity9$parity_func.v:55$5372$\odd' using process `\profibus_phy.$proc$profibus_phy_mod.v:881$5661'.
  created $dff cell `$procdff$15721' with positive edge clock.
Creating register for signal `\profibus_phy.$func$\parity9$parity_func.v:55$5372$\a' using process `\profibus_phy.$proc$profibus_phy_mod.v:881$5661'.
  created $dff cell `$procdff$15722' with positive edge clock.
Creating register for signal `\profibus_phy.$func$\parity9$parity_func.v:55$5372$\b' using process `\profibus_phy.$proc$profibus_phy_mod.v:881$5661'.
  created $dff cell `$procdff$15723' with positive edge clock.
Creating register for signal `\profibus_phy.$func$\parity9$parity_func.v:55$5372$\c' using process `\profibus_phy.$proc$profibus_phy_mod.v:881$5661'.
  created $dff cell `$procdff$15724' with positive edge clock.
Creating register for signal `\profibus_phy.$func$\parity9$parity_func.v:55$5372$\d' using process `\profibus_phy.$proc$profibus_phy_mod.v:881$5661'.
  created $dff cell `$procdff$15725' with positive edge clock.
Creating register for signal `\profibus_phy.$func$\parity9$parity_func.v:55$5372$\e' using process `\profibus_phy.$proc$profibus_phy_mod.v:881$5661'.
  created $dff cell `$procdff$15726' with positive edge clock.
Creating register for signal `\profibus_phy.$func$\parity9$parity_func.v:55$5372$\f' using process `\profibus_phy.$proc$profibus_phy_mod.v:881$5661'.
  created $dff cell `$procdff$15727' with positive edge clock.
Creating register for signal `\profibus_phy.$func$\parity9$parity_func.v:55$5372$\g' using process `\profibus_phy.$proc$profibus_phy_mod.v:881$5661'.
  created $dff cell `$procdff$15728' with positive edge clock.
Creating register for signal `\profibus_phy.$func$\parity9$parity_func.v:55$5372$\h' using process `\profibus_phy.$proc$profibus_phy_mod.v:881$5661'.
  created $dff cell `$procdff$15729' with positive edge clock.
Creating register for signal `\profibus_phy.$func$\parity9$parity_func.v:55$5372$\i' using process `\profibus_phy.$proc$profibus_phy_mod.v:881$5661'.
  created $dff cell `$procdff$15730' with positive edge clock.
Creating register for signal `\profibus_phy.\n_poweronreset_status' using process `\profibus_phy.$proc$profibus_phy_mod.v:604$5408'.
  created $dff cell `$procdff$15731' with positive edge clock.
Creating register for signal `\profibus_phy.\n_hardreset_status' using process `\profibus_phy.$proc$profibus_phy_mod.v:604$5408'.
  created $dff cell `$procdff$15732' with positive edge clock.
Creating register for signal `\profibus_phy.\softreset_status' using process `\profibus_phy.$proc$profibus_phy_mod.v:604$5408'.
  created $dff cell `$procdff$15733' with positive edge clock.
Creating register for signal `\profibus_phy.\softreset' using process `\profibus_phy.$proc$profibus_phy_mod.v:604$5408'.
  created $dff cell `$procdff$15734' with positive edge clock.
Creating register for signal `\profibus_phy.\tx_buf_wr_addr' using process `\profibus_phy.$proc$profibus_phy_mod.v:604$5408'.
  created $dff cell `$procdff$15735' with positive edge clock.
Creating register for signal `\profibus_phy.\tx_buf_wr_data' using process `\profibus_phy.$proc$profibus_phy_mod.v:604$5408'.
  created $dff cell `$procdff$15736' with positive edge clock.
Creating register for signal `\profibus_phy.\tx_buf_wr' using process `\profibus_phy.$proc$profibus_phy_mod.v:604$5408'.
  created $dff cell `$procdff$15737' with positive edge clock.
Creating register for signal `\profibus_phy.\tx_buf_overflow' using process `\profibus_phy.$proc$profibus_phy_mod.v:604$5408'.
  created $dff cell `$procdff$15738' with positive edge clock.
Creating register for signal `\profibus_phy.\rx_buf_overflow [1]' using process `\profibus_phy.$proc$profibus_phy_mod.v:604$5408'.
  created $dff cell `$procdff$15739' with positive edge clock.
Creating register for signal `\profibus_phy.\uart_clks_per_sym' using process `\profibus_phy.$proc$profibus_phy_mod.v:604$5408'.
  created $dff cell `$procdff$15740' with positive edge clock.
Creating register for signal `\profibus_phy.\tsyn_clks' using process `\profibus_phy.$proc$profibus_phy_mod.v:604$5408'.
  created $dff cell `$procdff$15741' with positive edge clock.
Creating register for signal `\profibus_phy.\spirx_state' using process `\profibus_phy.$proc$profibus_phy_mod.v:604$5408'.
  created $dff cell `$procdff$15742' with positive edge clock.
Creating register for signal `\profibus_phy.\spirx_len' using process `\profibus_phy.$proc$profibus_phy_mod.v:604$5408'.
  created $dff cell `$procdff$15743' with positive edge clock.
Creating register for signal `\profibus_phy.\spirx_len_valid' using process `\profibus_phy.$proc$profibus_phy_mod.v:604$5408'.
  created $dff cell `$procdff$15744' with positive edge clock.
Creating register for signal `\profibus_phy.\spirx_bytecount' using process `\profibus_phy.$proc$profibus_phy_mod.v:604$5408'.
  created $dff cell `$procdff$15745' with positive edge clock.
Creating register for signal `\profibus_phy.\spirx_ctrl' using process `\profibus_phy.$proc$profibus_phy_mod.v:604$5408'.
  created $dff cell `$procdff$15746' with positive edge clock.
Creating register for signal `\profibus_phy.\spirx_ctrl_data' using process `\profibus_phy.$proc$profibus_phy_mod.v:604$5408'.
  created $dff cell `$procdff$15747' with positive edge clock.
Creating register for signal `\profibus_phy.\spirx_crc' using process `\profibus_phy.$proc$profibus_phy_mod.v:604$5408'.
  created $dff cell `$procdff$15748' with positive edge clock.
Creating register for signal `\profibus_phy.\spirx_ctrl_crcerr' using process `\profibus_phy.$proc$profibus_phy_mod.v:604$5408'.
  created $dff cell `$procdff$15749' with positive edge clock.
Creating register for signal `\profibus_phy.\spirx_lencalc_n_reset' using process `\profibus_phy.$proc$profibus_phy_mod.v:604$5408'.
  created $dff cell `$procdff$15750' with positive edge clock.
Creating register for signal `\profibus_phy.\spirx_lencalc_byte' using process `\profibus_phy.$proc$profibus_phy_mod.v:604$5408'.
  created $dff cell `$procdff$15751' with positive edge clock.
Creating register for signal `\profibus_phy.\spirx_lencalc_new' using process `\profibus_phy.$proc$profibus_phy_mod.v:604$5408'.
  created $dff cell `$procdff$15752' with positive edge clock.
Creating register for signal `\profibus_phy.\spitx_ctrl_reply' using process `\profibus_phy.$proc$profibus_phy_mod.v:604$5408'.
  created $dff cell `$procdff$15753' with positive edge clock.
Creating register for signal `\profibus_phy.\spitx_ctrl_reply_data' using process `\profibus_phy.$proc$profibus_phy_mod.v:604$5408'.
  created $dff cell `$procdff$15754' with positive edge clock.
Creating register for signal `\profibus_phy.\spitx_ctrl_pending' using process `\profibus_phy.$proc$profibus_phy_mod.v:604$5408'.
  created $dff cell `$procdff$15755' with positive edge clock.
Creating register for signal `\profibus_phy.$func$\parity8$profibus_phy_mod.v:631$5349$\parity8' using process `\profibus_phy.$proc$profibus_phy_mod.v:604$5408'.
  created $dff cell `$procdff$15756' with positive edge clock.
Creating register for signal `\profibus_phy.$func$\parity8$profibus_phy_mod.v:631$5349$\odd' using process `\profibus_phy.$proc$profibus_phy_mod.v:604$5408'.
  created $dff cell `$procdff$15757' with positive edge clock.
Creating register for signal `\profibus_phy.$func$\parity8$profibus_phy_mod.v:631$5349$\a' using process `\profibus_phy.$proc$profibus_phy_mod.v:604$5408'.
  created $dff cell `$procdff$15758' with positive edge clock.
Creating register for signal `\profibus_phy.$func$\parity8$profibus_phy_mod.v:631$5349$\b' using process `\profibus_phy.$proc$profibus_phy_mod.v:604$5408'.
  created $dff cell `$procdff$15759' with positive edge clock.
Creating register for signal `\profibus_phy.$func$\parity8$profibus_phy_mod.v:631$5349$\c' using process `\profibus_phy.$proc$profibus_phy_mod.v:604$5408'.
  created $dff cell `$procdff$15760' with positive edge clock.
Creating register for signal `\profibus_phy.$func$\parity8$profibus_phy_mod.v:631$5349$\d' using process `\profibus_phy.$proc$profibus_phy_mod.v:604$5408'.
  created $dff cell `$procdff$15761' with positive edge clock.
Creating register for signal `\profibus_phy.$func$\parity8$profibus_phy_mod.v:631$5349$\e' using process `\profibus_phy.$proc$profibus_phy_mod.v:604$5408'.
  created $dff cell `$procdff$15762' with positive edge clock.
Creating register for signal `\profibus_phy.$func$\parity8$profibus_phy_mod.v:631$5349$\f' using process `\profibus_phy.$proc$profibus_phy_mod.v:604$5408'.
  created $dff cell `$procdff$15763' with positive edge clock.
Creating register for signal `\profibus_phy.$func$\parity8$profibus_phy_mod.v:631$5349$\g' using process `\profibus_phy.$proc$profibus_phy_mod.v:604$5408'.
  created $dff cell `$procdff$15764' with positive edge clock.
Creating register for signal `\profibus_phy.$func$\parity8$profibus_phy_mod.v:631$5349$\h' using process `\profibus_phy.$proc$profibus_phy_mod.v:604$5408'.
  created $dff cell `$procdff$15765' with positive edge clock.
Creating register for signal `\profibus_phy.$func$\parity9$parity_func.v:55$5350$\parity9' using process `\profibus_phy.$proc$profibus_phy_mod.v:604$5408'.
  created $dff cell `$procdff$15766' with positive edge clock.
Creating register for signal `\profibus_phy.$func$\parity9$parity_func.v:55$5350$\odd' using process `\profibus_phy.$proc$profibus_phy_mod.v:604$5408'.
  created $dff cell `$procdff$15767' with positive edge clock.
Creating register for signal `\profibus_phy.$func$\parity9$parity_func.v:55$5350$\a' using process `\profibus_phy.$proc$profibus_phy_mod.v:604$5408'.
  created $dff cell `$procdff$15768' with positive edge clock.
Creating register for signal `\profibus_phy.$func$\parity9$parity_func.v:55$5350$\b' using process `\profibus_phy.$proc$profibus_phy_mod.v:604$5408'.
  created $dff cell `$procdff$15769' with positive edge clock.
Creating register for signal `\profibus_phy.$func$\parity9$parity_func.v:55$5350$\c' using process `\profibus_phy.$proc$profibus_phy_mod.v:604$5408'.
  created $dff cell `$procdff$15770' with positive edge clock.
Creating register for signal `\profibus_phy.$func$\parity9$parity_func.v:55$5350$\d' using process `\profibus_phy.$proc$profibus_phy_mod.v:604$5408'.
  created $dff cell `$procdff$15771' with positive edge clock.
Creating register for signal `\profibus_phy.$func$\parity9$parity_func.v:55$5350$\e' using process `\profibus_phy.$proc$profibus_phy_mod.v:604$5408'.
  created $dff cell `$procdff$15772' with positive edge clock.
Creating register for signal `\profibus_phy.$func$\parity9$parity_func.v:55$5350$\f' using process `\profibus_phy.$proc$profibus_phy_mod.v:604$5408'.
  created $dff cell `$procdff$15773' with positive edge clock.
Creating register for signal `\profibus_phy.$func$\parity9$parity_func.v:55$5350$\g' using process `\profibus_phy.$proc$profibus_phy_mod.v:604$5408'.
  created $dff cell `$procdff$15774' with positive edge clock.
Creating register for signal `\profibus_phy.$func$\parity9$parity_func.v:55$5350$\h' using process `\profibus_phy.$proc$profibus_phy_mod.v:604$5408'.
  created $dff cell `$procdff$15775' with positive edge clock.
Creating register for signal `\profibus_phy.$func$\parity9$parity_func.v:55$5350$\i' using process `\profibus_phy.$proc$profibus_phy_mod.v:604$5408'.
  created $dff cell `$procdff$15776' with positive edge clock.
Creating register for signal `\profibus_phy.$func$\crc8$profibus_phy_mod.v:703$5352$\crc8' using process `\profibus_phy.$proc$profibus_phy_mod.v:604$5408'.
  created $dff cell `$procdff$15777' with positive edge clock.
Creating register for signal `\profibus_phy.$func$\crc8$profibus_phy_mod.v:703$5352$\crcIn' using process `\profibus_phy.$proc$profibus_phy_mod.v:604$5408'.
  created $dff cell `$procdff$15778' with positive edge clock.
Creating register for signal `\profibus_phy.$func$\crc8$profibus_phy_mod.v:703$5352$\data' using process `\profibus_phy.$proc$profibus_phy_mod.v:604$5408'.
  created $dff cell `$procdff$15779' with positive edge clock.
Creating register for signal `\profibus_phy.$func$\crc8$profibus_phy_mod.v:711$5353$\crc8' using process `\profibus_phy.$proc$profibus_phy_mod.v:604$5408'.
  created $dff cell `$procdff$15780' with positive edge clock.
Creating register for signal `\profibus_phy.$func$\crc8$profibus_phy_mod.v:711$5353$\crcIn' using process `\profibus_phy.$proc$profibus_phy_mod.v:604$5408'.
  created $dff cell `$procdff$15781' with positive edge clock.
Creating register for signal `\profibus_phy.$func$\crc8$profibus_phy_mod.v:711$5353$\data' using process `\profibus_phy.$proc$profibus_phy_mod.v:604$5408'.
  created $dff cell `$procdff$15782' with positive edge clock.
Creating register for signal `\profibus_phy.$func$\tx_buf_overflow_get$profibus_phy_mod.v:762$5355$\tx_buf_overflow_get' using process `\profibus_phy.$proc$profibus_phy_mod.v:604$5408'.
  created $dff cell `$procdff$15783' with positive edge clock.
Creating register for signal `\profibus_phy.$func$\rx_buf_overflow_get$profibus_phy_mod.v:763$5356$\rx_buf_overflow_get' using process `\profibus_phy.$proc$profibus_phy_mod.v:604$5408'.
  created $dff cell `$procdff$15784' with positive edge clock.
Creating register for signal `\profibus_phy.$func$\spirx_ctrl_crcerr_get$profibus_phy_mod.v:764$5357$\spirx_ctrl_crcerr_get' using process `\profibus_phy.$proc$profibus_phy_mod.v:604$5408'.
  created $dff cell `$procdff$15785' with positive edge clock.
Creating register for signal `\profibus_phy.\tx_buf_rd_addr' using process `\profibus_phy.$proc$profibus_phy_mod.v:510$5397'.
  created $dff cell `$procdff$15786' with positive edge clock.
Creating register for signal `\profibus_phy.\uart_tx_data' using process `\profibus_phy.$proc$profibus_phy_mod.v:510$5397'.
  created $dff cell `$procdff$15787' with positive edge clock.
Creating register for signal `\profibus_phy.\uart_tx_trigger' using process `\profibus_phy.$proc$profibus_phy_mod.v:510$5397'.
  created $dff cell `$procdff$15788' with positive edge clock.
Creating register for signal `\profibus_phy.\rx_buf_wr_addr' using process `\profibus_phy.$proc$profibus_phy_mod.v:476$5389'.
  created $dff cell `$procdff$15789' with positive edge clock.
Creating register for signal `\profibus_phy.\rx_buf_wr_data' using process `\profibus_phy.$proc$profibus_phy_mod.v:476$5389'.
  created $dff cell `$procdff$15790' with positive edge clock.
Creating register for signal `\profibus_phy.\rx_buf_wr' using process `\profibus_phy.$proc$profibus_phy_mod.v:476$5389'.
  created $dff cell `$procdff$15791' with positive edge clock.
Creating register for signal `\profibus_phy.\rx_buf_overflow [0]' using process `\profibus_phy.$proc$profibus_phy_mod.v:476$5389'.
  created $dff cell `$procdff$15792' with positive edge clock.
Creating register for signal `\profibus_telegram_length.\length_valid' using process `\profibus_telegram_length.$proc$profibus_phy_mod.v:109$5333'.
  created $dff cell `$procdff$15793' with positive edge clock.
Creating register for signal `\profibus_telegram_length.\error' using process `\profibus_telegram_length.$proc$profibus_phy_mod.v:109$5333'.
  created $dff cell `$procdff$15794' with positive edge clock.
Creating register for signal `\profibus_telegram_length.\byte_le' using process `\profibus_telegram_length.$proc$profibus_phy_mod.v:109$5333'.
  created $dff cell `$procdff$15795' with positive edge clock.
Creating register for signal `\profibus_telegram_length.\state' using process `\profibus_telegram_length.$proc$profibus_phy_mod.v:109$5333'.
  created $dff cell `$procdff$15796' with positive edge clock.
Creating register for signal `\profibus_telegram_length.\length' using process `\profibus_telegram_length.$proc$profibus_phy_mod.v:109$5333'.
  created $dff cell `$procdff$15797' with positive edge clock.
Creating register for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.\rd_data0' using process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$proc$block_ram_mod.v:50$8299'.
  created $dff cell `$procdff$15798' with positive edge clock.
Creating register for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.\rd_data1' using process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$proc$block_ram_mod.v:50$8299'.
  created $dff cell `$procdff$15799' with positive edge clock.
Creating register for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:52$8298_ADDR' using process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$proc$block_ram_mod.v:50$8299'.
  created $dff cell `$procdff$15800' with positive edge clock.
Creating register for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:52$8298_DATA' using process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$proc$block_ram_mod.v:50$8299'.
  created $dff cell `$procdff$15801' with positive edge clock.
Creating register for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:52$8298_EN' using process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$proc$block_ram_mod.v:50$8299'.
  created $dff cell `$procdff$15802' with positive edge clock.
Creating register for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.\rd_data0' using process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$proc$block_ram_mod.v:50$7010'.
  created $dff cell `$procdff$15803' with positive edge clock.
Creating register for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.\rd_data1' using process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$proc$block_ram_mod.v:50$7010'.
  created $dff cell `$procdff$15804' with positive edge clock.
Creating register for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:52$7009_ADDR' using process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$proc$block_ram_mod.v:50$7010'.
  created $dff cell `$procdff$15805' with positive edge clock.
Creating register for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:52$7009_DATA' using process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$proc$block_ram_mod.v:50$7010'.
  created $dff cell `$procdff$15806' with positive edge clock.
Creating register for signal `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$memwr$\mem$block_ram_mod.v:52$7009_EN' using process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$proc$block_ram_mod.v:50$7010'.
  created $dff cell `$procdff$15807' with positive edge clock.
Creating register for signal `$paramod\uart_half_duplex\DATABITS=8\PARITY_EVEN=1\STOP=1\ACTIVE_LOW=0.\tx_trigger_req' using process `$paramod\uart_half_duplex\DATABITS=8\PARITY_EVEN=1\STOP=1\ACTIVE_LOW=0.$proc$uart_mod.v:582$6492'.
  created $dff cell `$procdff$15808' with positive edge clock.
Creating register for signal `$paramod\uart_half_duplex\DATABITS=8\PARITY_EVEN=1\STOP=1\ACTIVE_LOW=0.\tx_data_r' using process `$paramod\uart_half_duplex\DATABITS=8\PARITY_EVEN=1\STOP=1\ACTIVE_LOW=0.$proc$uart_mod.v:582$6492'.
  created $dff cell `$procdff$15809' with positive edge clock.
Creating register for signal `$paramod\spi_slave\WORDSIZE=8\CPOL=0\CPHA=0\MSB_FIRST=1.\miso_r' using process `$paramod\spi_slave\WORDSIZE=8\CPOL=0\CPHA=0\MSB_FIRST=1.$proc$spi_slave_mod.v:82$6479'.
  created $dff cell `$procdff$15810' with positive edge clock.
Creating register for signal `$paramod\spi_slave\WORDSIZE=8\CPOL=0\CPHA=0\MSB_FIRST=1.\rx_irq_r' using process `$paramod\spi_slave\WORDSIZE=8\CPOL=0\CPHA=0\MSB_FIRST=1.$proc$spi_slave_mod.v:82$6479'.
  created $dff cell `$procdff$15811' with positive edge clock.
Creating register for signal `$paramod\spi_slave\WORDSIZE=8\CPOL=0\CPHA=0\MSB_FIRST=1.\rx_data_r' using process `$paramod\spi_slave\WORDSIZE=8\CPOL=0\CPHA=0\MSB_FIRST=1.$proc$spi_slave_mod.v:82$6479'.
  created $dff cell `$procdff$15812' with positive edge clock.
Creating register for signal `$paramod\spi_slave\WORDSIZE=8\CPOL=0\CPHA=0\MSB_FIRST=1.\rx_shiftreg' using process `$paramod\spi_slave\WORDSIZE=8\CPOL=0\CPHA=0\MSB_FIRST=1.$proc$spi_slave_mod.v:82$6479'.
  created $dff cell `$procdff$15813' with positive edge clock.
Creating register for signal `$paramod\spi_slave\WORDSIZE=8\CPOL=0\CPHA=0\MSB_FIRST=1.\tx_shiftreg' using process `$paramod\spi_slave\WORDSIZE=8\CPOL=0\CPHA=0\MSB_FIRST=1.$proc$spi_slave_mod.v:82$6479'.
  created $dff cell `$procdff$15814' with positive edge clock.
Creating register for signal `$paramod\spi_slave\WORDSIZE=8\CPOL=0\CPHA=0\MSB_FIRST=1.\bit_count' using process `$paramod\spi_slave\WORDSIZE=8\CPOL=0\CPHA=0\MSB_FIRST=1.$proc$spi_slave_mod.v:82$6479'.
  created $dff cell `$procdff$15815' with positive edge clock.
Creating register for signal `$paramod\uart_rx\DATABITS=8\PARITY_EVEN=1\ACTIVE_LOW=0.\rx_parity' using process `$paramod\uart_rx\DATABITS=8\PARITY_EVEN=1\ACTIVE_LOW=0.$proc$uart_mod.v:190$9177'.
  created $dff cell `$procdff$15816' with positive edge clock.
Creating register for signal `$paramod\uart_rx\DATABITS=8\PARITY_EVEN=1\ACTIVE_LOW=0.\rx_active' using process `$paramod\uart_rx\DATABITS=8\PARITY_EVEN=1\ACTIVE_LOW=0.$proc$uart_mod.v:190$9177'.
  created $dff cell `$procdff$15817' with positive edge clock.
Creating register for signal `$paramod\uart_rx\DATABITS=8\PARITY_EVEN=1\ACTIVE_LOW=0.\rx_parity_ok' using process `$paramod\uart_rx\DATABITS=8\PARITY_EVEN=1\ACTIVE_LOW=0.$proc$uart_mod.v:190$9177'.
  created $dff cell `$procdff$15818' with positive edge clock.
Creating register for signal `$paramod\uart_rx\DATABITS=8\PARITY_EVEN=1\ACTIVE_LOW=0.\rx_frame_error' using process `$paramod\uart_rx\DATABITS=8\PARITY_EVEN=1\ACTIVE_LOW=0.$proc$uart_mod.v:190$9177'.
  created $dff cell `$procdff$15819' with positive edge clock.
Creating register for signal `$paramod\uart_rx\DATABITS=8\PARITY_EVEN=1\ACTIVE_LOW=0.\rx_irq' using process `$paramod\uart_rx\DATABITS=8\PARITY_EVEN=1\ACTIVE_LOW=0.$proc$uart_mod.v:190$9177'.
  created $dff cell `$procdff$15820' with positive edge clock.
Creating register for signal `$paramod\uart_rx\DATABITS=8\PARITY_EVEN=1\ACTIVE_LOW=0.\rx_data' using process `$paramod\uart_rx\DATABITS=8\PARITY_EVEN=1\ACTIVE_LOW=0.$proc$uart_mod.v:190$9177'.
  created $dff cell `$procdff$15821' with positive edge clock.
Creating register for signal `$paramod\uart_rx\DATABITS=8\PARITY_EVEN=1\ACTIVE_LOW=0.\sym_count' using process `$paramod\uart_rx\DATABITS=8\PARITY_EVEN=1\ACTIVE_LOW=0.$proc$uart_mod.v:190$9177'.
  created $dff cell `$procdff$15822' with positive edge clock.
Creating register for signal `$paramod\uart_rx\DATABITS=8\PARITY_EVEN=1\ACTIVE_LOW=0.\rx_buf' using process `$paramod\uart_rx\DATABITS=8\PARITY_EVEN=1\ACTIVE_LOW=0.$proc$uart_mod.v:190$9177'.
  created $dff cell `$procdff$15823' with positive edge clock.
Creating register for signal `$paramod\uart_rx\DATABITS=8\PARITY_EVEN=1\ACTIVE_LOW=0.\rx_parity_buf' using process `$paramod\uart_rx\DATABITS=8\PARITY_EVEN=1\ACTIVE_LOW=0.$proc$uart_mod.v:190$9177'.
  created $dff cell `$procdff$15824' with positive edge clock.
Creating register for signal `$paramod\uart_rx\DATABITS=8\PARITY_EVEN=1\ACTIVE_LOW=0.\rx_frame_error_start' using process `$paramod\uart_rx\DATABITS=8\PARITY_EVEN=1\ACTIVE_LOW=0.$proc$uart_mod.v:190$9177'.
  created $dff cell `$procdff$15825' with positive edge clock.
Creating register for signal `$paramod\uart_rx\DATABITS=8\PARITY_EVEN=1\ACTIVE_LOW=0.\symclk_n_reset' using process `$paramod\uart_rx\DATABITS=8\PARITY_EVEN=1\ACTIVE_LOW=0.$proc$uart_mod.v:190$9177'.
  created $dff cell `$procdff$15826' with positive edge clock.
Creating register for signal `$paramod\uart_tx\DATABITS=8\PARITY_EVEN=1\STOP=1\ACTIVE_LOW=0.\sym_count' using process `$paramod\uart_tx\DATABITS=8\PARITY_EVEN=1\STOP=1\ACTIVE_LOW=0.$proc$uart_mod.v:330$9102'.
  created $dff cell `$procdff$15827' with positive edge clock.
Creating register for signal `$paramod\uart_tx\DATABITS=8\PARITY_EVEN=1\STOP=1\ACTIVE_LOW=0.\symclk_n_reset' using process `$paramod\uart_tx\DATABITS=8\PARITY_EVEN=1\STOP=1\ACTIVE_LOW=0.$proc$uart_mod.v:330$9102'.
  created $dff cell `$procdff$15828' with positive edge clock.
Creating register for signal `$paramod\uart_tx\DATABITS=8\PARITY_EVEN=1\STOP=1\ACTIVE_LOW=0.\tx_irq' using process `$paramod\uart_tx\DATABITS=8\PARITY_EVEN=1\STOP=1\ACTIVE_LOW=0.$proc$uart_mod.v:330$9102'.
  created $dff cell `$procdff$15829' with positive edge clock.
Creating register for signal `$paramod\uart_tx\DATABITS=8\PARITY_EVEN=1\STOP=1\ACTIVE_LOW=0.\tx_r' using process `$paramod\uart_tx\DATABITS=8\PARITY_EVEN=1\STOP=1\ACTIVE_LOW=0.$proc$uart_mod.v:330$9102'.
  created $dff cell `$procdff$15830' with positive edge clock.
Creating register for signal `$paramod\uart_tx\DATABITS=8\PARITY_EVEN=1\STOP=1\ACTIVE_LOW=0.\tx_buf' using process `$paramod\uart_tx\DATABITS=8\PARITY_EVEN=1\STOP=1\ACTIVE_LOW=0.$proc$uart_mod.v:330$9102'.
  created $dff cell `$procdff$15831' with positive edge clock.
Creating register for signal `$paramod\uart_tx\DATABITS=8\PARITY_EVEN=1\STOP=1\ACTIVE_LOW=0.\tx_active' using process `$paramod\uart_tx\DATABITS=8\PARITY_EVEN=1\STOP=1\ACTIVE_LOW=0.$proc$uart_mod.v:330$9102'.
  created $dff cell `$procdff$15832' with positive edge clock.
Creating register for signal `\uart_symclk.\symend' using process `\uart_symclk.$proc$uart_mod.v:71$16'.
  created $dff cell `$procdff$15833' with positive edge clock.
Creating register for signal `\uart_symclk.\count' using process `\uart_symclk.$proc$uart_mod.v:71$16'.
  created $dff cell `$procdff$15834' with positive edge clock.
Creating register for signal `\uart_symclk.\setup' using process `\uart_symclk.$proc$uart_mod.v:71$16'.
  created $dff cell `$procdff$15835' with positive edge clock.
Creating register for signal `\uart_symclk.\sample' using process `\uart_symclk.$proc$uart_mod.v:71$16'.
  created $dff cell `$procdff$15836' with positive edge clock.
Creating register for signal `\edge_detect.\prev_signal' using process `\edge_detect.$proc$edge_detect_mod.v:36$7'.
  created $dff cell `$procdff$15837' with positive edge clock.
Creating register for signal `\sync_signal.\shiftreg' using process `\sync_signal.$proc$sync_signal_mod.v:38$1'.
  created $dff cell `$procdff$15838' with positive edge clock.

2.3.9. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Removing empty process `$paramod\led_blink\BLINK_ON_CLKS=2400000\BLINK_OFF_CLKS=685714.$proc$led_blink_mod.v:38$9251'.
Found and cleaned up 5 empty switches in `$paramod\led_blink\BLINK_ON_CLKS=2400000\BLINK_OFF_CLKS=685714.$proc$led_blink_mod.v:44$9246'.
Removing empty process `$paramod\led_blink\BLINK_ON_CLKS=2400000\BLINK_OFF_CLKS=685714.$proc$led_blink_mod.v:44$9246'.
Removing empty process `profibus_phy.$proc$profibus_phy_mod.v:1040$6287'.
Removing empty process `profibus_phy.$proc$profibus_phy_mod.v:869$6286'.
Removing empty process `profibus_phy.$proc$profibus_phy_mod.v:577$6285'.
Removing empty process `profibus_phy.$proc$profibus_phy_mod.v:472$6284'.
Removing empty process `profibus_phy.$proc$profibus_phy_mod.v:455$6283'.
Removing empty process `profibus_phy.$proc$profibus_phy_mod.v:423$6282'.
Removing empty process `profibus_phy.$proc$profibus_phy_mod.v:358$6281'.
Removing empty process `profibus_phy.$proc$profibus_phy_mod.v:310$6280'.
Removing empty process `profibus_phy.$proc$profibus_phy_mod.v:277$6279'.
Removing empty process `profibus_phy.$proc$profibus_phy_mod.v:592$6275'.
Removing empty process `profibus_phy.$proc$profibus_phy_mod.v:366$6271'.
Removing empty process `profibus_phy.$proc$profibus_phy_mod.v:318$6267'.
Found and cleaned up 4 empty switches in `\profibus_phy.$proc$profibus_phy_mod.v:1046$6259'.
Removing empty process `profibus_phy.$proc$profibus_phy_mod.v:1046$6259'.
Found and cleaned up 11 empty switches in `\profibus_phy.$proc$profibus_phy_mod.v:881$5661'.
Removing empty process `profibus_phy.$proc$profibus_phy_mod.v:881$5661'.
Found and cleaned up 25 empty switches in `\profibus_phy.$proc$profibus_phy_mod.v:604$5408'.
Removing empty process `profibus_phy.$proc$profibus_phy_mod.v:604$5408'.
Found and cleaned up 4 empty switches in `\profibus_phy.$proc$profibus_phy_mod.v:510$5397'.
Removing empty process `profibus_phy.$proc$profibus_phy_mod.v:510$5397'.
Found and cleaned up 5 empty switches in `\profibus_phy.$proc$profibus_phy_mod.v:476$5389'.
Removing empty process `profibus_phy.$proc$profibus_phy_mod.v:476$5389'.
Removing empty process `profibus_telegram_length.$proc$profibus_phy_mod.v:101$5344'.
Found and cleaned up 12 empty switches in `\profibus_telegram_length.$proc$profibus_phy_mod.v:109$5333'.
Removing empty process `profibus_telegram_length.$proc$profibus_phy_mod.v:109$5333'.
Removing empty process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$proc$block_ram_mod.v:44$8562'.
Found and cleaned up 1 empty switch in `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$proc$block_ram_mod.v:50$8299'.
Removing empty process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.$proc$block_ram_mod.v:50$8299'.
Removing empty process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$proc$block_ram_mod.v:44$7273'.
Found and cleaned up 1 empty switch in `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$proc$block_ram_mod.v:50$7010'.
Removing empty process `$paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.$proc$block_ram_mod.v:50$7010'.
Removing empty process `$paramod\uart_half_duplex\DATABITS=8\PARITY_EVEN=1\STOP=1\ACTIVE_LOW=0.$proc$uart_mod.v:577$6496'.
Found and cleaned up 4 empty switches in `$paramod\uart_half_duplex\DATABITS=8\PARITY_EVEN=1\STOP=1\ACTIVE_LOW=0.$proc$uart_mod.v:582$6492'.
Removing empty process `$paramod\uart_half_duplex\DATABITS=8\PARITY_EVEN=1\STOP=1\ACTIVE_LOW=0.$proc$uart_mod.v:582$6492'.
Removing empty process `$paramod\spi_slave\WORDSIZE=8\CPOL=0\CPHA=0\MSB_FIRST=1.$proc$spi_slave_mod.v:71$6488'.
Found and cleaned up 5 empty switches in `$paramod\spi_slave\WORDSIZE=8\CPOL=0\CPHA=0\MSB_FIRST=1.$proc$spi_slave_mod.v:82$6479'.
Removing empty process `$paramod\spi_slave\WORDSIZE=8\CPOL=0\CPHA=0\MSB_FIRST=1.$proc$spi_slave_mod.v:82$6479'.
Removing empty process `$paramod\uart_rx\DATABITS=8\PARITY_EVEN=1\ACTIVE_LOW=0.$proc$uart_mod.v:175$9245'.
Removing empty process `$paramod\uart_rx\DATABITS=8\PARITY_EVEN=1\ACTIVE_LOW=0.$proc$parity_func.v:26$9207'.
Found and cleaned up 15 empty switches in `$paramod\uart_rx\DATABITS=8\PARITY_EVEN=1\ACTIVE_LOW=0.$proc$uart_mod.v:190$9177'.
Removing empty process `$paramod\uart_rx\DATABITS=8\PARITY_EVEN=1\ACTIVE_LOW=0.$proc$uart_mod.v:190$9177'.
Removing empty process `$paramod\uart_tx\DATABITS=8\PARITY_EVEN=1\STOP=1\ACTIVE_LOW=0.$proc$uart_mod.v:322$9171'.
Removing empty process `$paramod\uart_tx\DATABITS=8\PARITY_EVEN=1\STOP=1\ACTIVE_LOW=0.$proc$parity_func.v:26$9133'.
Found and cleaned up 17 empty switches in `$paramod\uart_tx\DATABITS=8\PARITY_EVEN=1\STOP=1\ACTIVE_LOW=0.$proc$uart_mod.v:330$9102'.
Removing empty process `$paramod\uart_tx\DATABITS=8\PARITY_EVEN=1\STOP=1\ACTIVE_LOW=0.$proc$uart_mod.v:330$9102'.
Removing empty process `uart_symclk.$proc$uart_mod.v:64$25'.
Found and cleaned up 4 empty switches in `\uart_symclk.$proc$uart_mod.v:71$16'.
Removing empty process `uart_symclk.$proc$uart_mod.v:71$16'.
Removing empty process `edge_detect.$proc$edge_detect_mod.v:36$7'.
Removing empty process `sync_signal.$proc$sync_signal_mod.v:34$6'.
Removing empty process `sync_signal.$proc$sync_signal_mod.v:38$1'.
Cleaned up 113 empty switches.

2.4. Executing FLATTEN pass (flatten design).
Using template pll_module for cells of type pll_module.
Using template $paramod\common_main_module\CLK_HZ=24000000 for cells of type $paramod\common_main_module\CLK_HZ=24000000.
Using template $paramod\led_blink\BLINK_ON_CLKS=2400000\BLINK_OFF_CLKS=685714 for cells of type $paramod\led_blink\BLINK_ON_CLKS=2400000\BLINK_OFF_CLKS=685714.
Using template profibus_phy for cells of type profibus_phy.
Using template profibus_telegram_length for cells of type profibus_telegram_length.
Using template $paramod\spi_slave\WORDSIZE=8\CPOL=0\CPHA=0\MSB_FIRST=1 for cells of type $paramod\spi_slave\WORDSIZE=8\CPOL=0\CPHA=0\MSB_FIRST=1.
Using template $paramod\uart_half_duplex\DATABITS=8\PARITY_EVEN=1\STOP=1\ACTIVE_LOW=0 for cells of type $paramod\uart_half_duplex\DATABITS=8\PARITY_EVEN=1\STOP=1\ACTIVE_LOW=0.
Using template $paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256 for cells of type $paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.
Using template $paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256 for cells of type $paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.
Using template sync_signal for cells of type sync_signal.
Using template $paramod\uart_tx\DATABITS=8\PARITY_EVEN=1\STOP=1\ACTIVE_LOW=0 for cells of type $paramod\uart_tx\DATABITS=8\PARITY_EVEN=1\STOP=1\ACTIVE_LOW=0.
Using template $paramod\uart_rx\DATABITS=8\PARITY_EVEN=1\ACTIVE_LOW=0 for cells of type $paramod\uart_rx\DATABITS=8\PARITY_EVEN=1\ACTIVE_LOW=0.
Using template $paramod\uart_arbiter\ACTIVE_LOW=0 for cells of type $paramod\uart_arbiter\ACTIVE_LOW=0.
Using template uart_symclk for cells of type uart_symclk.
Using template edge_detect for cells of type edge_detect.
<suppressed ~19 debug messages>
No more expansions possible.
Deleting now unused module pll_module.
Deleting now unused module $paramod\common_main_module\CLK_HZ=24000000.
Deleting now unused module $paramod\led_blink\BLINK_ON_CLKS=2400000\BLINK_OFF_CLKS=685714.
Deleting now unused module profibus_phy.
Deleting now unused module profibus_telegram_length.
Deleting now unused module $paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=8\MEM_BYTES=256.
Deleting now unused module $paramod\block_ram\ADDR_WIDTH=8\DATA_WIDTH=9\MEM_BYTES=256.
Deleting now unused module $paramod\uart_half_duplex\DATABITS=8\PARITY_EVEN=1\STOP=1\ACTIVE_LOW=0.
Deleting now unused module $paramod\spi_slave\WORDSIZE=8\CPOL=0\CPHA=0\MSB_FIRST=1.
Deleting now unused module $paramod\uart_arbiter\ACTIVE_LOW=0.
Deleting now unused module $paramod\uart_rx\DATABITS=8\PARITY_EVEN=1\ACTIVE_LOW=0.
Deleting now unused module $paramod\uart_tx\DATABITS=8\PARITY_EVEN=1\STOP=1\ACTIVE_LOW=0.
Deleting now unused module uart_symclk.
Deleting now unused module edge_detect.
Deleting now unused module sync_signal.

2.5. Executing TRIBUF pass.

2.6. Executing DEMINOUT pass (demote inout ports to input or output).
Demoting inout port top_module.PIN_10 to output.

2.7. Executing OPT_EXPR pass (perform const folding).
Optimizing module top_module.
<suppressed ~123 debug messages>

2.8. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \top_module..
Removed 1463 unused cells and 6064 unused wires.
<suppressed ~1509 debug messages>

2.9. Executing CHECK pass (checking for obvious problems).
checking module top_module..
found and reported 0 problems.

2.10. Executing OPT pass (performing simple optimizations).

2.10.1. Executing OPT_EXPR pass (perform const folding).
Optimizing module top_module.

2.10.2. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\top_module'.
<suppressed ~948 debug messages>
Removed a total of 316 cells.

2.10.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
Running muxtree optimizer on module \top_module..
  Creating internal representation of mux trees.
  Evaluating internal representation of mux trees.
      Replacing known input bits on port A of cell $techmap\common.led_blink.$procmux$9286: \common.led_blink.led -> 1'1
      Replacing known input bits on port A of cell $techmap\common.led_blink.$procmux$9282: \common.led_blink.led -> 1'0
      Replacing known input bits on port A of cell $techmap\common.led_blink.$procmux$9280: \common.led_blink.led -> 1'0
      Replacing known input bits on port B of cell $techmap\common.pb.$procmux$14393: \common.pb.spirx_len_valid -> 1'1
      Replacing known input bits on port B of cell $techmap\common.pb.$procmux$14390: \common.pb.spirx_len_valid -> 1'0
      Replacing known input bits on port A of cell $techmap\common.pb.$procmux$14387: \common.pb.spirx_len_valid -> 1'0
      Replacing known input bits on port A of cell $techmap\common.pb.$procmux$14549: \common.pb.tx_buf_wr -> 1'0
      Replacing known input bits on port A of cell $techmap\common.pb.$procmux$14547: \common.pb.tx_buf_wr -> 1'0
      Replacing known input bits on port A of cell $techmap\common.pb.$procmux$14556: \common.pb.tx_buf_wr -> 1'0
      Replacing known input bits on port A of cell $techmap\common.pb.$procmux$14659: \common.pb.uart_tx_trigger -> 1'0
      Replacing known input bits on port A of cell $techmap\common.pb.$procmux$14657: \common.pb.uart_tx_trigger -> 1'0
      Replacing known input bits on port A of cell $techmap\common.pb.$procmux$14709: \common.pb.rx_buf_wr -> 1'0
      Replacing known input bits on port A of cell $techmap\common.pb.uart.$procmux$14904: \common.pb.uart.tx_trigger_req -> 1'1
      Replacing known input bits on port A of cell $techmap\common.pb.uart.$procmux$14901: \common.pb.uart.tx_trigger_req -> 1'0
  Analyzing evaluation results.
    dead port 2/2 on $mux $techmap\common.pb.$procmux$10471.
    dead port 1/2 on $mux $techmap\common.pb.$procmux$10474.
    dead port 2/2 on $mux $techmap\common.pb.$procmux$10476.
    dead port 1/2 on $mux $techmap\common.pb.$procmux$10674.
    dead port 2/2 on $mux $techmap\common.pb.$procmux$10676.
    dead port 2/2 on $mux $techmap\common.pb.$procmux$10695.
    dead port 2/2 on $mux $techmap\common.pb.$procmux$11151.
    dead port 2/2 on $mux $techmap\common.pb.$procmux$11333.
    dead port 2/2 on $mux $techmap\common.pb.$procmux$11365.
    dead port 2/2 on $mux $techmap\common.pb.$procmux$11412.
    dead port 1/2 on $mux $techmap\common.pb.$procmux$9327.
    dead port 2/2 on $mux $techmap\common.pb.$procmux$9329.
    dead port 2/2 on $mux $techmap\common.pb.$procmux$9331.
    dead port 1/2 on $mux $techmap\common.pb.$procmux$9334.
    dead port 2/2 on $mux $techmap\common.pb.$procmux$9336.
    dead port 1/2 on $mux $techmap\common.pb.$procmux$9729.
    dead port 2/2 on $mux $techmap\common.pb.$procmux$9731.
    dead port 2/2 on $mux $techmap\common.pb.$procmux$9733.
    dead port 1/2 on $mux $techmap\common.pb.$procmux$9736.
    dead port 2/2 on $mux $techmap\common.pb.$procmux$9738.
    dead port 1/2 on $mux $techmap\common.pb.$procmux$9753.
    dead port 2/2 on $mux $techmap\common.pb.$procmux$9755.
    dead port 2/2 on $mux $techmap\common.pb.$procmux$9757.
    dead port 1/2 on $mux $techmap\common.pb.$procmux$9760.
    dead port 2/2 on $mux $techmap\common.pb.$procmux$9762.
    dead port 1/2 on $mux $techmap\common.pb.$procmux$9777.
    dead port 2/2 on $mux $techmap\common.pb.$procmux$9779.
    dead port 2/2 on $mux $techmap\common.pb.$procmux$9781.
    dead port 1/2 on $mux $techmap\common.pb.$procmux$9784.
    dead port 2/2 on $mux $techmap\common.pb.$procmux$9786.
    dead port 1/2 on $mux $techmap\common.pb.$procmux$9801.
    dead port 2/2 on $mux $techmap\common.pb.$procmux$9803.
    dead port 2/2 on $mux $techmap\common.pb.$procmux$9805.
    dead port 1/2 on $mux $techmap\common.pb.$procmux$9808.
    dead port 2/2 on $mux $techmap\common.pb.$procmux$9810.
    dead port 1/2 on $mux $techmap\common.pb.$procmux$9825.
    dead port 2/2 on $mux $techmap\common.pb.$procmux$9827.
    dead port 2/2 on $mux $techmap\common.pb.$procmux$9829.
    dead port 1/2 on $mux $techmap\common.pb.$procmux$9832.
    dead port 2/2 on $mux $techmap\common.pb.$procmux$9834.
    dead port 1/2 on $mux $techmap\common.pb.$procmux$9849.
    dead port 2/2 on $mux $techmap\common.pb.$procmux$9851.
    dead port 2/2 on $mux $techmap\common.pb.$procmux$9853.
    dead port 1/2 on $mux $techmap\common.pb.$procmux$9856.
    dead port 2/2 on $mux $techmap\common.pb.$procmux$9858.
    dead port 1/2 on $mux $techmap\common.pb.$procmux$9873.
    dead port 2/2 on $mux $techmap\common.pb.$procmux$9875.
    dead port 2/2 on $mux $techmap\common.pb.$procmux$9877.
    dead port 1/2 on $mux $techmap\common.pb.$procmux$9880.
    dead port 2/2 on $mux $techmap\common.pb.$procmux$9882.
    dead port 2/2 on $mux $techmap\common.pb.$procmux$9890.
    dead port 2/2 on $mux $techmap\common.pb.$procmux$9892.
    dead port 1/2 on $mux $techmap\common.pb.$procmux$9895.
    dead port 2/2 on $mux $techmap\common.pb.$procmux$9897.
    dead port 2/2 on $mux $techmap\common.pb.$procmux$11461.
    dead port 2/2 on $mux $techmap\common.pb.$procmux$11512.
    dead port 2/2 on $mux $techmap\common.pb.$procmux$11565.
    dead port 2/2 on $mux $techmap\common.pb.uart.rx_mod.$procmux$14961.
    dead port 1/2 on $mux $techmap\common.pb.uart.rx_mod.$procmux$14964.
    dead port 1/2 on $mux $techmap\common.pb.uart.rx_mod.$procmux$14967.
    dead port 1/2 on $mux $techmap\common.pb.uart.rx_mod.$procmux$14970.
    dead port 2/2 on $mux $techmap\common.pb.uart.rx_mod.$procmux$14972.
    dead port 1/2 on $mux $techmap\common.pb.uart.rx_mod.$procmux$14979.
    dead port 1/2 on $mux $techmap\common.pb.uart.rx_mod.$procmux$14982.
    dead port 1/2 on $mux $techmap\common.pb.uart.rx_mod.$procmux$14985.
    dead port 2/2 on $mux $techmap\common.pb.uart.rx_mod.$procmux$14987.
    dead port 2/2 on $mux $techmap\common.pb.uart.rx_mod.$procmux$14995.
    dead port 2/2 on $mux $techmap\common.pb.uart.rx_mod.$procmux$14997.
    dead port 1/2 on $mux $techmap\common.pb.uart.rx_mod.$procmux$15000.
    dead port 1/2 on $mux $techmap\common.pb.uart.rx_mod.$procmux$15003.
    dead port 2/2 on $mux $techmap\common.pb.uart.rx_mod.$procmux$15005.
    dead port 2/2 on $mux $techmap\common.pb.uart.rx_mod.$procmux$15016.
    dead port 2/2 on $mux $techmap\common.pb.uart.rx_mod.$procmux$15018.
    dead port 1/2 on $mux $techmap\common.pb.uart.rx_mod.$procmux$15021.
    dead port 1/2 on $mux $techmap\common.pb.uart.rx_mod.$procmux$15024.
    dead port 2/2 on $mux $techmap\common.pb.uart.rx_mod.$procmux$15026.
    dead port 2/2 on $mux $techmap\common.pb.uart.rx_mod.$procmux$15039.
    dead port 2/2 on $mux $techmap\common.pb.uart.rx_mod.$procmux$15041.
    dead port 1/2 on $mux $techmap\common.pb.uart.rx_mod.$procmux$15044.
    dead port 1/2 on $mux $techmap\common.pb.uart.rx_mod.$procmux$15047.
    dead port 2/2 on $mux $techmap\common.pb.uart.rx_mod.$procmux$15049.
    dead port 2/2 on $mux $techmap\common.pb.uart.rx_mod.$procmux$15064.
    dead port 2/2 on $mux $techmap\common.pb.uart.rx_mod.$procmux$15066.
    dead port 1/2 on $mux $techmap\common.pb.uart.rx_mod.$procmux$15069.
    dead port 1/2 on $mux $techmap\common.pb.uart.rx_mod.$procmux$15072.
    dead port 2/2 on $mux $techmap\common.pb.uart.rx_mod.$procmux$15074.
    dead port 2/2 on $mux $techmap\common.pb.uart.rx_mod.$procmux$15083.
    dead port 2/2 on $mux $techmap\common.pb.uart.rx_mod.$procmux$15085.
    dead port 1/2 on $mux $techmap\common.pb.uart.rx_mod.$procmux$15088.
    dead port 1/2 on $mux $techmap\common.pb.uart.rx_mod.$procmux$15091.
    dead port 2/2 on $mux $techmap\common.pb.uart.rx_mod.$procmux$15093.
    dead port 2/2 on $mux $techmap\common.pb.uart.rx_mod.$procmux$15107.
    dead port 2/2 on $mux $techmap\common.pb.uart.rx_mod.$procmux$15109.
    dead port 1/2 on $mux $techmap\common.pb.uart.rx_mod.$procmux$15112.
    dead port 1/2 on $mux $techmap\common.pb.uart.rx_mod.$procmux$15115.
    dead port 2/2 on $mux $techmap\common.pb.uart.rx_mod.$procmux$15117.
    dead port 2/2 on $mux $techmap\common.pb.uart.rx_mod.$procmux$15129.
    dead port 2/2 on $mux $techmap\common.pb.uart.rx_mod.$procmux$15131.
    dead port 1/2 on $mux $techmap\common.pb.uart.rx_mod.$procmux$15134.
    dead port 1/2 on $mux $techmap\common.pb.uart.rx_mod.$procmux$15137.
    dead port 2/2 on $mux $techmap\common.pb.uart.rx_mod.$procmux$15139.
    dead port 2/2 on $mux $techmap\common.pb.uart.rx_mod.$procmux$15149.
    dead port 2/2 on $mux $techmap\common.pb.uart.rx_mod.$procmux$15151.
    dead port 1/2 on $mux $techmap\common.pb.uart.rx_mod.$procmux$15154.
    dead port 1/2 on $mux $techmap\common.pb.uart.rx_mod.$procmux$15157.
    dead port 2/2 on $mux $techmap\common.pb.uart.rx_mod.$procmux$15159.
    dead port 2/2 on $mux $techmap\common.pb.uart.rx_mod.$procmux$15166.
    dead port 1/2 on $mux $techmap\common.pb.uart.rx_mod.$procmux$15169.
    dead port 1/2 on $mux $techmap\common.pb.uart.rx_mod.$procmux$15172.
    dead port 2/2 on $mux $techmap\common.pb.uart.rx_mod.$procmux$15174.
    dead port 1/2 on $mux $techmap\common.pb.uart.rx_mod.$procmux$15181.
    dead port 1/2 on $mux $techmap\common.pb.uart.rx_mod.$procmux$15184.
    dead port 2/2 on $mux $techmap\common.pb.uart.rx_mod.$procmux$15186.
    dead port 1/2 on $mux $techmap\common.pb.uart.rx_mod.$procmux$15193.
    dead port 1/2 on $mux $techmap\common.pb.uart.rx_mod.$procmux$15196.
    dead port 2/2 on $mux $techmap\common.pb.uart.rx_mod.$procmux$15198.
    dead port 1/2 on $mux $techmap\common.pb.uart.rx_mod.$procmux$15205.
    dead port 2/2 on $mux $techmap\common.pb.uart.rx_mod.$procmux$15207.
    dead port 1/2 on $mux $techmap\common.pb.uart.rx_mod.$procmux$15214.
    dead port 2/2 on $mux $techmap\common.pb.uart.rx_mod.$procmux$15216.
    dead port 2/2 on $mux $techmap\common.pb.uart.rx_mod.$procmux$15222.
    dead port 2/2 on $mux $techmap\common.pb.uart.rx_mod.$procmux$15230.
Removed 122 multiplexer ports.
<suppressed ~102 debug messages>

2.10.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
  Optimizing cells in module \top_module.
    New ctrl vector for $pmux cell $techmap\common.pb.$procmux$14257: { $techmap\common.pb.$procmux$14280_CMP $techmap\common.pb.$procmux$13500_CMP $auto$opt_reduce.cc:132:opt_mux$15856 }
    New ctrl vector for $pmux cell $techmap\common.pb.$procmux$14316: { $techmap\common.pb.$procmux$14238_CMP $techmap\common.pb.$procmux$14260_CMP $auto$opt_reduce.cc:132:opt_mux$15858 }
    New ctrl vector for $pmux cell $techmap\common.pb.$procmux$12930: $auto$opt_reduce.cc:132:opt_mux$15860
    New ctrl vector for $pmux cell $techmap\common.pb.$procmux$14335: { $techmap\common.pb.$procmux$14238_CMP $techmap\common.pb.$procmux$14261_CMP $auto$opt_reduce.cc:132:opt_mux$15862 }
    New ctrl vector for $mux cell $techmap\common.pb.$procmux$14362: { }
    New ctrl vector for $pmux cell $techmap\common.pb.$procmux$11352: { $auto$opt_reduce.cc:132:opt_mux$15864 $techmap\common.pb.$procmux$10688_CMP $techmap\common.pb.$procmux$10687_CMP $techmap\common.pb.$procmux$10686_CMP $techmap\common.pb.$procmux$10685_CMP $techmap\common.pb.$procmux$10684_CMP $techmap\common.pb.$procmux$10683_CMP }
    New ctrl vector for $pmux cell $techmap\common.pb.$procmux$14541: { $techmap\common.pb.$procmux$14238_CMP $techmap\common.pb.$procmux$13500_CMP $auto$opt_reduce.cc:132:opt_mux$15866 }
    New ctrl vector for $mux cell $techmap\common.pb.$procmux$14556: { }
    New ctrl vector for $pmux cell $techmap\common.pb.$procmux$14563: { $techmap\common.pb.$procmux$13500_CMP $auto$opt_reduce.cc:132:opt_mux$15868 }
    New ctrl vector for $mux cell $techmap\common.pb.$procmux$12912: { }
    New ctrl vector for $pmux cell $techmap\common.pb.$procmux$14583: { $techmap\common.pb.$procmux$14238_CMP $techmap\common.pb.$procmux$13500_CMP $auto$opt_reduce.cc:132:opt_mux$15870 }
    New ctrl vector for $mux cell $techmap\common.pb.$procmux$14709: { }
    New ctrl vector for $pmux cell $techmap\common.pb.$procmux$12949: $auto$opt_reduce.cc:132:opt_mux$15872
    Consolidated identical input bits for $mux cell $techmap\common.pb.rx_buf.$procmux$14884:
      Old ports: A=9'000000000, B=9'111111111, Y=$techmap\common.pb.rx_buf.$0$memwr$\mem$block_ram_mod.v:52$7009_EN[8:0]$7013
      New ports: A=1'0, B=1'1, Y=$techmap\common.pb.rx_buf.$0$memwr$\mem$block_ram_mod.v:52$7009_EN[8:0]$7013 [0]
      New connections: $techmap\common.pb.rx_buf.$0$memwr$\mem$block_ram_mod.v:52$7009_EN[8:0]$7013 [8:1] = { $techmap\common.pb.rx_buf.$0$memwr$\mem$block_ram_mod.v:52$7009_EN[8:0]$7013 [0] $techmap\common.pb.rx_buf.$0$memwr$\mem$block_ram_mod.v:52$7009_EN[8:0]$7013 [0] $techmap\common.pb.rx_buf.$0$memwr$\mem$block_ram_mod.v:52$7009_EN[8:0]$7013 [0] $techmap\common.pb.rx_buf.$0$memwr$\mem$block_ram_mod.v:52$7009_EN[8:0]$7013 [0] $techmap\common.pb.rx_buf.$0$memwr$\mem$block_ram_mod.v:52$7009_EN[8:0]$7013 [0] $techmap\common.pb.rx_buf.$0$memwr$\mem$block_ram_mod.v:52$7009_EN[8:0]$7013 [0] $techmap\common.pb.rx_buf.$0$memwr$\mem$block_ram_mod.v:52$7009_EN[8:0]$7013 [0] $techmap\common.pb.rx_buf.$0$memwr$\mem$block_ram_mod.v:52$7009_EN[8:0]$7013 [0] }
    New ctrl vector for $pmux cell $techmap\common.pb.spirx_lencalc.$procmux$14797: { $techmap\common.pb.spirx_lencalc.$procmux$14749_CMP $auto$opt_reduce.cc:132:opt_mux$15874 }
    New ctrl vector for $pmux cell $techmap\common.pb.$procmux$12845: $auto$opt_reduce.cc:132:opt_mux$15876
    Consolidated identical input bits for $mux cell $techmap\common.pb.tx_buf.$procmux$14878:
      Old ports: A=8'00000000, B=8'11111111, Y=$techmap\common.pb.tx_buf.$0$memwr$\mem$block_ram_mod.v:52$8298_EN[7:0]$8302
      New ports: A=1'0, B=1'1, Y=$techmap\common.pb.tx_buf.$0$memwr$\mem$block_ram_mod.v:52$8298_EN[7:0]$8302 [0]
      New connections: $techmap\common.pb.tx_buf.$0$memwr$\mem$block_ram_mod.v:52$8298_EN[7:0]$8302 [7:1] = { $techmap\common.pb.tx_buf.$0$memwr$\mem$block_ram_mod.v:52$8298_EN[7:0]$8302 [0] $techmap\common.pb.tx_buf.$0$memwr$\mem$block_ram_mod.v:52$8298_EN[7:0]$8302 [0] $techmap\common.pb.tx_buf.$0$memwr$\mem$block_ram_mod.v:52$8298_EN[7:0]$8302 [0] $techmap\common.pb.tx_buf.$0$memwr$\mem$block_ram_mod.v:52$8298_EN[7:0]$8302 [0] $techmap\common.pb.tx_buf.$0$memwr$\mem$block_ram_mod.v:52$8298_EN[7:0]$8302 [0] $techmap\common.pb.tx_buf.$0$memwr$\mem$block_ram_mod.v:52$8298_EN[7:0]$8302 [0] $techmap\common.pb.tx_buf.$0$memwr$\mem$block_ram_mod.v:52$8298_EN[7:0]$8302 [0] }
    New input vector for $reduce_or cell $auto$opt_reduce.cc:126:opt_mux$15867: { $techmap\common.pb.$procmux$14280_CMP $techmap\common.pb.$procmux$14261_CMP $techmap\common.pb.$procmux$14260_CMP $techmap\common.pb.$procmux$14238_CMP $techmap\common.pb.$procmux$13248_CMP $techmap\common.pb.$procmux$13005_CMP }
    New input vector for $reduce_or cell $auto$opt_reduce.cc:126:opt_mux$15861: { $techmap\common.pb.$procmux$14280_CMP $techmap\common.pb.$procmux$14260_CMP $techmap\common.pb.$procmux$13500_CMP $techmap\common.pb.$procmux$13248_CMP $techmap\common.pb.$procmux$13005_CMP }
    New input vector for $reduce_or cell $auto$opt_reduce.cc:126:opt_mux$15857: { $techmap\common.pb.$procmux$14280_CMP $techmap\common.pb.$procmux$14261_CMP $techmap\common.pb.$procmux$13500_CMP $techmap\common.pb.$procmux$13248_CMP $techmap\common.pb.$procmux$13005_CMP }
    New input vector for $reduce_or cell $auto$opt_reduce.cc:126:opt_mux$15859: { $techmap\common.pb.$procmux$10688_CMP $techmap\common.pb.$procmux$10687_CMP $techmap\common.pb.$procmux$10686_CMP $techmap\common.pb.$procmux$10685_CMP $techmap\common.pb.$procmux$10684_CMP $techmap\common.pb.$eq$profibus_phy_mod.v:970$6215_Y $techmap\common.pb.$eq$profibus_phy_mod.v:964$6192_Y }
    New input vector for $reduce_or cell $auto$opt_reduce.cc:126:opt_mux$15863: { $techmap\common.pb.$eq$profibus_phy_mod.v:970$6215_Y $techmap\common.pb.$eq$profibus_phy_mod.v:964$6192_Y }
    New input vector for $reduce_or cell $auto$opt_reduce.cc:126:opt_mux$15871: { $techmap\common.pb.$procmux$10688_CMP $techmap\common.pb.$procmux$10687_CMP $techmap\common.pb.$procmux$10686_CMP $techmap\common.pb.$procmux$10685_CMP $techmap\common.pb.$procmux$10684_CMP $techmap\common.pb.$eq$profibus_phy_mod.v:970$6215_Y $techmap\common.pb.$eq$profibus_phy_mod.v:964$6192_Y }
    New input vector for $reduce_or cell $auto$opt_reduce.cc:126:opt_mux$15875: { $techmap\common.pb.$procmux$10688_CMP $techmap\common.pb.$procmux$10687_CMP $techmap\common.pb.$procmux$10686_CMP $techmap\common.pb.$procmux$10685_CMP $techmap\common.pb.$procmux$10684_CMP $techmap\common.pb.$eq$profibus_phy_mod.v:970$6215_Y $techmap\common.pb.$eq$profibus_phy_mod.v:964$6192_Y }
    New ctrl vector for $pmux cell $techmap\common.pb.$procmux$14541: { $techmap\common.pb.$procmux$13500_CMP $auto$opt_reduce.cc:132:opt_mux$15866 }
  Optimizing cells in module \top_module.
Performed a total of 25 changes.

2.10.5. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\top_module'.
<suppressed ~102 debug messages>
Removed a total of 34 cells.

2.10.6. Executing OPT_RMDFF pass (remove dff with constant values).
Promoting init spec \common.pb.uart.rx_mod.rx_parity = 1'0 to constant driver in module top_module.
Promoting init spec \common.pb.uart.tx_mod.symclk.sample = 1'0 to constant driver in module top_module.
Promoting init spec \common.pb.uart.rx_mod.symclk.setup = 1'0 to constant driver in module top_module.
Promoted 3 init specs to constant drivers.

2.10.7. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \top_module..
Removed 0 unused cells and 476 unused wires.
<suppressed ~1 debug messages>

2.10.8. Executing OPT_EXPR pass (perform const folding).
Optimizing module top_module.

2.10.9. Rerunning OPT passes. (Maybe there is more to do..)

2.10.10. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
Running muxtree optimizer on module \top_module..
  Creating internal representation of mux trees.
  Evaluating internal representation of mux trees.
  Analyzing evaluation results.
Removed 0 multiplexer ports.
<suppressed ~105 debug messages>

2.10.11. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
  Optimizing cells in module \top_module.
    New ctrl vector for $pmux cell $techmap\common.pb.$procmux$12992: { $auto$opt_reduce.cc:132:opt_mux$15880 $auto$opt_reduce.cc:132:opt_mux$15878 }
    New ctrl vector for $pmux cell $techmap\common.pb.$procmux$13013: { $techmap\common.pb.$procmux$13003_CMP $techmap\common.pb.$procmux$13000_CMP $auto$opt_reduce.cc:132:opt_mux$15882 }
    New ctrl vector for $pmux cell $techmap\common.pb.$procmux$13034: { $techmap\common.pb.$procmux$13003_CMP $techmap\common.pb.$procmux$13000_CMP $auto$opt_reduce.cc:132:opt_mux$15884 }
    New ctrl vector for $pmux cell $techmap\common.pb.$procmux$13070: { $techmap\common.pb.$procmux$13003_CMP $techmap\common.pb.$procmux$13000_CMP $auto$opt_reduce.cc:132:opt_mux$15886 }
    New ctrl vector for $pmux cell $techmap\common.pb.$procmux$13106: { $techmap\common.pb.$procmux$13003_CMP $techmap\common.pb.$procmux$13000_CMP $auto$opt_reduce.cc:132:opt_mux$15888 }
    New ctrl vector for $pmux cell $techmap\common.pb.$procmux$13142: { $techmap\common.pb.$procmux$13003_CMP $techmap\common.pb.$procmux$13000_CMP $auto$opt_reduce.cc:132:opt_mux$15890 }
    New ctrl vector for $pmux cell $techmap\common.pb.$procmux$13163: { $techmap\common.pb.$procmux$13003_CMP $techmap\common.pb.$procmux$13000_CMP $auto$opt_reduce.cc:132:opt_mux$15892 }
    New ctrl vector for $pmux cell $techmap\common.pb.$procmux$13184: $auto$opt_reduce.cc:132:opt_mux$15894
    New ctrl vector for $pmux cell $techmap\common.pb.$procmux$14178: $auto$opt_reduce.cc:132:opt_mux$15896
    New ctrl vector for $pmux cell $techmap\common.pb.$procmux$14211: { $techmap\common.pb.$procmux$13003_CMP $techmap\common.pb.$procmux$13000_CMP $auto$opt_reduce.cc:132:opt_mux$15898 }
    New ctrl vector for $pmux cell $techmap\common.pb.$procmux$14301: { $techmap\common.pb.$procmux$14238_CMP $auto$opt_reduce.cc:132:opt_mux$15900 }
    New ctrl vector for $pmux cell $techmap\common.pb.$procmux$14432: $auto$opt_reduce.cc:132:opt_mux$15902
    New ctrl vector for $pmux cell $techmap\common.pb.$procmux$14583: { $auto$opt_reduce.cc:132:opt_mux$15904 $auto$opt_reduce.cc:132:opt_mux$15866 }
  Optimizing cells in module \top_module.
Performed a total of 13 changes.

2.10.12. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\top_module'.
<suppressed ~27 debug messages>
Removed a total of 9 cells.

2.10.13. Executing OPT_RMDFF pass (remove dff with constant values).

2.10.14. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \top_module..
Removed 0 unused cells and 9 unused wires.
<suppressed ~1 debug messages>

2.10.15. Executing OPT_EXPR pass (perform const folding).
Optimizing module top_module.

2.10.16. Rerunning OPT passes. (Maybe there is more to do..)

2.10.17. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
Running muxtree optimizer on module \top_module..
  Creating internal representation of mux trees.
  Evaluating internal representation of mux trees.
  Analyzing evaluation results.
Removed 0 multiplexer ports.
<suppressed ~105 debug messages>

2.10.18. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
  Optimizing cells in module \top_module.
Performed a total of 0 changes.

2.10.19. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\top_module'.
Removed a total of 0 cells.

2.10.20. Executing OPT_RMDFF pass (remove dff with constant values).

2.10.21. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \top_module..

2.10.22. Executing OPT_EXPR pass (perform const folding).
Optimizing module top_module.

2.10.23. Finished OPT passes. (There is nothing left to do.)

2.11. Executing WREDUCE pass (reducing word size of cells).
Removed top 24 address bits (of 32) from memory init port top_module.$techmap\common.pb.rx_buf.$meminit$\mem$block_ram_mod.v:46$7016 (common.pb.rx_buf.mem).
Removed top 24 address bits (of 32) from memory init port top_module.$techmap\common.pb.rx_buf.$meminit$\mem$block_ram_mod.v:46$7017 (common.pb.rx_buf.mem).
Removed top 24 address bits (of 32) from memory init port top_module.$techmap\common.pb.rx_buf.$meminit$\mem$block_ram_mod.v:46$7018 (common.pb.rx_buf.mem).
Removed top 24 address bits (of 32) from memory init port top_module.$techmap\common.pb.rx_buf.$meminit$\mem$block_ram_mod.v:46$7019 (common.pb.rx_buf.mem).
Removed top 24 address bits (of 32) from memory init port top_module.$techmap\common.pb.rx_buf.$meminit$\mem$block_ram_mod.v:46$7020 (common.pb.rx_buf.mem).
Removed top 24 address bits (of 32) from memory init port top_module.$techmap\common.pb.rx_buf.$meminit$\mem$block_ram_mod.v:46$7021 (common.pb.rx_buf.mem).
Removed top 24 address bits (of 32) from memory init port top_module.$techmap\common.pb.rx_buf.$meminit$\mem$block_ram_mod.v:46$7022 (common.pb.rx_buf.mem).
Removed top 24 address bits (of 32) from memory init port top_module.$techmap\common.pb.rx_buf.$meminit$\mem$block_ram_mod.v:46$7023 (common.pb.rx_buf.mem).
Removed top 24 address bits (of 32) from memory init port top_module.$techmap\common.pb.rx_buf.$meminit$\mem$block_ram_mod.v:46$7024 (common.pb.rx_buf.mem).
Removed top 24 address bits (of 32) from memory init port top_module.$techmap\common.pb.rx_buf.$meminit$\mem$block_ram_mod.v:46$7025 (common.pb.rx_buf.mem).
Removed top 24 address bits (of 32) from memory init port top_module.$techmap\common.pb.rx_buf.$meminit$\mem$block_ram_mod.v:46$7026 (common.pb.rx_buf.mem).
Removed top 24 address bits (of 32) from memory init port top_module.$techmap\common.pb.rx_buf.$meminit$\mem$block_ram_mod.v:46$7027 (common.pb.rx_buf.mem).
Removed top 24 address bits (of 32) from memory init port top_module.$techmap\common.pb.rx_buf.$meminit$\mem$block_ram_mod.v:46$7028 (common.pb.rx_buf.mem).
Removed top 24 address bits (of 32) from memory init port top_module.$techmap\common.pb.rx_buf.$meminit$\mem$block_ram_mod.v:46$7029 (common.pb.rx_buf.mem).
Removed top 24 address bits (of 32) from memory init port top_module.$techmap\common.pb.rx_buf.$meminit$\mem$block_ram_mod.v:46$7030 (common.pb.rx_buf.mem).
Removed top 24 address bits (of 32) from memory init port top_module.$techmap\common.pb.rx_buf.$meminit$\mem$block_ram_mod.v:46$7031 (common.pb.rx_buf.mem).
Removed top 24 address bits (of 32) from memory init port top_module.$techmap\common.pb.rx_buf.$meminit$\mem$block_ram_mod.v:46$7032 (common.pb.rx_buf.mem).
Removed top 24 address bits (of 32) from memory init port top_module.$techmap\common.pb.rx_buf.$meminit$\mem$block_ram_mod.v:46$7033 (common.pb.rx_buf.mem).
Removed top 24 address bits (of 32) from memory init port top_module.$techmap\common.pb.rx_buf.$meminit$\mem$block_ram_mod.v:46$7034 (common.pb.rx_buf.mem).
Removed top 24 address bits (of 32) from memory init port top_module.$techmap\common.pb.rx_buf.$meminit$\mem$block_ram_mod.v:46$7035 (common.pb.rx_buf.mem).
Removed top 24 address bits (of 32) from memory init port top_module.$techmap\common.pb.rx_buf.$meminit$\mem$block_ram_mod.v:46$7036 (common.pb.rx_buf.mem).
Removed top 24 address bits (of 32) from memory init port top_module.$techmap\common.pb.rx_buf.$meminit$\mem$block_ram_mod.v:46$7037 (common.pb.rx_buf.mem).
Removed top 24 address bits (of 32) from memory init port top_module.$techmap\common.pb.rx_buf.$meminit$\mem$block_ram_mod.v:46$7038 (common.pb.rx_buf.mem).
Removed top 24 address bits (of 32) from memory init port top_module.$techmap\common.pb.rx_buf.$meminit$\mem$block_ram_mod.v:46$7039 (common.pb.rx_buf.mem).
Removed top 24 address bits (of 32) from memory init port top_module.$techmap\common.pb.rx_buf.$meminit$\mem$block_ram_mod.v:46$7040 (common.pb.rx_buf.mem).
Removed top 24 address bits (of 32) from memory init port top_module.$techmap\common.pb.rx_buf.$meminit$\mem$block_ram_mod.v:46$7041 (common.pb.rx_buf.mem).
Removed top 24 address bits (of 32) from memory init port top_module.$techmap\common.pb.rx_buf.$meminit$\mem$block_ram_mod.v:46$7042 (common.pb.rx_buf.mem).
Removed top 24 address bits (of 32) from memory init port top_module.$techmap\common.pb.rx_buf.$meminit$\mem$block_ram_mod.v:46$7043 (common.pb.rx_buf.mem).
Removed top 24 address bits (of 32) from memory init port top_module.$techmap\common.pb.rx_buf.$meminit$\mem$block_ram_mod.v:46$7044 (common.pb.rx_buf.mem).
Removed top 24 address bits (of 32) from memory init port top_module.$techmap\common.pb.rx_buf.$meminit$\mem$block_ram_mod.v:46$7045 (common.pb.rx_buf.mem).
Removed top 24 address bits (of 32) from memory init port top_module.$techmap\common.pb.rx_buf.$meminit$\mem$block_ram_mod.v:46$7046 (common.pb.rx_buf.mem).
Removed top 24 address bits (of 32) from memory init port top_module.$techmap\common.pb.rx_buf.$meminit$\mem$block_ram_mod.v:46$7047 (common.pb.rx_buf.mem).
Removed top 24 address bits (of 32) from memory init port top_module.$techmap\common.pb.rx_buf.$meminit$\mem$block_ram_mod.v:46$7048 (common.pb.rx_buf.mem).
Removed top 24 address bits (of 32) from memory init port top_module.$techmap\common.pb.rx_buf.$meminit$\mem$block_ram_mod.v:46$7049 (common.pb.rx_buf.mem).
Removed top 24 address bits (of 32) from memory init port top_module.$techmap\common.pb.rx_buf.$meminit$\mem$block_ram_mod.v:46$7050 (common.pb.rx_buf.mem).
Removed top 24 address bits (of 32) from memory init port top_module.$techmap\common.pb.rx_buf.$meminit$\mem$block_ram_mod.v:46$7051 (common.pb.rx_buf.mem).
Removed top 24 address bits (of 32) from memory init port top_module.$techmap\common.pb.rx_buf.$meminit$\mem$block_ram_mod.v:46$7052 (common.pb.rx_buf.mem).
Removed top 24 address bits (of 32) from memory init port top_module.$techmap\common.pb.rx_buf.$meminit$\mem$block_ram_mod.v:46$7053 (common.pb.rx_buf.mem).
Removed top 24 address bits (of 32) from memory init port top_module.$techmap\common.pb.rx_buf.$meminit$\mem$block_ram_mod.v:46$7054 (common.pb.rx_buf.mem).
Removed top 24 address bits (of 32) from memory init port top_module.$techmap\common.pb.rx_buf.$meminit$\mem$block_ram_mod.v:46$7055 (common.pb.rx_buf.mem).
Removed top 24 address bits (of 32) from memory init port top_module.$techmap\common.pb.rx_buf.$meminit$\mem$block_ram_mod.v:46$7056 (common.pb.rx_buf.mem).
Removed top 24 address bits (of 32) from memory init port top_module.$techmap\common.pb.rx_buf.$meminit$\mem$block_ram_mod.v:46$7057 (common.pb.rx_buf.mem).
Removed top 24 address bits (of 32) from memory init port top_module.$techmap\common.pb.rx_buf.$meminit$\mem$block_ram_mod.v:46$7058 (common.pb.rx_buf.mem).
Removed top 24 address bits (of 32) from memory init port top_module.$techmap\common.pb.rx_buf.$meminit$\mem$block_ram_mod.v:46$7059 (common.pb.rx_buf.mem).
Removed top 24 address bits (of 32) from memory init port top_module.$techmap\common.pb.rx_buf.$meminit$\mem$block_ram_mod.v:46$7060 (common.pb.rx_buf.mem).
Removed top 24 address bits (of 32) from memory init port top_module.$techmap\common.pb.rx_buf.$meminit$\mem$block_ram_mod.v:46$7061 (common.pb.rx_buf.mem).
Removed top 24 address bits (of 32) from memory init port top_module.$techmap\common.pb.rx_buf.$meminit$\mem$block_ram_mod.v:46$7062 (common.pb.rx_buf.mem).
Removed top 24 address bits (of 32) from memory init port top_module.$techmap\common.pb.rx_buf.$meminit$\mem$block_ram_mod.v:46$7063 (common.pb.rx_buf.mem).
Removed top 24 address bits (of 32) from memory init port top_module.$techmap\common.pb.rx_buf.$meminit$\mem$block_ram_mod.v:46$7064 (common.pb.rx_buf.mem).
Removed top 24 address bits (of 32) from memory init port top_module.$techmap\common.pb.rx_buf.$meminit$\mem$block_ram_mod.v:46$7065 (common.pb.rx_buf.mem).
Removed top 24 address bits (of 32) from memory init port top_module.$techmap\common.pb.rx_buf.$meminit$\mem$block_ram_mod.v:46$7066 (common.pb.rx_buf.mem).
Removed top 24 address bits (of 32) from memory init port top_module.$techmap\common.pb.rx_buf.$meminit$\mem$block_ram_mod.v:46$7067 (common.pb.rx_buf.mem).
Removed top 24 address bits (of 32) from memory init port top_module.$techmap\common.pb.rx_buf.$meminit$\mem$block_ram_mod.v:46$7068 (common.pb.rx_buf.mem).
Removed top 24 address bits (of 32) from memory init port top_module.$techmap\common.pb.rx_buf.$meminit$\mem$block_ram_mod.v:46$7069 (common.pb.rx_buf.mem).
Removed top 24 address bits (of 32) from memory init port top_module.$techmap\common.pb.rx_buf.$meminit$\mem$block_ram_mod.v:46$7070 (common.pb.rx_buf.mem).
Removed top 24 address bits (of 32) from memory init port top_module.$techmap\common.pb.rx_buf.$meminit$\mem$block_ram_mod.v:46$7071 (common.pb.rx_buf.mem).
Removed top 24 address bits (of 32) from memory init port top_module.$techmap\common.pb.rx_buf.$meminit$\mem$block_ram_mod.v:46$7072 (common.pb.rx_buf.mem).
Removed top 24 address bits (of 32) from memory init port top_module.$techmap\common.pb.rx_buf.$meminit$\mem$block_ram_mod.v:46$7073 (common.pb.rx_buf.mem).
Removed top 24 address bits (of 32) from memory init port top_module.$techmap\common.pb.rx_buf.$meminit$\mem$block_ram_mod.v:46$7074 (common.pb.rx_buf.mem).
Removed top 24 address bits (of 32) from memory init port top_module.$techmap\common.pb.rx_buf.$meminit$\mem$block_ram_mod.v:46$7075 (common.pb.rx_buf.mem).
Removed top 24 address bits (of 32) from memory init port top_module.$techmap\common.pb.rx_buf.$meminit$\mem$block_ram_mod.v:46$7076 (common.pb.rx_buf.mem).
Removed top 24 address bits (of 32) from memory init port top_module.$techmap\common.pb.rx_buf.$meminit$\mem$block_ram_mod.v:46$7077 (common.pb.rx_buf.mem).
Removed top 24 address bits (of 32) from memory init port top_module.$techmap\common.pb.rx_buf.$meminit$\mem$block_ram_mod.v:46$7078 (common.pb.rx_buf.mem).
Removed top 24 address bits (of 32) from memory init port top_module.$techmap\common.pb.rx_buf.$meminit$\mem$block_ram_mod.v:46$7079 (common.pb.rx_buf.mem).
Removed top 24 address bits (of 32) from memory init port top_module.$techmap\common.pb.rx_buf.$meminit$\mem$block_ram_mod.v:46$7080 (common.pb.rx_buf.mem).
Removed top 24 address bits (of 32) from memory init port top_module.$techmap\common.pb.rx_buf.$meminit$\mem$block_ram_mod.v:46$7081 (common.pb.rx_buf.mem).
Removed top 24 address bits (of 32) from memory init port top_module.$techmap\common.pb.rx_buf.$meminit$\mem$block_ram_mod.v:46$7082 (common.pb.rx_buf.mem).
Removed top 24 address bits (of 32) from memory init port top_module.$techmap\common.pb.rx_buf.$meminit$\mem$block_ram_mod.v:46$7083 (common.pb.rx_buf.mem).
Removed top 24 address bits (of 32) from memory init port top_module.$techmap\common.pb.rx_buf.$meminit$\mem$block_ram_mod.v:46$7084 (common.pb.rx_buf.mem).
Removed top 24 address bits (of 32) from memory init port top_module.$techmap\common.pb.rx_buf.$meminit$\mem$block_ram_mod.v:46$7085 (common.pb.rx_buf.mem).
Removed top 24 address bits (of 32) from memory init port top_module.$techmap\common.pb.rx_buf.$meminit$\mem$block_ram_mod.v:46$7086 (common.pb.rx_buf.mem).
Removed top 24 address bits (of 32) from memory init port top_module.$techmap\common.pb.rx_buf.$meminit$\mem$block_ram_mod.v:46$7087 (common.pb.rx_buf.mem).
Removed top 24 address bits (of 32) from memory init port top_module.$techmap\common.pb.rx_buf.$meminit$\mem$block_ram_mod.v:46$7088 (common.pb.rx_buf.mem).
Removed top 24 address bits (of 32) from memory init port top_module.$techmap\common.pb.rx_buf.$meminit$\mem$block_ram_mod.v:46$7089 (common.pb.rx_buf.mem).
Removed top 24 address bits (of 32) from memory init port top_module.$techmap\common.pb.rx_buf.$meminit$\mem$block_ram_mod.v:46$7090 (common.pb.rx_buf.mem).
Removed top 24 address bits (of 32) from memory init port top_module.$techmap\common.pb.rx_buf.$meminit$\mem$block_ram_mod.v:46$7091 (common.pb.rx_buf.mem).
Removed top 24 address bits (of 32) from memory init port top_module.$techmap\common.pb.rx_buf.$meminit$\mem$block_ram_mod.v:46$7092 (common.pb.rx_buf.mem).
Removed top 24 address bits (of 32) from memory init port top_module.$techmap\common.pb.rx_buf.$meminit$\mem$block_ram_mod.v:46$7093 (common.pb.rx_buf.mem).
Removed top 24 address bits (of 32) from memory init port top_module.$techmap\common.pb.rx_buf.$meminit$\mem$block_ram_mod.v:46$7094 (common.pb.rx_buf.mem).
Removed top 24 address bits (of 32) from memory init port top_module.$techmap\common.pb.rx_buf.$meminit$\mem$block_ram_mod.v:46$7095 (common.pb.rx_buf.mem).
Removed top 24 address bits (of 32) from memory init port top_module.$techmap\common.pb.rx_buf.$meminit$\mem$block_ram_mod.v:46$7096 (common.pb.rx_buf.mem).
Removed top 24 address bits (of 32) from memory init port top_module.$techmap\common.pb.rx_buf.$meminit$\mem$block_ram_mod.v:46$7097 (common.pb.rx_buf.mem).
Removed top 24 address bits (of 32) from memory init port top_module.$techmap\common.pb.rx_buf.$meminit$\mem$block_ram_mod.v:46$7098 (common.pb.rx_buf.mem).
Removed top 24 address bits (of 32) from memory init port top_module.$techmap\common.pb.rx_buf.$meminit$\mem$block_ram_mod.v:46$7099 (common.pb.rx_buf.mem).
Removed top 24 address bits (of 32) from memory init port top_module.$techmap\common.pb.rx_buf.$meminit$\mem$block_ram_mod.v:46$7100 (common.pb.rx_buf.mem).
Removed top 24 address bits (of 32) from memory init port top_module.$techmap\common.pb.rx_buf.$meminit$\mem$block_ram_mod.v:46$7101 (common.pb.rx_buf.mem).
Removed top 24 address bits (of 32) from memory init port top_module.$techmap\common.pb.rx_buf.$meminit$\mem$block_ram_mod.v:46$7102 (common.pb.rx_buf.mem).
Removed top 24 address bits (of 32) from memory init port top_module.$techmap\common.pb.rx_buf.$meminit$\mem$block_ram_mod.v:46$7103 (common.pb.rx_buf.mem).
Removed top 24 address bits (of 32) from memory init port top_module.$techmap\common.pb.rx_buf.$meminit$\mem$block_ram_mod.v:46$7104 (common.pb.rx_buf.mem).
Removed top 24 address bits (of 32) from memory init port top_module.$techmap\common.pb.rx_buf.$meminit$\mem$block_ram_mod.v:46$7105 (common.pb.rx_buf.mem).
Removed top 24 address bits (of 32) from memory init port top_module.$techmap\common.pb.rx_buf.$meminit$\mem$block_ram_mod.v:46$7106 (common.pb.rx_buf.mem).
Removed top 24 address bits (of 32) from memory init port top_module.$techmap\common.pb.rx_buf.$meminit$\mem$block_ram_mod.v:46$7107 (common.pb.rx_buf.mem).
Removed top 24 address bits (of 32) from memory init port top_module.$techmap\common.pb.rx_buf.$meminit$\mem$block_ram_mod.v:46$7108 (common.pb.rx_buf.mem).
Removed top 24 address bits (of 32) from memory init port top_module.$techmap\common.pb.rx_buf.$meminit$\mem$block_ram_mod.v:46$7109 (common.pb.rx_buf.mem).
Removed top 24 address bits (of 32) from memory init port top_module.$techmap\common.pb.rx_buf.$meminit$\mem$block_ram_mod.v:46$7110 (common.pb.rx_buf.mem).
Removed top 24 address bits (of 32) from memory init port top_module.$techmap\common.pb.rx_buf.$meminit$\mem$block_ram_mod.v:46$7111 (common.pb.rx_buf.mem).
Removed top 24 address bits (of 32) from memory init port top_module.$techmap\common.pb.rx_buf.$meminit$\mem$block_ram_mod.v:46$7112 (common.pb.rx_buf.mem).
Removed top 24 address bits (of 32) from memory init port top_module.$techmap\common.pb.rx_buf.$meminit$\mem$block_ram_mod.v:46$7113 (common.pb.rx_buf.mem).
Removed top 24 address bits (of 32) from memory init port top_module.$techmap\common.pb.rx_buf.$meminit$\mem$block_ram_mod.v:46$7114 (common.pb.rx_buf.mem).
Removed top 24 address bits (of 32) from memory init port top_module.$techmap\common.pb.rx_buf.$meminit$\mem$block_ram_mod.v:46$7115 (common.pb.rx_buf.mem).
Removed top 24 address bits (of 32) from memory init port top_module.$techmap\common.pb.rx_buf.$meminit$\mem$block_ram_mod.v:46$7116 (common.pb.rx_buf.mem).
Removed top 24 address bits (of 32) from memory init port top_module.$techmap\common.pb.rx_buf.$meminit$\mem$block_ram_mod.v:46$7117 (common.pb.rx_buf.mem).
Removed top 24 address bits (of 32) from memory init port top_module.$techmap\common.pb.rx_buf.$meminit$\mem$block_ram_mod.v:46$7118 (common.pb.rx_buf.mem).
Removed top 24 address bits (of 32) from memory init port top_module.$techmap\common.pb.rx_buf.$meminit$\mem$block_ram_mod.v:46$7119 (common.pb.rx_buf.mem).
Removed top 24 address bits (of 32) from memory init port top_module.$techmap\common.pb.rx_buf.$meminit$\mem$block_ram_mod.v:46$7120 (common.pb.rx_buf.mem).
Removed top 24 address bits (of 32) from memory init port top_module.$techmap\common.pb.rx_buf.$meminit$\mem$block_ram_mod.v:46$7121 (common.pb.rx_buf.mem).
Removed top 24 address bits (of 32) from memory init port top_module.$techmap\common.pb.rx_buf.$meminit$\mem$block_ram_mod.v:46$7122 (common.pb.rx_buf.mem).
Removed top 24 address bits (of 32) from memory init port top_module.$techmap\common.pb.rx_buf.$meminit$\mem$block_ram_mod.v:46$7123 (common.pb.rx_buf.mem).
Removed top 24 address bits (of 32) from memory init port top_module.$techmap\common.pb.rx_buf.$meminit$\mem$block_ram_mod.v:46$7124 (common.pb.rx_buf.mem).
Removed top 24 address bits (of 32) from memory init port top_module.$techmap\common.pb.rx_buf.$meminit$\mem$block_ram_mod.v:46$7125 (common.pb.rx_buf.mem).
Removed top 24 address bits (of 32) from memory init port top_module.$techmap\common.pb.rx_buf.$meminit$\mem$block_ram_mod.v:46$7126 (common.pb.rx_buf.mem).
Removed top 24 address bits (of 32) from memory init port top_module.$techmap\common.pb.rx_buf.$meminit$\mem$block_ram_mod.v:46$7127 (common.pb.rx_buf.mem).
Removed top 24 address bits (of 32) from memory init port top_module.$techmap\common.pb.rx_buf.$meminit$\mem$block_ram_mod.v:46$7128 (common.pb.rx_buf.mem).
Removed top 24 address bits (of 32) from memory init port top_module.$techmap\common.pb.rx_buf.$meminit$\mem$block_ram_mod.v:46$7129 (common.pb.rx_buf.mem).
Removed top 24 address bits (of 32) from memory init port top_module.$techmap\common.pb.rx_buf.$meminit$\mem$block_ram_mod.v:46$7130 (common.pb.rx_buf.mem).
Removed top 24 address bits (of 32) from memory init port top_module.$techmap\common.pb.rx_buf.$meminit$\mem$block_ram_mod.v:46$7131 (common.pb.rx_buf.mem).
Removed top 24 address bits (of 32) from memory init port top_module.$techmap\common.pb.rx_buf.$meminit$\mem$block_ram_mod.v:46$7132 (common.pb.rx_buf.mem).
Removed top 24 address bits (of 32) from memory init port top_module.$techmap\common.pb.rx_buf.$meminit$\mem$block_ram_mod.v:46$7133 (common.pb.rx_buf.mem).
Removed top 24 address bits (of 32) from memory init port top_module.$techmap\common.pb.rx_buf.$meminit$\mem$block_ram_mod.v:46$7134 (common.pb.rx_buf.mem).
Removed top 24 address bits (of 32) from memory init port top_module.$techmap\common.pb.rx_buf.$meminit$\mem$block_ram_mod.v:46$7135 (common.pb.rx_buf.mem).
Removed top 24 address bits (of 32) from memory init port top_module.$techmap\common.pb.rx_buf.$meminit$\mem$block_ram_mod.v:46$7136 (common.pb.rx_buf.mem).
Removed top 24 address bits (of 32) from memory init port top_module.$techmap\common.pb.rx_buf.$meminit$\mem$block_ram_mod.v:46$7137 (common.pb.rx_buf.mem).
Removed top 24 address bits (of 32) from memory init port top_module.$techmap\common.pb.rx_buf.$meminit$\mem$block_ram_mod.v:46$7138 (common.pb.rx_buf.mem).
Removed top 24 address bits (of 32) from memory init port top_module.$techmap\common.pb.rx_buf.$meminit$\mem$block_ram_mod.v:46$7139 (common.pb.rx_buf.mem).
Removed top 24 address bits (of 32) from memory init port top_module.$techmap\common.pb.rx_buf.$meminit$\mem$block_ram_mod.v:46$7140 (common.pb.rx_buf.mem).
Removed top 24 address bits (of 32) from memory init port top_module.$techmap\common.pb.rx_buf.$meminit$\mem$block_ram_mod.v:46$7141 (common.pb.rx_buf.mem).
Removed top 24 address bits (of 32) from memory init port top_module.$techmap\common.pb.rx_buf.$meminit$\mem$block_ram_mod.v:46$7142 (common.pb.rx_buf.mem).
Removed top 24 address bits (of 32) from memory init port top_module.$techmap\common.pb.rx_buf.$meminit$\mem$block_ram_mod.v:46$7143 (common.pb.rx_buf.mem).
Removed top 24 address bits (of 32) from memory init port top_module.$techmap\common.pb.rx_buf.$meminit$\mem$block_ram_mod.v:46$7144 (common.pb.rx_buf.mem).
Removed top 24 address bits (of 32) from memory init port top_module.$techmap\common.pb.rx_buf.$meminit$\mem$block_ram_mod.v:46$7145 (common.pb.rx_buf.mem).
Removed top 24 address bits (of 32) from memory init port top_module.$techmap\common.pb.rx_buf.$meminit$\mem$block_ram_mod.v:46$7146 (common.pb.rx_buf.mem).
Removed top 24 address bits (of 32) from memory init port top_module.$techmap\common.pb.rx_buf.$meminit$\mem$block_ram_mod.v:46$7147 (common.pb.rx_buf.mem).
Removed top 24 address bits (of 32) from memory init port top_module.$techmap\common.pb.rx_buf.$meminit$\mem$block_ram_mod.v:46$7148 (common.pb.rx_buf.mem).
Removed top 24 address bits (of 32) from memory init port top_module.$techmap\common.pb.rx_buf.$meminit$\mem$block_ram_mod.v:46$7149 (common.pb.rx_buf.mem).
Removed top 24 address bits (of 32) from memory init port top_module.$techmap\common.pb.rx_buf.$meminit$\mem$block_ram_mod.v:46$7150 (common.pb.rx_buf.mem).
Removed top 24 address bits (of 32) from memory init port top_module.$techmap\common.pb.rx_buf.$meminit$\mem$block_ram_mod.v:46$7151 (common.pb.rx_buf.mem).
Removed top 24 address bits (of 32) from memory init port top_module.$techmap\common.pb.rx_buf.$meminit$\mem$block_ram_mod.v:46$7152 (common.pb.rx_buf.mem).
Removed top 24 address bits (of 32) from memory init port top_module.$techmap\common.pb.rx_buf.$meminit$\mem$block_ram_mod.v:46$7153 (common.pb.rx_buf.mem).
Removed top 24 address bits (of 32) from memory init port top_module.$techmap\common.pb.rx_buf.$meminit$\mem$block_ram_mod.v:46$7154 (common.pb.rx_buf.mem).
Removed top 24 address bits (of 32) from memory init port top_module.$techmap\common.pb.rx_buf.$meminit$\mem$block_ram_mod.v:46$7155 (common.pb.rx_buf.mem).
Removed top 24 address bits (of 32) from memory init port top_module.$techmap\common.pb.rx_buf.$meminit$\mem$block_ram_mod.v:46$7156 (common.pb.rx_buf.mem).
Removed top 24 address bits (of 32) from memory init port top_module.$techmap\common.pb.rx_buf.$meminit$\mem$block_ram_mod.v:46$7157 (common.pb.rx_buf.mem).
Removed top 24 address bits (of 32) from memory init port top_module.$techmap\common.pb.rx_buf.$meminit$\mem$block_ram_mod.v:46$7158 (common.pb.rx_buf.mem).
Removed top 24 address bits (of 32) from memory init port top_module.$techmap\common.pb.rx_buf.$meminit$\mem$block_ram_mod.v:46$7159 (common.pb.rx_buf.mem).
Removed top 24 address bits (of 32) from memory init port top_module.$techmap\common.pb.rx_buf.$meminit$\mem$block_ram_mod.v:46$7160 (common.pb.rx_buf.mem).
Removed top 24 address bits (of 32) from memory init port top_module.$techmap\common.pb.rx_buf.$meminit$\mem$block_ram_mod.v:46$7161 (common.pb.rx_buf.mem).
Removed top 24 address bits (of 32) from memory init port top_module.$techmap\common.pb.rx_buf.$meminit$\mem$block_ram_mod.v:46$7162 (common.pb.rx_buf.mem).
Removed top 24 address bits (of 32) from memory init port top_module.$techmap\common.pb.rx_buf.$meminit$\mem$block_ram_mod.v:46$7163 (common.pb.rx_buf.mem).
Removed top 24 address bits (of 32) from memory init port top_module.$techmap\common.pb.rx_buf.$meminit$\mem$block_ram_mod.v:46$7164 (common.pb.rx_buf.mem).
Removed top 24 address bits (of 32) from memory init port top_module.$techmap\common.pb.rx_buf.$meminit$\mem$block_ram_mod.v:46$7165 (common.pb.rx_buf.mem).
Removed top 24 address bits (of 32) from memory init port top_module.$techmap\common.pb.rx_buf.$meminit$\mem$block_ram_mod.v:46$7166 (common.pb.rx_buf.mem).
Removed top 24 address bits (of 32) from memory init port top_module.$techmap\common.pb.rx_buf.$meminit$\mem$block_ram_mod.v:46$7167 (common.pb.rx_buf.mem).
Removed top 24 address bits (of 32) from memory init port top_module.$techmap\common.pb.rx_buf.$meminit$\mem$block_ram_mod.v:46$7168 (common.pb.rx_buf.mem).
Removed top 24 address bits (of 32) from memory init port top_module.$techmap\common.pb.rx_buf.$meminit$\mem$block_ram_mod.v:46$7169 (common.pb.rx_buf.mem).
Removed top 24 address bits (of 32) from memory init port top_module.$techmap\common.pb.rx_buf.$meminit$\mem$block_ram_mod.v:46$7170 (common.pb.rx_buf.mem).
Removed top 24 address bits (of 32) from memory init port top_module.$techmap\common.pb.rx_buf.$meminit$\mem$block_ram_mod.v:46$7171 (common.pb.rx_buf.mem).
Removed top 24 address bits (of 32) from memory init port top_module.$techmap\common.pb.rx_buf.$meminit$\mem$block_ram_mod.v:46$7172 (common.pb.rx_buf.mem).
Removed top 24 address bits (of 32) from memory init port top_module.$techmap\common.pb.rx_buf.$meminit$\mem$block_ram_mod.v:46$7173 (common.pb.rx_buf.mem).
Removed top 24 address bits (of 32) from memory init port top_module.$techmap\common.pb.rx_buf.$meminit$\mem$block_ram_mod.v:46$7174 (common.pb.rx_buf.mem).
Removed top 24 address bits (of 32) from memory init port top_module.$techmap\common.pb.rx_buf.$meminit$\mem$block_ram_mod.v:46$7175 (common.pb.rx_buf.mem).
Removed top 24 address bits (of 32) from memory init port top_module.$techmap\common.pb.rx_buf.$meminit$\mem$block_ram_mod.v:46$7176 (common.pb.rx_buf.mem).
Removed top 24 address bits (of 32) from memory init port top_module.$techmap\common.pb.rx_buf.$meminit$\mem$block_ram_mod.v:46$7177 (common.pb.rx_buf.mem).
Removed top 24 address bits (of 32) from memory init port top_module.$techmap\common.pb.rx_buf.$meminit$\mem$block_ram_mod.v:46$7178 (common.pb.rx_buf.mem).
Removed top 24 address bits (of 32) from memory init port top_module.$techmap\common.pb.rx_buf.$meminit$\mem$block_ram_mod.v:46$7179 (common.pb.rx_buf.mem).
Removed top 24 address bits (of 32) from memory init port top_module.$techmap\common.pb.rx_buf.$meminit$\mem$block_ram_mod.v:46$7180 (common.pb.rx_buf.mem).
Removed top 24 address bits (of 32) from memory init port top_module.$techmap\common.pb.rx_buf.$meminit$\mem$block_ram_mod.v:46$7181 (common.pb.rx_buf.mem).
Removed top 24 address bits (of 32) from memory init port top_module.$techmap\common.pb.rx_buf.$meminit$\mem$block_ram_mod.v:46$7182 (common.pb.rx_buf.mem).
Removed top 24 address bits (of 32) from memory init port top_module.$techmap\common.pb.rx_buf.$meminit$\mem$block_ram_mod.v:46$7183 (common.pb.rx_buf.mem).
Removed top 24 address bits (of 32) from memory init port top_module.$techmap\common.pb.rx_buf.$meminit$\mem$block_ram_mod.v:46$7184 (common.pb.rx_buf.mem).
Removed top 24 address bits (of 32) from memory init port top_module.$techmap\common.pb.rx_buf.$meminit$\mem$block_ram_mod.v:46$7185 (common.pb.rx_buf.mem).
Removed top 24 address bits (of 32) from memory init port top_module.$techmap\common.pb.rx_buf.$meminit$\mem$block_ram_mod.v:46$7186 (common.pb.rx_buf.mem).
Removed top 24 address bits (of 32) from memory init port top_module.$techmap\common.pb.rx_buf.$meminit$\mem$block_ram_mod.v:46$7187 (common.pb.rx_buf.mem).
Removed top 24 address bits (of 32) from memory init port top_module.$techmap\common.pb.rx_buf.$meminit$\mem$block_ram_mod.v:46$7188 (common.pb.rx_buf.mem).
Removed top 24 address bits (of 32) from memory init port top_module.$techmap\common.pb.rx_buf.$meminit$\mem$block_ram_mod.v:46$7189 (common.pb.rx_buf.mem).
Removed top 24 address bits (of 32) from memory init port top_module.$techmap\common.pb.rx_buf.$meminit$\mem$block_ram_mod.v:46$7190 (common.pb.rx_buf.mem).
Removed top 24 address bits (of 32) from memory init port top_module.$techmap\common.pb.rx_buf.$meminit$\mem$block_ram_mod.v:46$7191 (common.pb.rx_buf.mem).
Removed top 24 address bits (of 32) from memory init port top_module.$techmap\common.pb.rx_buf.$meminit$\mem$block_ram_mod.v:46$7192 (common.pb.rx_buf.mem).
Removed top 24 address bits (of 32) from memory init port top_module.$techmap\common.pb.rx_buf.$meminit$\mem$block_ram_mod.v:46$7193 (common.pb.rx_buf.mem).
Removed top 24 address bits (of 32) from memory init port top_module.$techmap\common.pb.rx_buf.$meminit$\mem$block_ram_mod.v:46$7194 (common.pb.rx_buf.mem).
Removed top 24 address bits (of 32) from memory init port top_module.$techmap\common.pb.rx_buf.$meminit$\mem$block_ram_mod.v:46$7195 (common.pb.rx_buf.mem).
Removed top 24 address bits (of 32) from memory init port top_module.$techmap\common.pb.rx_buf.$meminit$\mem$block_ram_mod.v:46$7196 (common.pb.rx_buf.mem).
Removed top 24 address bits (of 32) from memory init port top_module.$techmap\common.pb.rx_buf.$meminit$\mem$block_ram_mod.v:46$7197 (common.pb.rx_buf.mem).
Removed top 24 address bits (of 32) from memory init port top_module.$techmap\common.pb.rx_buf.$meminit$\mem$block_ram_mod.v:46$7198 (common.pb.rx_buf.mem).
Removed top 24 address bits (of 32) from memory init port top_module.$techmap\common.pb.rx_buf.$meminit$\mem$block_ram_mod.v:46$7199 (common.pb.rx_buf.mem).
Removed top 24 address bits (of 32) from memory init port top_module.$techmap\common.pb.rx_buf.$meminit$\mem$block_ram_mod.v:46$7200 (common.pb.rx_buf.mem).
Removed top 24 address bits (of 32) from memory init port top_module.$techmap\common.pb.rx_buf.$meminit$\mem$block_ram_mod.v:46$7201 (common.pb.rx_buf.mem).
Removed top 24 address bits (of 32) from memory init port top_module.$techmap\common.pb.rx_buf.$meminit$\mem$block_ram_mod.v:46$7202 (common.pb.rx_buf.mem).
Removed top 24 address bits (of 32) from memory init port top_module.$techmap\common.pb.rx_buf.$meminit$\mem$block_ram_mod.v:46$7203 (common.pb.rx_buf.mem).
Removed top 24 address bits (of 32) from memory init port top_module.$techmap\common.pb.rx_buf.$meminit$\mem$block_ram_mod.v:46$7204 (common.pb.rx_buf.mem).
Removed top 24 address bits (of 32) from memory init port top_module.$techmap\common.pb.rx_buf.$meminit$\mem$block_ram_mod.v:46$7205 (common.pb.rx_buf.mem).
Removed top 24 address bits (of 32) from memory init port top_module.$techmap\common.pb.rx_buf.$meminit$\mem$block_ram_mod.v:46$7206 (common.pb.rx_buf.mem).
Removed top 24 address bits (of 32) from memory init port top_module.$techmap\common.pb.rx_buf.$meminit$\mem$block_ram_mod.v:46$7207 (common.pb.rx_buf.mem).
Removed top 24 address bits (of 32) from memory init port top_module.$techmap\common.pb.rx_buf.$meminit$\mem$block_ram_mod.v:46$7208 (common.pb.rx_buf.mem).
Removed top 24 address bits (of 32) from memory init port top_module.$techmap\common.pb.rx_buf.$meminit$\mem$block_ram_mod.v:46$7209 (common.pb.rx_buf.mem).
Removed top 24 address bits (of 32) from memory init port top_module.$techmap\common.pb.rx_buf.$meminit$\mem$block_ram_mod.v:46$7210 (common.pb.rx_buf.mem).
Removed top 24 address bits (of 32) from memory init port top_module.$techmap\common.pb.rx_buf.$meminit$\mem$block_ram_mod.v:46$7211 (common.pb.rx_buf.mem).
Removed top 24 address bits (of 32) from memory init port top_module.$techmap\common.pb.rx_buf.$meminit$\mem$block_ram_mod.v:46$7212 (common.pb.rx_buf.mem).
Removed top 24 address bits (of 32) from memory init port top_module.$techmap\common.pb.rx_buf.$meminit$\mem$block_ram_mod.v:46$7213 (common.pb.rx_buf.mem).
Removed top 24 address bits (of 32) from memory init port top_module.$techmap\common.pb.rx_buf.$meminit$\mem$block_ram_mod.v:46$7214 (common.pb.rx_buf.mem).
Removed top 24 address bits (of 32) from memory init port top_module.$techmap\common.pb.rx_buf.$meminit$\mem$block_ram_mod.v:46$7215 (common.pb.rx_buf.mem).
Removed top 24 address bits (of 32) from memory init port top_module.$techmap\common.pb.rx_buf.$meminit$\mem$block_ram_mod.v:46$7216 (common.pb.rx_buf.mem).
Removed top 24 address bits (of 32) from memory init port top_module.$techmap\common.pb.rx_buf.$meminit$\mem$block_ram_mod.v:46$7217 (common.pb.rx_buf.mem).
Removed top 24 address bits (of 32) from memory init port top_module.$techmap\common.pb.rx_buf.$meminit$\mem$block_ram_mod.v:46$7218 (common.pb.rx_buf.mem).
Removed top 24 address bits (of 32) from memory init port top_module.$techmap\common.pb.rx_buf.$meminit$\mem$block_ram_mod.v:46$7219 (common.pb.rx_buf.mem).
Removed top 24 address bits (of 32) from memory init port top_module.$techmap\common.pb.rx_buf.$meminit$\mem$block_ram_mod.v:46$7220 (common.pb.rx_buf.mem).
Removed top 24 address bits (of 32) from memory init port top_module.$techmap\common.pb.rx_buf.$meminit$\mem$block_ram_mod.v:46$7221 (common.pb.rx_buf.mem).
Removed top 24 address bits (of 32) from memory init port top_module.$techmap\common.pb.rx_buf.$meminit$\mem$block_ram_mod.v:46$7222 (common.pb.rx_buf.mem).
Removed top 24 address bits (of 32) from memory init port top_module.$techmap\common.pb.rx_buf.$meminit$\mem$block_ram_mod.v:46$7223 (common.pb.rx_buf.mem).
Removed top 24 address bits (of 32) from memory init port top_module.$techmap\common.pb.rx_buf.$meminit$\mem$block_ram_mod.v:46$7224 (common.pb.rx_buf.mem).
Removed top 24 address bits (of 32) from memory init port top_module.$techmap\common.pb.rx_buf.$meminit$\mem$block_ram_mod.v:46$7225 (common.pb.rx_buf.mem).
Removed top 24 address bits (of 32) from memory init port top_module.$techmap\common.pb.rx_buf.$meminit$\mem$block_ram_mod.v:46$7226 (common.pb.rx_buf.mem).
Removed top 24 address bits (of 32) from memory init port top_module.$techmap\common.pb.rx_buf.$meminit$\mem$block_ram_mod.v:46$7227 (common.pb.rx_buf.mem).
Removed top 24 address bits (of 32) from memory init port top_module.$techmap\common.pb.rx_buf.$meminit$\mem$block_ram_mod.v:46$7228 (common.pb.rx_buf.mem).
Removed top 24 address bits (of 32) from memory init port top_module.$techmap\common.pb.rx_buf.$meminit$\mem$block_ram_mod.v:46$7229 (common.pb.rx_buf.mem).
Removed top 24 address bits (of 32) from memory init port top_module.$techmap\common.pb.rx_buf.$meminit$\mem$block_ram_mod.v:46$7230 (common.pb.rx_buf.mem).
Removed top 24 address bits (of 32) from memory init port top_module.$techmap\common.pb.rx_buf.$meminit$\mem$block_ram_mod.v:46$7231 (common.pb.rx_buf.mem).
Removed top 24 address bits (of 32) from memory init port top_module.$techmap\common.pb.rx_buf.$meminit$\mem$block_ram_mod.v:46$7232 (common.pb.rx_buf.mem).
Removed top 24 address bits (of 32) from memory init port top_module.$techmap\common.pb.rx_buf.$meminit$\mem$block_ram_mod.v:46$7233 (common.pb.rx_buf.mem).
Removed top 24 address bits (of 32) from memory init port top_module.$techmap\common.pb.rx_buf.$meminit$\mem$block_ram_mod.v:46$7234 (common.pb.rx_buf.mem).
Removed top 24 address bits (of 32) from memory init port top_module.$techmap\common.pb.rx_buf.$meminit$\mem$block_ram_mod.v:46$7235 (common.pb.rx_buf.mem).
Removed top 24 address bits (of 32) from memory init port top_module.$techmap\common.pb.rx_buf.$meminit$\mem$block_ram_mod.v:46$7236 (common.pb.rx_buf.mem).
Removed top 24 address bits (of 32) from memory init port top_module.$techmap\common.pb.rx_buf.$meminit$\mem$block_ram_mod.v:46$7237 (common.pb.rx_buf.mem).
Removed top 24 address bits (of 32) from memory init port top_module.$techmap\common.pb.rx_buf.$meminit$\mem$block_ram_mod.v:46$7238 (common.pb.rx_buf.mem).
Removed top 24 address bits (of 32) from memory init port top_module.$techmap\common.pb.rx_buf.$meminit$\mem$block_ram_mod.v:46$7239 (common.pb.rx_buf.mem).
Removed top 24 address bits (of 32) from memory init port top_module.$techmap\common.pb.rx_buf.$meminit$\mem$block_ram_mod.v:46$7240 (common.pb.rx_buf.mem).
Removed top 24 address bits (of 32) from memory init port top_module.$techmap\common.pb.rx_buf.$meminit$\mem$block_ram_mod.v:46$7241 (common.pb.rx_buf.mem).
Removed top 24 address bits (of 32) from memory init port top_module.$techmap\common.pb.rx_buf.$meminit$\mem$block_ram_mod.v:46$7242 (common.pb.rx_buf.mem).
Removed top 24 address bits (of 32) from memory init port top_module.$techmap\common.pb.rx_buf.$meminit$\mem$block_ram_mod.v:46$7243 (common.pb.rx_buf.mem).
Removed top 24 address bits (of 32) from memory init port top_module.$techmap\common.pb.rx_buf.$meminit$\mem$block_ram_mod.v:46$7244 (common.pb.rx_buf.mem).
Removed top 24 address bits (of 32) from memory init port top_module.$techmap\common.pb.rx_buf.$meminit$\mem$block_ram_mod.v:46$7245 (common.pb.rx_buf.mem).
Removed top 24 address bits (of 32) from memory init port top_module.$techmap\common.pb.rx_buf.$meminit$\mem$block_ram_mod.v:46$7246 (common.pb.rx_buf.mem).
Removed top 24 address bits (of 32) from memory init port top_module.$techmap\common.pb.rx_buf.$meminit$\mem$block_ram_mod.v:46$7247 (common.pb.rx_buf.mem).
Removed top 24 address bits (of 32) from memory init port top_module.$techmap\common.pb.rx_buf.$meminit$\mem$block_ram_mod.v:46$7248 (common.pb.rx_buf.mem).
Removed top 24 address bits (of 32) from memory init port top_module.$techmap\common.pb.rx_buf.$meminit$\mem$block_ram_mod.v:46$7249 (common.pb.rx_buf.mem).
Removed top 24 address bits (of 32) from memory init port top_module.$techmap\common.pb.rx_buf.$meminit$\mem$block_ram_mod.v:46$7250 (common.pb.rx_buf.mem).
Removed top 24 address bits (of 32) from memory init port top_module.$techmap\common.pb.rx_buf.$meminit$\mem$block_ram_mod.v:46$7251 (common.pb.rx_buf.mem).
Removed top 24 address bits (of 32) from memory init port top_module.$techmap\common.pb.rx_buf.$meminit$\mem$block_ram_mod.v:46$7252 (common.pb.rx_buf.mem).
Removed top 24 address bits (of 32) from memory init port top_module.$techmap\common.pb.rx_buf.$meminit$\mem$block_ram_mod.v:46$7253 (common.pb.rx_buf.mem).
Removed top 24 address bits (of 32) from memory init port top_module.$techmap\common.pb.rx_buf.$meminit$\mem$block_ram_mod.v:46$7254 (common.pb.rx_buf.mem).
Removed top 24 address bits (of 32) from memory init port top_module.$techmap\common.pb.rx_buf.$meminit$\mem$block_ram_mod.v:46$7255 (common.pb.rx_buf.mem).
Removed top 24 address bits (of 32) from memory init port top_module.$techmap\common.pb.rx_buf.$meminit$\mem$block_ram_mod.v:46$7256 (common.pb.rx_buf.mem).
Removed top 24 address bits (of 32) from memory init port top_module.$techmap\common.pb.rx_buf.$meminit$\mem$block_ram_mod.v:46$7257 (common.pb.rx_buf.mem).
Removed top 24 address bits (of 32) from memory init port top_module.$techmap\common.pb.rx_buf.$meminit$\mem$block_ram_mod.v:46$7258 (common.pb.rx_buf.mem).
Removed top 24 address bits (of 32) from memory init port top_module.$techmap\common.pb.rx_buf.$meminit$\mem$block_ram_mod.v:46$7259 (common.pb.rx_buf.mem).
Removed top 24 address bits (of 32) from memory init port top_module.$techmap\common.pb.rx_buf.$meminit$\mem$block_ram_mod.v:46$7260 (common.pb.rx_buf.mem).
Removed top 24 address bits (of 32) from memory init port top_module.$techmap\common.pb.rx_buf.$meminit$\mem$block_ram_mod.v:46$7261 (common.pb.rx_buf.mem).
Removed top 24 address bits (of 32) from memory init port top_module.$techmap\common.pb.rx_buf.$meminit$\mem$block_ram_mod.v:46$7262 (common.pb.rx_buf.mem).
Removed top 24 address bits (of 32) from memory init port top_module.$techmap\common.pb.rx_buf.$meminit$\mem$block_ram_mod.v:46$7263 (common.pb.rx_buf.mem).
Removed top 24 address bits (of 32) from memory init port top_module.$techmap\common.pb.rx_buf.$meminit$\mem$block_ram_mod.v:46$7264 (common.pb.rx_buf.mem).
Removed top 24 address bits (of 32) from memory init port top_module.$techmap\common.pb.rx_buf.$meminit$\mem$block_ram_mod.v:46$7265 (common.pb.rx_buf.mem).
Removed top 24 address bits (of 32) from memory init port top_module.$techmap\common.pb.rx_buf.$meminit$\mem$block_ram_mod.v:46$7266 (common.pb.rx_buf.mem).
Removed top 24 address bits (of 32) from memory init port top_module.$techmap\common.pb.rx_buf.$meminit$\mem$block_ram_mod.v:46$7267 (common.pb.rx_buf.mem).
Removed top 24 address bits (of 32) from memory init port top_module.$techmap\common.pb.rx_buf.$meminit$\mem$block_ram_mod.v:46$7268 (common.pb.rx_buf.mem).
Removed top 24 address bits (of 32) from memory init port top_module.$techmap\common.pb.rx_buf.$meminit$\mem$block_ram_mod.v:46$7269 (common.pb.rx_buf.mem).
Removed top 24 address bits (of 32) from memory init port top_module.$techmap\common.pb.rx_buf.$meminit$\mem$block_ram_mod.v:46$7270 (common.pb.rx_buf.mem).
Removed top 24 address bits (of 32) from memory init port top_module.$techmap\common.pb.rx_buf.$meminit$\mem$block_ram_mod.v:46$7271 (common.pb.rx_buf.mem).
Removed top 24 address bits (of 32) from memory init port top_module.$techmap\common.pb.tx_buf.$meminit$\mem$block_ram_mod.v:46$8305 (common.pb.tx_buf.mem).
Removed top 24 address bits (of 32) from memory init port top_module.$techmap\common.pb.tx_buf.$meminit$\mem$block_ram_mod.v:46$8306 (common.pb.tx_buf.mem).
Removed top 24 address bits (of 32) from memory init port top_module.$techmap\common.pb.tx_buf.$meminit$\mem$block_ram_mod.v:46$8307 (common.pb.tx_buf.mem).
Removed top 24 address bits (of 32) from memory init port top_module.$techmap\common.pb.tx_buf.$meminit$\mem$block_ram_mod.v:46$8308 (common.pb.tx_buf.mem).
Removed top 24 address bits (of 32) from memory init port top_module.$techmap\common.pb.tx_buf.$meminit$\mem$block_ram_mod.v:46$8309 (common.pb.tx_buf.mem).
Removed top 24 address bits (of 32) from memory init port top_module.$techmap\common.pb.tx_buf.$meminit$\mem$block_ram_mod.v:46$8310 (common.pb.tx_buf.mem).
Removed top 24 address bits (of 32) from memory init port top_module.$techmap\common.pb.tx_buf.$meminit$\mem$block_ram_mod.v:46$8311 (common.pb.tx_buf.mem).
Removed top 24 address bits (of 32) from memory init port top_module.$techmap\common.pb.tx_buf.$meminit$\mem$block_ram_mod.v:46$8312 (common.pb.tx_buf.mem).
Removed top 24 address bits (of 32) from memory init port top_module.$techmap\common.pb.tx_buf.$meminit$\mem$block_ram_mod.v:46$8313 (common.pb.tx_buf.mem).
Removed top 24 address bits (of 32) from memory init port top_module.$techmap\common.pb.tx_buf.$meminit$\mem$block_ram_mod.v:46$8314 (common.pb.tx_buf.mem).
Removed top 24 address bits (of 32) from memory init port top_module.$techmap\common.pb.tx_buf.$meminit$\mem$block_ram_mod.v:46$8315 (common.pb.tx_buf.mem).
Removed top 24 address bits (of 32) from memory init port top_module.$techmap\common.pb.tx_buf.$meminit$\mem$block_ram_mod.v:46$8316 (common.pb.tx_buf.mem).
Removed top 24 address bits (of 32) from memory init port top_module.$techmap\common.pb.tx_buf.$meminit$\mem$block_ram_mod.v:46$8317 (common.pb.tx_buf.mem).
Removed top 24 address bits (of 32) from memory init port top_module.$techmap\common.pb.tx_buf.$meminit$\mem$block_ram_mod.v:46$8318 (common.pb.tx_buf.mem).
Removed top 24 address bits (of 32) from memory init port top_module.$techmap\common.pb.tx_buf.$meminit$\mem$block_ram_mod.v:46$8319 (common.pb.tx_buf.mem).
Removed top 24 address bits (of 32) from memory init port top_module.$techmap\common.pb.tx_buf.$meminit$\mem$block_ram_mod.v:46$8320 (common.pb.tx_buf.mem).
Removed top 24 address bits (of 32) from memory init port top_module.$techmap\common.pb.tx_buf.$meminit$\mem$block_ram_mod.v:46$8321 (common.pb.tx_buf.mem).
Removed top 24 address bits (of 32) from memory init port top_module.$techmap\common.pb.tx_buf.$meminit$\mem$block_ram_mod.v:46$8322 (common.pb.tx_buf.mem).
Removed top 24 address bits (of 32) from memory init port top_module.$techmap\common.pb.tx_buf.$meminit$\mem$block_ram_mod.v:46$8323 (common.pb.tx_buf.mem).
Removed top 24 address bits (of 32) from memory init port top_module.$techmap\common.pb.tx_buf.$meminit$\mem$block_ram_mod.v:46$8324 (common.pb.tx_buf.mem).
Removed top 24 address bits (of 32) from memory init port top_module.$techmap\common.pb.tx_buf.$meminit$\mem$block_ram_mod.v:46$8325 (common.pb.tx_buf.mem).
Removed top 24 address bits (of 32) from memory init port top_module.$techmap\common.pb.tx_buf.$meminit$\mem$block_ram_mod.v:46$8326 (common.pb.tx_buf.mem).
Removed top 24 address bits (of 32) from memory init port top_module.$techmap\common.pb.tx_buf.$meminit$\mem$block_ram_mod.v:46$8327 (common.pb.tx_buf.mem).
Removed top 24 address bits (of 32) from memory init port top_module.$techmap\common.pb.tx_buf.$meminit$\mem$block_ram_mod.v:46$8328 (common.pb.tx_buf.mem).
Removed top 24 address bits (of 32) from memory init port top_module.$techmap\common.pb.tx_buf.$meminit$\mem$block_ram_mod.v:46$8329 (common.pb.tx_buf.mem).
Removed top 24 address bits (of 32) from memory init port top_module.$techmap\common.pb.tx_buf.$meminit$\mem$block_ram_mod.v:46$8330 (common.pb.tx_buf.mem).
Removed top 24 address bits (of 32) from memory init port top_module.$techmap\common.pb.tx_buf.$meminit$\mem$block_ram_mod.v:46$8331 (common.pb.tx_buf.mem).
Removed top 24 address bits (of 32) from memory init port top_module.$techmap\common.pb.tx_buf.$meminit$\mem$block_ram_mod.v:46$8332 (common.pb.tx_buf.mem).
Removed top 24 address bits (of 32) from memory init port top_module.$techmap\common.pb.tx_buf.$meminit$\mem$block_ram_mod.v:46$8333 (common.pb.tx_buf.mem).
Removed top 24 address bits (of 32) from memory init port top_module.$techmap\common.pb.tx_buf.$meminit$\mem$block_ram_mod.v:46$8334 (common.pb.tx_buf.mem).
Removed top 24 address bits (of 32) from memory init port top_module.$techmap\common.pb.tx_buf.$meminit$\mem$block_ram_mod.v:46$8335 (common.pb.tx_buf.mem).
Removed top 24 address bits (of 32) from memory init port top_module.$techmap\common.pb.tx_buf.$meminit$\mem$block_ram_mod.v:46$8336 (common.pb.tx_buf.mem).
Removed top 24 address bits (of 32) from memory init port top_module.$techmap\common.pb.tx_buf.$meminit$\mem$block_ram_mod.v:46$8337 (common.pb.tx_buf.mem).
Removed top 24 address bits (of 32) from memory init port top_module.$techmap\common.pb.tx_buf.$meminit$\mem$block_ram_mod.v:46$8338 (common.pb.tx_buf.mem).
Removed top 24 address bits (of 32) from memory init port top_module.$techmap\common.pb.tx_buf.$meminit$\mem$block_ram_mod.v:46$8339 (common.pb.tx_buf.mem).
Removed top 24 address bits (of 32) from memory init port top_module.$techmap\common.pb.tx_buf.$meminit$\mem$block_ram_mod.v:46$8340 (common.pb.tx_buf.mem).
Removed top 24 address bits (of 32) from memory init port top_module.$techmap\common.pb.tx_buf.$meminit$\mem$block_ram_mod.v:46$8341 (common.pb.tx_buf.mem).
Removed top 24 address bits (of 32) from memory init port top_module.$techmap\common.pb.tx_buf.$meminit$\mem$block_ram_mod.v:46$8342 (common.pb.tx_buf.mem).
Removed top 24 address bits (of 32) from memory init port top_module.$techmap\common.pb.tx_buf.$meminit$\mem$block_ram_mod.v:46$8343 (common.pb.tx_buf.mem).
Removed top 24 address bits (of 32) from memory init port top_module.$techmap\common.pb.tx_buf.$meminit$\mem$block_ram_mod.v:46$8344 (common.pb.tx_buf.mem).
Removed top 24 address bits (of 32) from memory init port top_module.$techmap\common.pb.tx_buf.$meminit$\mem$block_ram_mod.v:46$8345 (common.pb.tx_buf.mem).
Removed top 24 address bits (of 32) from memory init port top_module.$techmap\common.pb.tx_buf.$meminit$\mem$block_ram_mod.v:46$8346 (common.pb.tx_buf.mem).
Removed top 24 address bits (of 32) from memory init port top_module.$techmap\common.pb.tx_buf.$meminit$\mem$block_ram_mod.v:46$8347 (common.pb.tx_buf.mem).
Removed top 24 address bits (of 32) from memory init port top_module.$techmap\common.pb.tx_buf.$meminit$\mem$block_ram_mod.v:46$8348 (common.pb.tx_buf.mem).
Removed top 24 address bits (of 32) from memory init port top_module.$techmap\common.pb.tx_buf.$meminit$\mem$block_ram_mod.v:46$8349 (common.pb.tx_buf.mem).
Removed top 24 address bits (of 32) from memory init port top_module.$techmap\common.pb.tx_buf.$meminit$\mem$block_ram_mod.v:46$8350 (common.pb.tx_buf.mem).
Removed top 24 address bits (of 32) from memory init port top_module.$techmap\common.pb.tx_buf.$meminit$\mem$block_ram_mod.v:46$8351 (common.pb.tx_buf.mem).
Removed top 24 address bits (of 32) from memory init port top_module.$techmap\common.pb.tx_buf.$meminit$\mem$block_ram_mod.v:46$8352 (common.pb.tx_buf.mem).
Removed top 24 address bits (of 32) from memory init port top_module.$techmap\common.pb.tx_buf.$meminit$\mem$block_ram_mod.v:46$8353 (common.pb.tx_buf.mem).
Removed top 24 address bits (of 32) from memory init port top_module.$techmap\common.pb.tx_buf.$meminit$\mem$block_ram_mod.v:46$8354 (common.pb.tx_buf.mem).
Removed top 24 address bits (of 32) from memory init port top_module.$techmap\common.pb.tx_buf.$meminit$\mem$block_ram_mod.v:46$8355 (common.pb.tx_buf.mem).
Removed top 24 address bits (of 32) from memory init port top_module.$techmap\common.pb.tx_buf.$meminit$\mem$block_ram_mod.v:46$8356 (common.pb.tx_buf.mem).
Removed top 24 address bits (of 32) from memory init port top_module.$techmap\common.pb.tx_buf.$meminit$\mem$block_ram_mod.v:46$8357 (common.pb.tx_buf.mem).
Removed top 24 address bits (of 32) from memory init port top_module.$techmap\common.pb.tx_buf.$meminit$\mem$block_ram_mod.v:46$8358 (common.pb.tx_buf.mem).
Removed top 24 address bits (of 32) from memory init port top_module.$techmap\common.pb.tx_buf.$meminit$\mem$block_ram_mod.v:46$8359 (common.pb.tx_buf.mem).
Removed top 24 address bits (of 32) from memory init port top_module.$techmap\common.pb.tx_buf.$meminit$\mem$block_ram_mod.v:46$8360 (common.pb.tx_buf.mem).
Removed top 24 address bits (of 32) from memory init port top_module.$techmap\common.pb.tx_buf.$meminit$\mem$block_ram_mod.v:46$8361 (common.pb.tx_buf.mem).
Removed top 24 address bits (of 32) from memory init port top_module.$techmap\common.pb.tx_buf.$meminit$\mem$block_ram_mod.v:46$8362 (common.pb.tx_buf.mem).
Removed top 24 address bits (of 32) from memory init port top_module.$techmap\common.pb.tx_buf.$meminit$\mem$block_ram_mod.v:46$8363 (common.pb.tx_buf.mem).
Removed top 24 address bits (of 32) from memory init port top_module.$techmap\common.pb.tx_buf.$meminit$\mem$block_ram_mod.v:46$8364 (common.pb.tx_buf.mem).
Removed top 24 address bits (of 32) from memory init port top_module.$techmap\common.pb.tx_buf.$meminit$\mem$block_ram_mod.v:46$8365 (common.pb.tx_buf.mem).
Removed top 24 address bits (of 32) from memory init port top_module.$techmap\common.pb.tx_buf.$meminit$\mem$block_ram_mod.v:46$8366 (common.pb.tx_buf.mem).
Removed top 24 address bits (of 32) from memory init port top_module.$techmap\common.pb.tx_buf.$meminit$\mem$block_ram_mod.v:46$8367 (common.pb.tx_buf.mem).
Removed top 24 address bits (of 32) from memory init port top_module.$techmap\common.pb.tx_buf.$meminit$\mem$block_ram_mod.v:46$8368 (common.pb.tx_buf.mem).
Removed top 24 address bits (of 32) from memory init port top_module.$techmap\common.pb.tx_buf.$meminit$\mem$block_ram_mod.v:46$8369 (common.pb.tx_buf.mem).
Removed top 24 address bits (of 32) from memory init port top_module.$techmap\common.pb.tx_buf.$meminit$\mem$block_ram_mod.v:46$8370 (common.pb.tx_buf.mem).
Removed top 24 address bits (of 32) from memory init port top_module.$techmap\common.pb.tx_buf.$meminit$\mem$block_ram_mod.v:46$8371 (common.pb.tx_buf.mem).
Removed top 24 address bits (of 32) from memory init port top_module.$techmap\common.pb.tx_buf.$meminit$\mem$block_ram_mod.v:46$8372 (common.pb.tx_buf.mem).
Removed top 24 address bits (of 32) from memory init port top_module.$techmap\common.pb.tx_buf.$meminit$\mem$block_ram_mod.v:46$8373 (common.pb.tx_buf.mem).
Removed top 24 address bits (of 32) from memory init port top_module.$techmap\common.pb.tx_buf.$meminit$\mem$block_ram_mod.v:46$8374 (common.pb.tx_buf.mem).
Removed top 24 address bits (of 32) from memory init port top_module.$techmap\common.pb.tx_buf.$meminit$\mem$block_ram_mod.v:46$8375 (common.pb.tx_buf.mem).
Removed top 24 address bits (of 32) from memory init port top_module.$techmap\common.pb.tx_buf.$meminit$\mem$block_ram_mod.v:46$8376 (common.pb.tx_buf.mem).
Removed top 24 address bits (of 32) from memory init port top_module.$techmap\common.pb.tx_buf.$meminit$\mem$block_ram_mod.v:46$8377 (common.pb.tx_buf.mem).
Removed top 24 address bits (of 32) from memory init port top_module.$techmap\common.pb.tx_buf.$meminit$\mem$block_ram_mod.v:46$8378 (common.pb.tx_buf.mem).
Removed top 24 address bits (of 32) from memory init port top_module.$techmap\common.pb.tx_buf.$meminit$\mem$block_ram_mod.v:46$8379 (common.pb.tx_buf.mem).
Removed top 24 address bits (of 32) from memory init port top_module.$techmap\common.pb.tx_buf.$meminit$\mem$block_ram_mod.v:46$8380 (common.pb.tx_buf.mem).
Removed top 24 address bits (of 32) from memory init port top_module.$techmap\common.pb.tx_buf.$meminit$\mem$block_ram_mod.v:46$8381 (common.pb.tx_buf.mem).
Removed top 24 address bits (of 32) from memory init port top_module.$techmap\common.pb.tx_buf.$meminit$\mem$block_ram_mod.v:46$8382 (common.pb.tx_buf.mem).
Removed top 24 address bits (of 32) from memory init port top_module.$techmap\common.pb.tx_buf.$meminit$\mem$block_ram_mod.v:46$8383 (common.pb.tx_buf.mem).
Removed top 24 address bits (of 32) from memory init port top_module.$techmap\common.pb.tx_buf.$meminit$\mem$block_ram_mod.v:46$8384 (common.pb.tx_buf.mem).
Removed top 24 address bits (of 32) from memory init port top_module.$techmap\common.pb.tx_buf.$meminit$\mem$block_ram_mod.v:46$8385 (common.pb.tx_buf.mem).
Removed top 24 address bits (of 32) from memory init port top_module.$techmap\common.pb.tx_buf.$meminit$\mem$block_ram_mod.v:46$8386 (common.pb.tx_buf.mem).
Removed top 24 address bits (of 32) from memory init port top_module.$techmap\common.pb.tx_buf.$meminit$\mem$block_ram_mod.v:46$8387 (common.pb.tx_buf.mem).
Removed top 24 address bits (of 32) from memory init port top_module.$techmap\common.pb.tx_buf.$meminit$\mem$block_ram_mod.v:46$8388 (common.pb.tx_buf.mem).
Removed top 24 address bits (of 32) from memory init port top_module.$techmap\common.pb.tx_buf.$meminit$\mem$block_ram_mod.v:46$8389 (common.pb.tx_buf.mem).
Removed top 24 address bits (of 32) from memory init port top_module.$techmap\common.pb.tx_buf.$meminit$\mem$block_ram_mod.v:46$8390 (common.pb.tx_buf.mem).
Removed top 24 address bits (of 32) from memory init port top_module.$techmap\common.pb.tx_buf.$meminit$\mem$block_ram_mod.v:46$8391 (common.pb.tx_buf.mem).
Removed top 24 address bits (of 32) from memory init port top_module.$techmap\common.pb.tx_buf.$meminit$\mem$block_ram_mod.v:46$8392 (common.pb.tx_buf.mem).
Removed top 24 address bits (of 32) from memory init port top_module.$techmap\common.pb.tx_buf.$meminit$\mem$block_ram_mod.v:46$8393 (common.pb.tx_buf.mem).
Removed top 24 address bits (of 32) from memory init port top_module.$techmap\common.pb.tx_buf.$meminit$\mem$block_ram_mod.v:46$8394 (common.pb.tx_buf.mem).
Removed top 24 address bits (of 32) from memory init port top_module.$techmap\common.pb.tx_buf.$meminit$\mem$block_ram_mod.v:46$8395 (common.pb.tx_buf.mem).
Removed top 24 address bits (of 32) from memory init port top_module.$techmap\common.pb.tx_buf.$meminit$\mem$block_ram_mod.v:46$8396 (common.pb.tx_buf.mem).
Removed top 24 address bits (of 32) from memory init port top_module.$techmap\common.pb.tx_buf.$meminit$\mem$block_ram_mod.v:46$8397 (common.pb.tx_buf.mem).
Removed top 24 address bits (of 32) from memory init port top_module.$techmap\common.pb.tx_buf.$meminit$\mem$block_ram_mod.v:46$8398 (common.pb.tx_buf.mem).
Removed top 24 address bits (of 32) from memory init port top_module.$techmap\common.pb.tx_buf.$meminit$\mem$block_ram_mod.v:46$8399 (common.pb.tx_buf.mem).
Removed top 24 address bits (of 32) from memory init port top_module.$techmap\common.pb.tx_buf.$meminit$\mem$block_ram_mod.v:46$8400 (common.pb.tx_buf.mem).
Removed top 24 address bits (of 32) from memory init port top_module.$techmap\common.pb.tx_buf.$meminit$\mem$block_ram_mod.v:46$8401 (common.pb.tx_buf.mem).
Removed top 24 address bits (of 32) from memory init port top_module.$techmap\common.pb.tx_buf.$meminit$\mem$block_ram_mod.v:46$8402 (common.pb.tx_buf.mem).
Removed top 24 address bits (of 32) from memory init port top_module.$techmap\common.pb.tx_buf.$meminit$\mem$block_ram_mod.v:46$8403 (common.pb.tx_buf.mem).
Removed top 24 address bits (of 32) from memory init port top_module.$techmap\common.pb.tx_buf.$meminit$\mem$block_ram_mod.v:46$8404 (common.pb.tx_buf.mem).
Removed top 24 address bits (of 32) from memory init port top_module.$techmap\common.pb.tx_buf.$meminit$\mem$block_ram_mod.v:46$8405 (common.pb.tx_buf.mem).
Removed top 24 address bits (of 32) from memory init port top_module.$techmap\common.pb.tx_buf.$meminit$\mem$block_ram_mod.v:46$8406 (common.pb.tx_buf.mem).
Removed top 24 address bits (of 32) from memory init port top_module.$techmap\common.pb.tx_buf.$meminit$\mem$block_ram_mod.v:46$8407 (common.pb.tx_buf.mem).
Removed top 24 address bits (of 32) from memory init port top_module.$techmap\common.pb.tx_buf.$meminit$\mem$block_ram_mod.v:46$8408 (common.pb.tx_buf.mem).
Removed top 24 address bits (of 32) from memory init port top_module.$techmap\common.pb.tx_buf.$meminit$\mem$block_ram_mod.v:46$8409 (common.pb.tx_buf.mem).
Removed top 24 address bits (of 32) from memory init port top_module.$techmap\common.pb.tx_buf.$meminit$\mem$block_ram_mod.v:46$8410 (common.pb.tx_buf.mem).
Removed top 24 address bits (of 32) from memory init port top_module.$techmap\common.pb.tx_buf.$meminit$\mem$block_ram_mod.v:46$8411 (common.pb.tx_buf.mem).
Removed top 24 address bits (of 32) from memory init port top_module.$techmap\common.pb.tx_buf.$meminit$\mem$block_ram_mod.v:46$8412 (common.pb.tx_buf.mem).
Removed top 24 address bits (of 32) from memory init port top_module.$techmap\common.pb.tx_buf.$meminit$\mem$block_ram_mod.v:46$8413 (common.pb.tx_buf.mem).
Removed top 24 address bits (of 32) from memory init port top_module.$techmap\common.pb.tx_buf.$meminit$\mem$block_ram_mod.v:46$8414 (common.pb.tx_buf.mem).
Removed top 24 address bits (of 32) from memory init port top_module.$techmap\common.pb.tx_buf.$meminit$\mem$block_ram_mod.v:46$8415 (common.pb.tx_buf.mem).
Removed top 24 address bits (of 32) from memory init port top_module.$techmap\common.pb.tx_buf.$meminit$\mem$block_ram_mod.v:46$8416 (common.pb.tx_buf.mem).
Removed top 24 address bits (of 32) from memory init port top_module.$techmap\common.pb.tx_buf.$meminit$\mem$block_ram_mod.v:46$8417 (common.pb.tx_buf.mem).
Removed top 24 address bits (of 32) from memory init port top_module.$techmap\common.pb.tx_buf.$meminit$\mem$block_ram_mod.v:46$8418 (common.pb.tx_buf.mem).
Removed top 24 address bits (of 32) from memory init port top_module.$techmap\common.pb.tx_buf.$meminit$\mem$block_ram_mod.v:46$8419 (common.pb.tx_buf.mem).
Removed top 24 address bits (of 32) from memory init port top_module.$techmap\common.pb.tx_buf.$meminit$\mem$block_ram_mod.v:46$8420 (common.pb.tx_buf.mem).
Removed top 24 address bits (of 32) from memory init port top_module.$techmap\common.pb.tx_buf.$meminit$\mem$block_ram_mod.v:46$8421 (common.pb.tx_buf.mem).
Removed top 24 address bits (of 32) from memory init port top_module.$techmap\common.pb.tx_buf.$meminit$\mem$block_ram_mod.v:46$8422 (common.pb.tx_buf.mem).
Removed top 24 address bits (of 32) from memory init port top_module.$techmap\common.pb.tx_buf.$meminit$\mem$block_ram_mod.v:46$8423 (common.pb.tx_buf.mem).
Removed top 24 address bits (of 32) from memory init port top_module.$techmap\common.pb.tx_buf.$meminit$\mem$block_ram_mod.v:46$8424 (common.pb.tx_buf.mem).
Removed top 24 address bits (of 32) from memory init port top_module.$techmap\common.pb.tx_buf.$meminit$\mem$block_ram_mod.v:46$8425 (common.pb.tx_buf.mem).
Removed top 24 address bits (of 32) from memory init port top_module.$techmap\common.pb.tx_buf.$meminit$\mem$block_ram_mod.v:46$8426 (common.pb.tx_buf.mem).
Removed top 24 address bits (of 32) from memory init port top_module.$techmap\common.pb.tx_buf.$meminit$\mem$block_ram_mod.v:46$8427 (common.pb.tx_buf.mem).
Removed top 24 address bits (of 32) from memory init port top_module.$techmap\common.pb.tx_buf.$meminit$\mem$block_ram_mod.v:46$8428 (common.pb.tx_buf.mem).
Removed top 24 address bits (of 32) from memory init port top_module.$techmap\common.pb.tx_buf.$meminit$\mem$block_ram_mod.v:46$8429 (common.pb.tx_buf.mem).
Removed top 24 address bits (of 32) from memory init port top_module.$techmap\common.pb.tx_buf.$meminit$\mem$block_ram_mod.v:46$8430 (common.pb.tx_buf.mem).
Removed top 24 address bits (of 32) from memory init port top_module.$techmap\common.pb.tx_buf.$meminit$\mem$block_ram_mod.v:46$8431 (common.pb.tx_buf.mem).
Removed top 24 address bits (of 32) from memory init port top_module.$techmap\common.pb.tx_buf.$meminit$\mem$block_ram_mod.v:46$8432 (common.pb.tx_buf.mem).
Removed top 24 address bits (of 32) from memory init port top_module.$techmap\common.pb.tx_buf.$meminit$\mem$block_ram_mod.v:46$8433 (common.pb.tx_buf.mem).
Removed top 24 address bits (of 32) from memory init port top_module.$techmap\common.pb.tx_buf.$meminit$\mem$block_ram_mod.v:46$8434 (common.pb.tx_buf.mem).
Removed top 24 address bits (of 32) from memory init port top_module.$techmap\common.pb.tx_buf.$meminit$\mem$block_ram_mod.v:46$8435 (common.pb.tx_buf.mem).
Removed top 24 address bits (of 32) from memory init port top_module.$techmap\common.pb.tx_buf.$meminit$\mem$block_ram_mod.v:46$8436 (common.pb.tx_buf.mem).
Removed top 24 address bits (of 32) from memory init port top_module.$techmap\common.pb.tx_buf.$meminit$\mem$block_ram_mod.v:46$8437 (common.pb.tx_buf.mem).
Removed top 24 address bits (of 32) from memory init port top_module.$techmap\common.pb.tx_buf.$meminit$\mem$block_ram_mod.v:46$8438 (common.pb.tx_buf.mem).
Removed top 24 address bits (of 32) from memory init port top_module.$techmap\common.pb.tx_buf.$meminit$\mem$block_ram_mod.v:46$8439 (common.pb.tx_buf.mem).
Removed top 24 address bits (of 32) from memory init port top_module.$techmap\common.pb.tx_buf.$meminit$\mem$block_ram_mod.v:46$8440 (common.pb.tx_buf.mem).
Removed top 24 address bits (of 32) from memory init port top_module.$techmap\common.pb.tx_buf.$meminit$\mem$block_ram_mod.v:46$8441 (common.pb.tx_buf.mem).
Removed top 24 address bits (of 32) from memory init port top_module.$techmap\common.pb.tx_buf.$meminit$\mem$block_ram_mod.v:46$8442 (common.pb.tx_buf.mem).
Removed top 24 address bits (of 32) from memory init port top_module.$techmap\common.pb.tx_buf.$meminit$\mem$block_ram_mod.v:46$8443 (common.pb.tx_buf.mem).
Removed top 24 address bits (of 32) from memory init port top_module.$techmap\common.pb.tx_buf.$meminit$\mem$block_ram_mod.v:46$8444 (common.pb.tx_buf.mem).
Removed top 24 address bits (of 32) from memory init port top_module.$techmap\common.pb.tx_buf.$meminit$\mem$block_ram_mod.v:46$8445 (common.pb.tx_buf.mem).
Removed top 24 address bits (of 32) from memory init port top_module.$techmap\common.pb.tx_buf.$meminit$\mem$block_ram_mod.v:46$8446 (common.pb.tx_buf.mem).
Removed top 24 address bits (of 32) from memory init port top_module.$techmap\common.pb.tx_buf.$meminit$\mem$block_ram_mod.v:46$8447 (common.pb.tx_buf.mem).
Removed top 24 address bits (of 32) from memory init port top_module.$techmap\common.pb.tx_buf.$meminit$\mem$block_ram_mod.v:46$8448 (common.pb.tx_buf.mem).
Removed top 24 address bits (of 32) from memory init port top_module.$techmap\common.pb.tx_buf.$meminit$\mem$block_ram_mod.v:46$8449 (common.pb.tx_buf.mem).
Removed top 24 address bits (of 32) from memory init port top_module.$techmap\common.pb.tx_buf.$meminit$\mem$block_ram_mod.v:46$8450 (common.pb.tx_buf.mem).
Removed top 24 address bits (of 32) from memory init port top_module.$techmap\common.pb.tx_buf.$meminit$\mem$block_ram_mod.v:46$8451 (common.pb.tx_buf.mem).
Removed top 24 address bits (of 32) from memory init port top_module.$techmap\common.pb.tx_buf.$meminit$\mem$block_ram_mod.v:46$8452 (common.pb.tx_buf.mem).
Removed top 24 address bits (of 32) from memory init port top_module.$techmap\common.pb.tx_buf.$meminit$\mem$block_ram_mod.v:46$8453 (common.pb.tx_buf.mem).
Removed top 24 address bits (of 32) from memory init port top_module.$techmap\common.pb.tx_buf.$meminit$\mem$block_ram_mod.v:46$8454 (common.pb.tx_buf.mem).
Removed top 24 address bits (of 32) from memory init port top_module.$techmap\common.pb.tx_buf.$meminit$\mem$block_ram_mod.v:46$8455 (common.pb.tx_buf.mem).
Removed top 24 address bits (of 32) from memory init port top_module.$techmap\common.pb.tx_buf.$meminit$\mem$block_ram_mod.v:46$8456 (common.pb.tx_buf.mem).
Removed top 24 address bits (of 32) from memory init port top_module.$techmap\common.pb.tx_buf.$meminit$\mem$block_ram_mod.v:46$8457 (common.pb.tx_buf.mem).
Removed top 24 address bits (of 32) from memory init port top_module.$techmap\common.pb.tx_buf.$meminit$\mem$block_ram_mod.v:46$8458 (common.pb.tx_buf.mem).
Removed top 24 address bits (of 32) from memory init port top_module.$techmap\common.pb.tx_buf.$meminit$\mem$block_ram_mod.v:46$8459 (common.pb.tx_buf.mem).
Removed top 24 address bits (of 32) from memory init port top_module.$techmap\common.pb.tx_buf.$meminit$\mem$block_ram_mod.v:46$8460 (common.pb.tx_buf.mem).
Removed top 24 address bits (of 32) from memory init port top_module.$techmap\common.pb.tx_buf.$meminit$\mem$block_ram_mod.v:46$8461 (common.pb.tx_buf.mem).
Removed top 24 address bits (of 32) from memory init port top_module.$techmap\common.pb.tx_buf.$meminit$\mem$block_ram_mod.v:46$8462 (common.pb.tx_buf.mem).
Removed top 24 address bits (of 32) from memory init port top_module.$techmap\common.pb.tx_buf.$meminit$\mem$block_ram_mod.v:46$8463 (common.pb.tx_buf.mem).
Removed top 24 address bits (of 32) from memory init port top_module.$techmap\common.pb.tx_buf.$meminit$\mem$block_ram_mod.v:46$8464 (common.pb.tx_buf.mem).
Removed top 24 address bits (of 32) from memory init port top_module.$techmap\common.pb.tx_buf.$meminit$\mem$block_ram_mod.v:46$8465 (common.pb.tx_buf.mem).
Removed top 24 address bits (of 32) from memory init port top_module.$techmap\common.pb.tx_buf.$meminit$\mem$block_ram_mod.v:46$8466 (common.pb.tx_buf.mem).
Removed top 24 address bits (of 32) from memory init port top_module.$techmap\common.pb.tx_buf.$meminit$\mem$block_ram_mod.v:46$8467 (common.pb.tx_buf.mem).
Removed top 24 address bits (of 32) from memory init port top_module.$techmap\common.pb.tx_buf.$meminit$\mem$block_ram_mod.v:46$8468 (common.pb.tx_buf.mem).
Removed top 24 address bits (of 32) from memory init port top_module.$techmap\common.pb.tx_buf.$meminit$\mem$block_ram_mod.v:46$8469 (common.pb.tx_buf.mem).
Removed top 24 address bits (of 32) from memory init port top_module.$techmap\common.pb.tx_buf.$meminit$\mem$block_ram_mod.v:46$8470 (common.pb.tx_buf.mem).
Removed top 24 address bits (of 32) from memory init port top_module.$techmap\common.pb.tx_buf.$meminit$\mem$block_ram_mod.v:46$8471 (common.pb.tx_buf.mem).
Removed top 24 address bits (of 32) from memory init port top_module.$techmap\common.pb.tx_buf.$meminit$\mem$block_ram_mod.v:46$8472 (common.pb.tx_buf.mem).
Removed top 24 address bits (of 32) from memory init port top_module.$techmap\common.pb.tx_buf.$meminit$\mem$block_ram_mod.v:46$8473 (common.pb.tx_buf.mem).
Removed top 24 address bits (of 32) from memory init port top_module.$techmap\common.pb.tx_buf.$meminit$\mem$block_ram_mod.v:46$8474 (common.pb.tx_buf.mem).
Removed top 24 address bits (of 32) from memory init port top_module.$techmap\common.pb.tx_buf.$meminit$\mem$block_ram_mod.v:46$8475 (common.pb.tx_buf.mem).
Removed top 24 address bits (of 32) from memory init port top_module.$techmap\common.pb.tx_buf.$meminit$\mem$block_ram_mod.v:46$8476 (common.pb.tx_buf.mem).
Removed top 24 address bits (of 32) from memory init port top_module.$techmap\common.pb.tx_buf.$meminit$\mem$block_ram_mod.v:46$8477 (common.pb.tx_buf.mem).
Removed top 24 address bits (of 32) from memory init port top_module.$techmap\common.pb.tx_buf.$meminit$\mem$block_ram_mod.v:46$8478 (common.pb.tx_buf.mem).
Removed top 24 address bits (of 32) from memory init port top_module.$techmap\common.pb.tx_buf.$meminit$\mem$block_ram_mod.v:46$8479 (common.pb.tx_buf.mem).
Removed top 24 address bits (of 32) from memory init port top_module.$techmap\common.pb.tx_buf.$meminit$\mem$block_ram_mod.v:46$8480 (common.pb.tx_buf.mem).
Removed top 24 address bits (of 32) from memory init port top_module.$techmap\common.pb.tx_buf.$meminit$\mem$block_ram_mod.v:46$8481 (common.pb.tx_buf.mem).
Removed top 24 address bits (of 32) from memory init port top_module.$techmap\common.pb.tx_buf.$meminit$\mem$block_ram_mod.v:46$8482 (common.pb.tx_buf.mem).
Removed top 24 address bits (of 32) from memory init port top_module.$techmap\common.pb.tx_buf.$meminit$\mem$block_ram_mod.v:46$8483 (common.pb.tx_buf.mem).
Removed top 24 address bits (of 32) from memory init port top_module.$techmap\common.pb.tx_buf.$meminit$\mem$block_ram_mod.v:46$8484 (common.pb.tx_buf.mem).
Removed top 24 address bits (of 32) from memory init port top_module.$techmap\common.pb.tx_buf.$meminit$\mem$block_ram_mod.v:46$8485 (common.pb.tx_buf.mem).
Removed top 24 address bits (of 32) from memory init port top_module.$techmap\common.pb.tx_buf.$meminit$\mem$block_ram_mod.v:46$8486 (common.pb.tx_buf.mem).
Removed top 24 address bits (of 32) from memory init port top_module.$techmap\common.pb.tx_buf.$meminit$\mem$block_ram_mod.v:46$8487 (common.pb.tx_buf.mem).
Removed top 24 address bits (of 32) from memory init port top_module.$techmap\common.pb.tx_buf.$meminit$\mem$block_ram_mod.v:46$8488 (common.pb.tx_buf.mem).
Removed top 24 address bits (of 32) from memory init port top_module.$techmap\common.pb.tx_buf.$meminit$\mem$block_ram_mod.v:46$8489 (common.pb.tx_buf.mem).
Removed top 24 address bits (of 32) from memory init port top_module.$techmap\common.pb.tx_buf.$meminit$\mem$block_ram_mod.v:46$8490 (common.pb.tx_buf.mem).
Removed top 24 address bits (of 32) from memory init port top_module.$techmap\common.pb.tx_buf.$meminit$\mem$block_ram_mod.v:46$8491 (common.pb.tx_buf.mem).
Removed top 24 address bits (of 32) from memory init port top_module.$techmap\common.pb.tx_buf.$meminit$\mem$block_ram_mod.v:46$8492 (common.pb.tx_buf.mem).
Removed top 24 address bits (of 32) from memory init port top_module.$techmap\common.pb.tx_buf.$meminit$\mem$block_ram_mod.v:46$8493 (common.pb.tx_buf.mem).
Removed top 24 address bits (of 32) from memory init port top_module.$techmap\common.pb.tx_buf.$meminit$\mem$block_ram_mod.v:46$8494 (common.pb.tx_buf.mem).
Removed top 24 address bits (of 32) from memory init port top_module.$techmap\common.pb.tx_buf.$meminit$\mem$block_ram_mod.v:46$8495 (common.pb.tx_buf.mem).
Removed top 24 address bits (of 32) from memory init port top_module.$techmap\common.pb.tx_buf.$meminit$\mem$block_ram_mod.v:46$8496 (common.pb.tx_buf.mem).
Removed top 24 address bits (of 32) from memory init port top_module.$techmap\common.pb.tx_buf.$meminit$\mem$block_ram_mod.v:46$8497 (common.pb.tx_buf.mem).
Removed top 24 address bits (of 32) from memory init port top_module.$techmap\common.pb.tx_buf.$meminit$\mem$block_ram_mod.v:46$8498 (common.pb.tx_buf.mem).
Removed top 24 address bits (of 32) from memory init port top_module.$techmap\common.pb.tx_buf.$meminit$\mem$block_ram_mod.v:46$8499 (common.pb.tx_buf.mem).
Removed top 24 address bits (of 32) from memory init port top_module.$techmap\common.pb.tx_buf.$meminit$\mem$block_ram_mod.v:46$8500 (common.pb.tx_buf.mem).
Removed top 24 address bits (of 32) from memory init port top_module.$techmap\common.pb.tx_buf.$meminit$\mem$block_ram_mod.v:46$8501 (common.pb.tx_buf.mem).
Removed top 24 address bits (of 32) from memory init port top_module.$techmap\common.pb.tx_buf.$meminit$\mem$block_ram_mod.v:46$8502 (common.pb.tx_buf.mem).
Removed top 24 address bits (of 32) from memory init port top_module.$techmap\common.pb.tx_buf.$meminit$\mem$block_ram_mod.v:46$8503 (common.pb.tx_buf.mem).
Removed top 24 address bits (of 32) from memory init port top_module.$techmap\common.pb.tx_buf.$meminit$\mem$block_ram_mod.v:46$8504 (common.pb.tx_buf.mem).
Removed top 24 address bits (of 32) from memory init port top_module.$techmap\common.pb.tx_buf.$meminit$\mem$block_ram_mod.v:46$8505 (common.pb.tx_buf.mem).
Removed top 24 address bits (of 32) from memory init port top_module.$techmap\common.pb.tx_buf.$meminit$\mem$block_ram_mod.v:46$8506 (common.pb.tx_buf.mem).
Removed top 24 address bits (of 32) from memory init port top_module.$techmap\common.pb.tx_buf.$meminit$\mem$block_ram_mod.v:46$8507 (common.pb.tx_buf.mem).
Removed top 24 address bits (of 32) from memory init port top_module.$techmap\common.pb.tx_buf.$meminit$\mem$block_ram_mod.v:46$8508 (common.pb.tx_buf.mem).
Removed top 24 address bits (of 32) from memory init port top_module.$techmap\common.pb.tx_buf.$meminit$\mem$block_ram_mod.v:46$8509 (common.pb.tx_buf.mem).
Removed top 24 address bits (of 32) from memory init port top_module.$techmap\common.pb.tx_buf.$meminit$\mem$block_ram_mod.v:46$8510 (common.pb.tx_buf.mem).
Removed top 24 address bits (of 32) from memory init port top_module.$techmap\common.pb.tx_buf.$meminit$\mem$block_ram_mod.v:46$8511 (common.pb.tx_buf.mem).
Removed top 24 address bits (of 32) from memory init port top_module.$techmap\common.pb.tx_buf.$meminit$\mem$block_ram_mod.v:46$8512 (common.pb.tx_buf.mem).
Removed top 24 address bits (of 32) from memory init port top_module.$techmap\common.pb.tx_buf.$meminit$\mem$block_ram_mod.v:46$8513 (common.pb.tx_buf.mem).
Removed top 24 address bits (of 32) from memory init port top_module.$techmap\common.pb.tx_buf.$meminit$\mem$block_ram_mod.v:46$8514 (common.pb.tx_buf.mem).
Removed top 24 address bits (of 32) from memory init port top_module.$techmap\common.pb.tx_buf.$meminit$\mem$block_ram_mod.v:46$8515 (common.pb.tx_buf.mem).
Removed top 24 address bits (of 32) from memory init port top_module.$techmap\common.pb.tx_buf.$meminit$\mem$block_ram_mod.v:46$8516 (common.pb.tx_buf.mem).
Removed top 24 address bits (of 32) from memory init port top_module.$techmap\common.pb.tx_buf.$meminit$\mem$block_ram_mod.v:46$8517 (common.pb.tx_buf.mem).
Removed top 24 address bits (of 32) from memory init port top_module.$techmap\common.pb.tx_buf.$meminit$\mem$block_ram_mod.v:46$8518 (common.pb.tx_buf.mem).
Removed top 24 address bits (of 32) from memory init port top_module.$techmap\common.pb.tx_buf.$meminit$\mem$block_ram_mod.v:46$8519 (common.pb.tx_buf.mem).
Removed top 24 address bits (of 32) from memory init port top_module.$techmap\common.pb.tx_buf.$meminit$\mem$block_ram_mod.v:46$8520 (common.pb.tx_buf.mem).
Removed top 24 address bits (of 32) from memory init port top_module.$techmap\common.pb.tx_buf.$meminit$\mem$block_ram_mod.v:46$8521 (common.pb.tx_buf.mem).
Removed top 24 address bits (of 32) from memory init port top_module.$techmap\common.pb.tx_buf.$meminit$\mem$block_ram_mod.v:46$8522 (common.pb.tx_buf.mem).
Removed top 24 address bits (of 32) from memory init port top_module.$techmap\common.pb.tx_buf.$meminit$\mem$block_ram_mod.v:46$8523 (common.pb.tx_buf.mem).
Removed top 24 address bits (of 32) from memory init port top_module.$techmap\common.pb.tx_buf.$meminit$\mem$block_ram_mod.v:46$8524 (common.pb.tx_buf.mem).
Removed top 24 address bits (of 32) from memory init port top_module.$techmap\common.pb.tx_buf.$meminit$\mem$block_ram_mod.v:46$8525 (common.pb.tx_buf.mem).
Removed top 24 address bits (of 32) from memory init port top_module.$techmap\common.pb.tx_buf.$meminit$\mem$block_ram_mod.v:46$8526 (common.pb.tx_buf.mem).
Removed top 24 address bits (of 32) from memory init port top_module.$techmap\common.pb.tx_buf.$meminit$\mem$block_ram_mod.v:46$8527 (common.pb.tx_buf.mem).
Removed top 24 address bits (of 32) from memory init port top_module.$techmap\common.pb.tx_buf.$meminit$\mem$block_ram_mod.v:46$8528 (common.pb.tx_buf.mem).
Removed top 24 address bits (of 32) from memory init port top_module.$techmap\common.pb.tx_buf.$meminit$\mem$block_ram_mod.v:46$8529 (common.pb.tx_buf.mem).
Removed top 24 address bits (of 32) from memory init port top_module.$techmap\common.pb.tx_buf.$meminit$\mem$block_ram_mod.v:46$8530 (common.pb.tx_buf.mem).
Removed top 24 address bits (of 32) from memory init port top_module.$techmap\common.pb.tx_buf.$meminit$\mem$block_ram_mod.v:46$8531 (common.pb.tx_buf.mem).
Removed top 24 address bits (of 32) from memory init port top_module.$techmap\common.pb.tx_buf.$meminit$\mem$block_ram_mod.v:46$8532 (common.pb.tx_buf.mem).
Removed top 24 address bits (of 32) from memory init port top_module.$techmap\common.pb.tx_buf.$meminit$\mem$block_ram_mod.v:46$8533 (common.pb.tx_buf.mem).
Removed top 24 address bits (of 32) from memory init port top_module.$techmap\common.pb.tx_buf.$meminit$\mem$block_ram_mod.v:46$8534 (common.pb.tx_buf.mem).
Removed top 24 address bits (of 32) from memory init port top_module.$techmap\common.pb.tx_buf.$meminit$\mem$block_ram_mod.v:46$8535 (common.pb.tx_buf.mem).
Removed top 24 address bits (of 32) from memory init port top_module.$techmap\common.pb.tx_buf.$meminit$\mem$block_ram_mod.v:46$8536 (common.pb.tx_buf.mem).
Removed top 24 address bits (of 32) from memory init port top_module.$techmap\common.pb.tx_buf.$meminit$\mem$block_ram_mod.v:46$8537 (common.pb.tx_buf.mem).
Removed top 24 address bits (of 32) from memory init port top_module.$techmap\common.pb.tx_buf.$meminit$\mem$block_ram_mod.v:46$8538 (common.pb.tx_buf.mem).
Removed top 24 address bits (of 32) from memory init port top_module.$techmap\common.pb.tx_buf.$meminit$\mem$block_ram_mod.v:46$8539 (common.pb.tx_buf.mem).
Removed top 24 address bits (of 32) from memory init port top_module.$techmap\common.pb.tx_buf.$meminit$\mem$block_ram_mod.v:46$8540 (common.pb.tx_buf.mem).
Removed top 24 address bits (of 32) from memory init port top_module.$techmap\common.pb.tx_buf.$meminit$\mem$block_ram_mod.v:46$8541 (common.pb.tx_buf.mem).
Removed top 24 address bits (of 32) from memory init port top_module.$techmap\common.pb.tx_buf.$meminit$\mem$block_ram_mod.v:46$8542 (common.pb.tx_buf.mem).
Removed top 24 address bits (of 32) from memory init port top_module.$techmap\common.pb.tx_buf.$meminit$\mem$block_ram_mod.v:46$8543 (common.pb.tx_buf.mem).
Removed top 24 address bits (of 32) from memory init port top_module.$techmap\common.pb.tx_buf.$meminit$\mem$block_ram_mod.v:46$8544 (common.pb.tx_buf.mem).
Removed top 24 address bits (of 32) from memory init port top_module.$techmap\common.pb.tx_buf.$meminit$\mem$block_ram_mod.v:46$8545 (common.pb.tx_buf.mem).
Removed top 24 address bits (of 32) from memory init port top_module.$techmap\common.pb.tx_buf.$meminit$\mem$block_ram_mod.v:46$8546 (common.pb.tx_buf.mem).
Removed top 24 address bits (of 32) from memory init port top_module.$techmap\common.pb.tx_buf.$meminit$\mem$block_ram_mod.v:46$8547 (common.pb.tx_buf.mem).
Removed top 24 address bits (of 32) from memory init port top_module.$techmap\common.pb.tx_buf.$meminit$\mem$block_ram_mod.v:46$8548 (common.pb.tx_buf.mem).
Removed top 24 address bits (of 32) from memory init port top_module.$techmap\common.pb.tx_buf.$meminit$\mem$block_ram_mod.v:46$8549 (common.pb.tx_buf.mem).
Removed top 24 address bits (of 32) from memory init port top_module.$techmap\common.pb.tx_buf.$meminit$\mem$block_ram_mod.v:46$8550 (common.pb.tx_buf.mem).
Removed top 24 address bits (of 32) from memory init port top_module.$techmap\common.pb.tx_buf.$meminit$\mem$block_ram_mod.v:46$8551 (common.pb.tx_buf.mem).
Removed top 24 address bits (of 32) from memory init port top_module.$techmap\common.pb.tx_buf.$meminit$\mem$block_ram_mod.v:46$8552 (common.pb.tx_buf.mem).
Removed top 24 address bits (of 32) from memory init port top_module.$techmap\common.pb.tx_buf.$meminit$\mem$block_ram_mod.v:46$8553 (common.pb.tx_buf.mem).
Removed top 24 address bits (of 32) from memory init port top_module.$techmap\common.pb.tx_buf.$meminit$\mem$block_ram_mod.v:46$8554 (common.pb.tx_buf.mem).
Removed top 24 address bits (of 32) from memory init port top_module.$techmap\common.pb.tx_buf.$meminit$\mem$block_ram_mod.v:46$8555 (common.pb.tx_buf.mem).
Removed top 24 address bits (of 32) from memory init port top_module.$techmap\common.pb.tx_buf.$meminit$\mem$block_ram_mod.v:46$8556 (common.pb.tx_buf.mem).
Removed top 24 address bits (of 32) from memory init port top_module.$techmap\common.pb.tx_buf.$meminit$\mem$block_ram_mod.v:46$8557 (common.pb.tx_buf.mem).
Removed top 24 address bits (of 32) from memory init port top_module.$techmap\common.pb.tx_buf.$meminit$\mem$block_ram_mod.v:46$8558 (common.pb.tx_buf.mem).
Removed top 24 address bits (of 32) from memory init port top_module.$techmap\common.pb.tx_buf.$meminit$\mem$block_ram_mod.v:46$8559 (common.pb.tx_buf.mem).
Removed top 24 address bits (of 32) from memory init port top_module.$techmap\common.pb.tx_buf.$meminit$\mem$block_ram_mod.v:46$8560 (common.pb.tx_buf.mem).
Removed top 31 bits (of 32) from port B of cell top_module.$techmap\common.led_blink.$sub$led_blink_mod.v:60$9250 ($sub).
Removed top 31 bits (of 32) from port B of cell top_module.$techmap\common.led_blink.$sub$led_blink_mod.v:51$9248 ($sub).
Removed top 6 bits (of 8) from port B of cell top_module.$techmap\common.pb.$procmux$14606_CMP0 ($eq).
Removed top 2 bits (of 3) from mux cell top_module.$techmap\common.pb.$procmux$14474 ($mux).
Removed top 2 bits (of 3) from port B of cell top_module.$techmap\common.pb.$procmux$14280_CMP0 ($eq).
Removed top 1 bits (of 3) from port B of cell top_module.$techmap\common.pb.$procmux$14261_CMP0 ($eq).
Removed top 1 bits (of 3) from port B of cell top_module.$techmap\common.pb.$procmux$13500_CMP0 ($eq).
Removed top 7 bits (of 8) from port B of cell top_module.$techmap\common.pb.$procmux$13003_CMP0 ($eq).
Removed top 5 bits (of 8) from port B of cell top_module.$techmap\common.pb.$procmux$13000_CMP0 ($eq).
Removed top 5 bits (of 8) from port B of cell top_module.$techmap\common.pb.$procmux$12996_CMP0 ($eq).
Removed top 5 bits (of 8) from port B of cell top_module.$techmap\common.pb.$procmux$12993_CMP0 ($eq).
Removed top 6 bits (of 8) from port B of cell top_module.$techmap\common.pb.$procmux$10688_CMP0 ($eq).
Removed top 6 bits (of 8) from port B of cell top_module.$techmap\common.pb.$procmux$10687_CMP0 ($eq).
Removed top 5 bits (of 8) from port B of cell top_module.$techmap\common.pb.$procmux$10686_CMP0 ($eq).
Removed top 5 bits (of 8) from port B of cell top_module.$techmap\common.pb.$procmux$10685_CMP0 ($eq).
Removed top 5 bits (of 8) from port B of cell top_module.$techmap\common.pb.$procmux$10684_CMP0 ($eq).
Removed top 5 bits (of 8) from port B of cell top_module.$techmap\common.pb.$procmux$10683_CMP0 ($eq).
Removed top 31 bits (of 32) from port B of cell top_module.$techmap\common.pb.$add$profibus_phy_mod.v:1059$6266 ($add).
Removed top 8 bits (of 32) from port Y of cell top_module.$techmap\common.pb.$add$profibus_phy_mod.v:1059$6266 ($add).
Removed top 31 bits (of 32) from port B of cell top_module.$techmap\common.pb.$add$profibus_phy_mod.v:999$6258 ($add).
Removed top 24 bits (of 32) from port Y of cell top_module.$techmap\common.pb.$add$profibus_phy_mod.v:999$6258 ($add).
Removed top 31 bits (of 32) from port B of cell top_module.$techmap\common.pb.$add$profibus_phy_mod.v:997$6256 ($add).
Removed top 24 bits (of 32) from port Y of cell top_module.$techmap\common.pb.$add$profibus_phy_mod.v:997$6256 ($add).
Removed top 30 bits (of 32) from port B of cell top_module.$techmap\common.pb.$ge$profibus_phy_mod.v:991$6252 ($ge).
Removed top 28 bits (of 32) from port B of cell top_module.$techmap\common.pb.$le$profibus_phy_mod.v:988$6248 ($le).
Removed top 30 bits (of 32) from port B of cell top_module.$techmap\common.pb.$ge$profibus_phy_mod.v:988$6247 ($ge).
Removed top 7 bits (of 8) from port B of cell top_module.$techmap\common.pb.$eq$profibus_phy_mod.v:970$6215 ($eq).
Removed top 31 bits (of 32) from port B of cell top_module.$techmap\common.pb.$add$profibus_phy_mod.v:891$5910 ($add).
Removed top 24 bits (of 32) from port Y of cell top_module.$techmap\common.pb.$add$profibus_phy_mod.v:891$5910 ($add).
Removed top 30 bits (of 32) from port B of cell top_module.$techmap\common.pb.$ge$profibus_phy_mod.v:712$5636 ($ge).
Removed top 31 bits (of 32) from port B of cell top_module.$techmap\common.pb.$add$profibus_phy_mod.v:690$5537 ($add).
Removed top 24 bits (of 32) from port Y of cell top_module.$techmap\common.pb.$add$profibus_phy_mod.v:690$5537 ($add).
Removed top 31 bits (of 32) from port B of cell top_module.$techmap\common.pb.$add$profibus_phy_mod.v:522$5404 ($add).
Removed top 24 bits (of 32) from port Y of cell top_module.$techmap\common.pb.$add$profibus_phy_mod.v:522$5404 ($add).
Removed top 31 bits (of 32) from port B of cell top_module.$techmap\common.pb.$add$profibus_phy_mod.v:356$5384 ($add).
Removed top 24 bits (of 32) from port Y of cell top_module.$techmap\common.pb.$add$profibus_phy_mod.v:356$5384 ($add).
Removed top 31 bits (of 32) from port B of cell top_module.$techmap\common.pb.$add$profibus_phy_mod.v:308$5383 ($add).
Removed top 24 bits (of 32) from port Y of cell top_module.$techmap\common.pb.$add$profibus_phy_mod.v:308$5383 ($add).
Removed top 7 bits (of 8) from mux cell top_module.$techmap\common.pb.spirx_lencalc.$procmux$14751 ($mux).
Removed top 1 bits (of 2) from port B of cell top_module.$techmap\common.pb.spirx_lencalc.$procmux$14749_CMP0 ($eq).
Removed top 29 bits (of 32) from port B of cell top_module.$techmap\common.pb.spirx_lencalc.$add$profibus_phy_mod.v:157$5343 ($add).
Removed top 24 bits (of 32) from port Y of cell top_module.$techmap\common.pb.spirx_lencalc.$add$profibus_phy_mod.v:157$5343 ($add).
Removed top 24 bits (of 32) from port B of cell top_module.$techmap\common.pb.spirx_lencalc.$le$profibus_phy_mod.v:144$5340 ($le).
Removed top 29 bits (of 32) from port B of cell top_module.$techmap\common.pb.spirx_lencalc.$ge$profibus_phy_mod.v:144$5339 ($ge).
Removed top 1 bits (of 8) from port B of cell top_module.$techmap\common.pb.spirx_lencalc.$eq$profibus_phy_mod.v:118$5335 ($eq).
Removed top 3 bits (of 8) from port B of cell top_module.$techmap\common.pb.spirx_lencalc.$eq$profibus_phy_mod.v:114$5334 ($eq).
Removed top 28 bits (of 32) from port B of cell top_module.$techmap\common.pb.spi.$ge$spi_slave_mod.v:138$6487 ($ge).
Removed top 31 bits (of 32) from port B of cell top_module.$techmap\common.pb.spi.$add$spi_slave_mod.v:134$6486 ($add).
Removed top 26 bits (of 32) from port Y of cell top_module.$techmap\common.pb.spi.$add$spi_slave_mod.v:134$6486 ($add).
Removed top 28 bits (of 32) from port B of cell top_module.$techmap\common.pb.spi.$lt$spi_slave_mod.v:125$6483 ($lt).
Removed top 8 bits (of 9) from FF cell top_module.$techmap\common.pb.rx_buf.$procdff$15807 ($dff).
Removed cell top_module.$techmap\common.pb.rx_buf.$procmux$14888 ($mux).
Removed cell top_module.$techmap\common.pb.rx_buf.$procmux$14886 ($mux).
Removed top 7 bits (of 8) from FF cell top_module.$techmap\common.pb.tx_buf.$procdff$15802 ($dff).
Removed cell top_module.$techmap\common.pb.tx_buf.$procmux$14882 ($mux).
Removed cell top_module.$techmap\common.pb.tx_buf.$procmux$14880 ($mux).
Removed top 1 bits (of 3) from FF cell top_module.$techmap\common.pb.spi.sync_ss.$procdff$15838 ($dff).
Removed top 1 bits (of 3) from FF cell top_module.$techmap\common.pb.spi.sync_mosi.$procdff$15838 ($dff).
Removed top 30 bits (of 32) from port B of cell top_module.$techmap\common.pb.uart.tx_mod.$sub$uart_mod.v:356$9124 ($sub).
Removed top 1 bits (of 4) from port B of cell top_module.$techmap\common.pb.uart.tx_mod.$eq$uart_mod.v:351$9116 ($eq).
Removed top 1 bits (of 4) from port B of cell top_module.$techmap\common.pb.uart.tx_mod.$eq$uart_mod.v:350$9114 ($eq).
Removed top 1 bits (of 4) from port B of cell top_module.$techmap\common.pb.uart.tx_mod.$eq$uart_mod.v:349$9112 ($eq).
Removed top 1 bits (of 4) from port B of cell top_module.$techmap\common.pb.uart.tx_mod.$eq$uart_mod.v:348$9110 ($eq).
Removed top 2 bits (of 4) from port B of cell top_module.$techmap\common.pb.uart.tx_mod.$eq$uart_mod.v:347$9108 ($eq).
Removed top 2 bits (of 4) from port B of cell top_module.$techmap\common.pb.uart.tx_mod.$eq$uart_mod.v:346$9107 ($eq).
Removed top 3 bits (of 4) from port B of cell top_module.$techmap\common.pb.uart.tx_mod.$eq$uart_mod.v:341$9105 ($eq).
Removed top 31 bits (of 32) from port B of cell top_module.$techmap\common.pb.uart.tx_mod.$add$uart_mod.v:335$9104 ($add).
Removed top 28 bits (of 32) from port Y of cell top_module.$techmap\common.pb.uart.tx_mod.$add$uart_mod.v:335$9104 ($add).
Removed top 1 bits (of 3) from FF cell top_module.$techmap\common.pb.uart.sync_rx.$procdff$15838 ($dff).
Removed top 29 bits (of 32) from port B of cell top_module.$techmap\common.pb.uart.rx_mod.$procmux$15148_CMP0 ($eq).
Removed top 30 bits (of 32) from port B of cell top_module.$techmap\common.pb.uart.rx_mod.$procmux$15128_CMP0 ($eq).
Removed top 31 bits (of 32) from port B of cell top_module.$techmap\common.pb.uart.rx_mod.$procmux$15106_CMP0 ($eq).
Removed top 29 bits (of 32) from port B of cell top_module.$techmap\common.pb.uart.rx_mod.$procmux$15082_CMP0 ($eq).
Removed top 30 bits (of 32) from port B of cell top_module.$techmap\common.pb.uart.rx_mod.$procmux$15038_CMP0 ($eq).
Removed top 29 bits (of 32) from port B of cell top_module.$techmap\common.pb.uart.rx_mod.$procmux$15015_CMP0 ($eq).
Removed top 29 bits (of 32) from port B of cell top_module.$techmap\common.pb.uart.rx_mod.$procmux$14994_CMP0 ($eq).
Removed top 30 bits (of 32) from port B of cell top_module.$techmap\common.pb.uart.rx_mod.$sub$uart_mod.v:216$9199 ($sub).
Removed top 1 bits (of 4) from port B of cell top_module.$techmap\common.pb.uart.rx_mod.$eq$uart_mod.v:211$9191 ($eq).
Removed top 1 bits (of 4) from port B of cell top_module.$techmap\common.pb.uart.rx_mod.$eq$uart_mod.v:210$9189 ($eq).
Removed top 1 bits (of 4) from port B of cell top_module.$techmap\common.pb.uart.rx_mod.$eq$uart_mod.v:209$9187 ($eq).
Removed top 1 bits (of 4) from port B of cell top_module.$techmap\common.pb.uart.rx_mod.$eq$uart_mod.v:208$9185 ($eq).
Removed top 2 bits (of 4) from port B of cell top_module.$techmap\common.pb.uart.rx_mod.$eq$uart_mod.v:207$9183 ($eq).
Removed top 2 bits (of 4) from port B of cell top_module.$techmap\common.pb.uart.rx_mod.$eq$uart_mod.v:206$9182 ($eq).
Removed top 3 bits (of 4) from port B of cell top_module.$techmap\common.pb.uart.rx_mod.$eq$uart_mod.v:200$9180 ($eq).
Removed top 31 bits (of 32) from port B of cell top_module.$techmap\common.pb.uart.rx_mod.$add$uart_mod.v:195$9179 ($add).
Removed top 28 bits (of 32) from port Y of cell top_module.$techmap\common.pb.uart.rx_mod.$add$uart_mod.v:195$9179 ($add).
Removed top 31 bits (of 32) from port B of cell top_module.$techmap\common.pb.uart.tx_mod.symclk.$add$uart_mod.v:74$18 ($add).
Removed top 8 bits (of 32) from port Y of cell top_module.$techmap\common.pb.uart.tx_mod.symclk.$add$uart_mod.v:74$18 ($add).
Removed top 31 bits (of 32) from port B of cell top_module.$techmap\common.pb.uart.rx_mod.symclk.$sub$uart_mod.v:83$22 ($sub).
Removed top 1 bits (of 24) from port A of cell top_module.$techmap\common.pb.uart.rx_mod.symclk.$sub$uart_mod.v:78$19 ($sub).
Removed top 31 bits (of 32) from port B of cell top_module.$techmap\common.pb.uart.rx_mod.symclk.$sub$uart_mod.v:78$19 ($sub).
Removed top 31 bits (of 32) from port B of cell top_module.$techmap\common.pb.uart.rx_mod.symclk.$add$uart_mod.v:74$18 ($add).
Removed top 8 bits (of 32) from port Y of cell top_module.$techmap\common.pb.uart.rx_mod.symclk.$add$uart_mod.v:74$18 ($add).
Removed top 8 bits (of 32) from mux cell top_module.$techmap\common.pb.uart.rx_mod.symclk.$ternary$uart_mod.v:61$14 ($mux).
Removed top 29 bits (of 32) from port B of cell top_module.$techmap\common.pb.uart.rx_mod.symclk.$ge$uart_mod.v:61$12 ($ge).
Removed top 8 bits (of 32) from wire top_module.$techmap\common.pb.$add$profibus_phy_mod.v:1059$6266_Y.
Removed top 24 bits (of 32) from wire top_module.$techmap\common.pb.$add$profibus_phy_mod.v:522$5404_Y.
Removed top 24 bits (of 32) from wire top_module.$techmap\common.pb.$add$profibus_phy_mod.v:690$5537_Y.
Removed top 2 bits (of 3) from wire top_module.$techmap\common.pb.$procmux$14474_Y.
Removed top 26 bits (of 32) from wire top_module.$techmap\common.pb.spi.$add$spi_slave_mod.v:134$6486_Y.
Removed top 24 bits (of 32) from wire top_module.$techmap\common.pb.spirx_lencalc.$add$profibus_phy_mod.v:157$5343_Y.
Removed top 28 bits (of 32) from wire top_module.$techmap\common.pb.uart.rx_mod.$add$uart_mod.v:195$9179_Y.
Removed top 8 bits (of 32) from wire top_module.$techmap\common.pb.uart.rx_mod.symclk.$add$uart_mod.v:74$18_Y.
Removed top 20 bits (of 32) from wire top_module.$techmap\common.pb.uart.rx_mod.symclk.$sub$uart_mod.v:83$22_Y.
Removed top 28 bits (of 32) from wire top_module.$techmap\common.pb.uart.tx_mod.$add$uart_mod.v:335$9104_Y.
Removed top 8 bits (of 32) from wire top_module.$techmap\common.pb.uart.tx_mod.symclk.$add$uart_mod.v:74$18_Y.
Removed top 6 bits (of 9) from wire top_module.common.pb.rx_buf.rd_data1.
Removed top 1 bits (of 24) from wire top_module.common.pb.uart.rx_mod.symclk.clks_per_sym_half.
Removed top 23 bits (of 24) from wire top_module.common.pb.uart.rx_mod.symclk.clks_per_sym_limited.

2.12. Executing PEEPOPT pass (run peephole optimizers).

2.13. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \top_module..
Removed 0 unused cells and 21 unused wires.
<suppressed ~1 debug messages>

2.14. Executing SHARE pass (SAT-based resource sharing).

2.15. Executing TECHMAP pass (map to technology primitives).

2.15.1. Executing Verilog-2005 frontend: /home/mb/fpga-toolchain/yosys/bin/../share/yosys/cmp2lut.v
Parsing Verilog input from `/home/mb/fpga-toolchain/yosys/bin/../share/yosys/cmp2lut.v' to AST representation.
Generating RTLIL representation for module `\_90_lut_cmp_'.
Successfully finished Verilog frontend.

2.15.2. Continuing TECHMAP pass.
Using template $paramod$d87a48a4cd82717ae6bd57e6fe5ce90d87c44016\_90_lut_cmp_ for cells of type $eq.
Using template $paramod$169bae89c32dcc6f3626d16cf9f47ceb469145db\_90_lut_cmp_ for cells of type $eq.
Using template $paramod$d31416a5863a8a220e16d7940a75ab70541ab32a\_90_lut_cmp_ for cells of type $eq.
Using template $paramod$4cde4291caf5aa85a196975f3624151774a86d78\_90_lut_cmp_ for cells of type $eq.
Using template $paramod$5652dda64580ddd7861fd245e644fd33eae2e158\_90_lut_cmp_ for cells of type $eq.
Using template $paramod$5b7c8f37cb386acdf3ce7e528c09e6d15eb51b72\_90_lut_cmp_ for cells of type $eq.
Using template $paramod$6816abac91a51b405c3de5bceb2855c03dd44485\_90_lut_cmp_ for cells of type $eq.
Using template $paramod$99e5b0ecd4c7f9fb6cd3a733593eba894c42613f\_90_lut_cmp_ for cells of type $eq.
Using template $paramod$5c2d7617d568809e504489b04c3cf382857f302a\_90_lut_cmp_ for cells of type $eq.
Using template $paramod$dc6060208f0369ff43b26b7eee8e43bf61e4b025\_90_lut_cmp_ for cells of type $eq.
Using template $paramod$ed69233d74549f287b72a59633b9a76ab6bcc119\_90_lut_cmp_ for cells of type $eq.
Using template $paramod$df71d3c5c306636e78c1ede81ccfd95a4d222f85\_90_lut_cmp_ for cells of type $eq.
Using template $paramod$64fdb727b8fb55a4fe9731fe5b6468d06ea5e6e3\_90_lut_cmp_ for cells of type $eq.
Using template $paramod$efc71e781fe178e08e0b73b60d007d65bb528021\_90_lut_cmp_ for cells of type $eq.
Using template $paramod$8c0aa91d4db8741c9947d7a0de6c875d8dfddc39\_90_lut_cmp_ for cells of type $eq.
Using template $paramod$b2c078492117e804fad9a0ec69f4ef95c8e4fc36\_90_lut_cmp_ for cells of type $eq.
Using template $paramod$71de91d27376199a7ef88a0ac0b14252f100e8e2\_90_lut_cmp_ for cells of type $eq.
Using template $paramod$d0a69964f9ce54b3124cbdb498a7c3bb278370d8\_90_lut_cmp_ for cells of type $eq.
Using template $paramod$947b4e84b41c8268c0b3f732cf601a46e109cf2f\_90_lut_cmp_ for cells of type $eq.
No more expansions possible.
<suppressed ~991 debug messages>

2.16. Executing OPT_EXPR pass (perform const folding).
Optimizing module top_module.

2.17. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \top_module..
Removed 0 unused cells and 90 unused wires.
<suppressed ~1 debug messages>

2.18. Executing ALUMACC pass (create $alu and $macc cells).
Extracting $alu and $macc cells in module top_module:
  creating $macc model for $techmap\common.led_blink.$sub$led_blink_mod.v:51$9248 ($sub).
  creating $macc model for $techmap\common.led_blink.$sub$led_blink_mod.v:60$9250 ($sub).
  creating $macc model for $techmap\common.pb.$add$profibus_phy_mod.v:1059$6266 ($add).
  creating $macc model for $techmap\common.pb.$add$profibus_phy_mod.v:308$5383 ($add).
  creating $macc model for $techmap\common.pb.$add$profibus_phy_mod.v:356$5384 ($add).
  creating $macc model for $techmap\common.pb.$add$profibus_phy_mod.v:522$5404 ($add).
  creating $macc model for $techmap\common.pb.$add$profibus_phy_mod.v:690$5537 ($add).
  creating $macc model for $techmap\common.pb.$add$profibus_phy_mod.v:809$5660 ($add).
  creating $macc model for $techmap\common.pb.$add$profibus_phy_mod.v:891$5910 ($add).
  creating $macc model for $techmap\common.pb.$add$profibus_phy_mod.v:997$6256 ($add).
  creating $macc model for $techmap\common.pb.$add$profibus_phy_mod.v:999$6258 ($add).
  creating $macc model for $techmap\common.pb.spi.$add$spi_slave_mod.v:134$6486 ($add).
  creating $macc model for $techmap\common.pb.spirx_lencalc.$add$profibus_phy_mod.v:157$5343 ($add).
  creating $macc model for $techmap\common.pb.uart.rx_mod.$add$uart_mod.v:195$9179 ($add).
  creating $macc model for $techmap\common.pb.uart.rx_mod.$sub$uart_mod.v:216$9199 ($sub).
  creating $macc model for $techmap\common.pb.uart.rx_mod.symclk.$add$uart_mod.v:74$18 ($add).
  creating $macc model for $techmap\common.pb.uart.rx_mod.symclk.$sub$uart_mod.v:78$19 ($sub).
  creating $macc model for $techmap\common.pb.uart.rx_mod.symclk.$sub$uart_mod.v:83$22 ($sub).
  creating $macc model for $techmap\common.pb.uart.tx_mod.$add$uart_mod.v:335$9104 ($add).
  creating $macc model for $techmap\common.pb.uart.tx_mod.$sub$uart_mod.v:356$9124 ($sub).
  creating $macc model for $techmap\common.pb.uart.tx_mod.symclk.$add$uart_mod.v:74$18 ($add).
  creating $alu model for $macc $techmap\common.pb.uart.tx_mod.symclk.$add$uart_mod.v:74$18.
  creating $alu model for $macc $techmap\common.pb.uart.tx_mod.$sub$uart_mod.v:356$9124.
  creating $alu model for $macc $techmap\common.pb.uart.tx_mod.$add$uart_mod.v:335$9104.
  creating $alu model for $macc $techmap\common.pb.uart.rx_mod.symclk.$sub$uart_mod.v:83$22.
  creating $alu model for $macc $techmap\common.pb.uart.rx_mod.symclk.$sub$uart_mod.v:78$19.
  creating $alu model for $macc $techmap\common.pb.uart.rx_mod.symclk.$add$uart_mod.v:74$18.
  creating $alu model for $macc $techmap\common.pb.uart.rx_mod.$sub$uart_mod.v:216$9199.
  creating $alu model for $macc $techmap\common.pb.uart.rx_mod.$add$uart_mod.v:195$9179.
  creating $alu model for $macc $techmap\common.pb.spirx_lencalc.$add$profibus_phy_mod.v:157$5343.
  creating $alu model for $macc $techmap\common.pb.spi.$add$spi_slave_mod.v:134$6486.
  creating $alu model for $macc $techmap\common.pb.$add$profibus_phy_mod.v:999$6258.
  creating $alu model for $macc $techmap\common.pb.$add$profibus_phy_mod.v:997$6256.
  creating $alu model for $macc $techmap\common.pb.$add$profibus_phy_mod.v:891$5910.
  creating $alu model for $macc $techmap\common.pb.$add$profibus_phy_mod.v:809$5660.
  creating $alu model for $macc $techmap\common.pb.$add$profibus_phy_mod.v:690$5537.
  creating $alu model for $macc $techmap\common.pb.$add$profibus_phy_mod.v:522$5404.
  creating $alu model for $macc $techmap\common.pb.$add$profibus_phy_mod.v:356$5384.
  creating $alu model for $macc $techmap\common.pb.$add$profibus_phy_mod.v:308$5383.
  creating $alu model for $macc $techmap\common.pb.$add$profibus_phy_mod.v:1059$6266.
  creating $alu model for $macc $techmap\common.led_blink.$sub$led_blink_mod.v:60$9250.
  creating $alu model for $macc $techmap\common.led_blink.$sub$led_blink_mod.v:51$9248.
  creating $alu model for $techmap\common.pb.$ge$profibus_phy_mod.v:483$5395 ($ge): new $alu
  creating $alu model for $techmap\common.pb.$ge$profibus_phy_mod.v:661$5534 ($ge): new $alu
  creating $alu model for $techmap\common.pb.$ge$profibus_phy_mod.v:712$5636 ($ge): new $alu
  creating $alu model for $techmap\common.pb.$ge$profibus_phy_mod.v:988$6247 ($ge): new $alu
  creating $alu model for $techmap\common.pb.$ge$profibus_phy_mod.v:991$6252 ($ge): new $alu
  creating $alu model for $techmap\common.pb.$le$profibus_phy_mod.v:988$6248 ($le): new $alu
  creating $alu model for $techmap\common.pb.$lt$profibus_phy_mod.v:1058$6265 ($lt): new $alu
  creating $alu model for $techmap\common.pb.spi.$ge$spi_slave_mod.v:138$6487 ($ge): new $alu
  creating $alu model for $techmap\common.pb.spi.$lt$spi_slave_mod.v:125$6483 ($lt): merged with $techmap\common.pb.spi.$ge$spi_slave_mod.v:138$6487.
  creating $alu model for $techmap\common.pb.spirx_lencalc.$ge$profibus_phy_mod.v:144$5339 ($ge): new $alu
  creating $alu model for $techmap\common.pb.spirx_lencalc.$le$profibus_phy_mod.v:144$5340 ($le): new $alu
  creating $alu model for $techmap\common.pb.uart.rx_mod.symclk.$ge$uart_mod.v:61$12 ($ge): new $alu
  creating $alu model for $techmap\common.pb.uart.rx_mod.symclk.$ge$uart_mod.v:83$23 ($ge): new $alu
  creating $alu model for $techmap\common.pb.uart.tx_mod.symclk.$ge$uart_mod.v:83$23 ($ge): new $alu
  creating $alu model for $techmap\common.pb.$procmux$10687_CMP0 ($eq): merged with $techmap\common.pb.$ge$profibus_phy_mod.v:991$6252.
  creating $alu model for $techmap\common.pb.$procmux$10688_CMP0 ($eq): merged with $techmap\common.pb.$ge$profibus_phy_mod.v:988$6247.
  creating $alu cell for $techmap\common.pb.uart.tx_mod.symclk.$ge$uart_mod.v:83$23: $auto$alumacc.cc:474:replace_alu$15981
  creating $alu cell for $techmap\common.pb.uart.rx_mod.symclk.$ge$uart_mod.v:83$23: $auto$alumacc.cc:474:replace_alu$15994
  creating $alu cell for $techmap\common.pb.uart.rx_mod.symclk.$ge$uart_mod.v:61$12: $auto$alumacc.cc:474:replace_alu$16007
  creating $alu cell for $techmap\common.pb.spirx_lencalc.$le$profibus_phy_mod.v:144$5340: $auto$alumacc.cc:474:replace_alu$16016
  creating $alu cell for $techmap\common.pb.spirx_lencalc.$ge$profibus_phy_mod.v:144$5339: $auto$alumacc.cc:474:replace_alu$16025
  creating $alu cell for $techmap\common.pb.spi.$ge$spi_slave_mod.v:138$6487, $techmap\common.pb.spi.$lt$spi_slave_mod.v:125$6483: $auto$alumacc.cc:474:replace_alu$16034
  creating $alu cell for $techmap\common.pb.$lt$profibus_phy_mod.v:1058$6265: $auto$alumacc.cc:474:replace_alu$16047
  creating $alu cell for $techmap\common.pb.$le$profibus_phy_mod.v:988$6248: $auto$alumacc.cc:474:replace_alu$16052
  creating $alu cell for $techmap\common.pb.$ge$profibus_phy_mod.v:991$6252, $techmap\common.pb.$procmux$10687_CMP0: $auto$alumacc.cc:474:replace_alu$16065
  creating $alu cell for $techmap\common.pb.$ge$profibus_phy_mod.v:988$6247, $techmap\common.pb.$procmux$10688_CMP0: $auto$alumacc.cc:474:replace_alu$16074
  creating $alu cell for $techmap\common.pb.$ge$profibus_phy_mod.v:712$5636: $auto$alumacc.cc:474:replace_alu$16083
  creating $alu cell for $techmap\common.pb.$ge$profibus_phy_mod.v:661$5534: $auto$alumacc.cc:474:replace_alu$16092
  creating $alu cell for $techmap\common.pb.$ge$profibus_phy_mod.v:483$5395: $auto$alumacc.cc:474:replace_alu$16105
  creating $alu cell for $techmap\common.led_blink.$sub$led_blink_mod.v:51$9248: $auto$alumacc.cc:474:replace_alu$16118
  creating $alu cell for $techmap\common.led_blink.$sub$led_blink_mod.v:60$9250: $auto$alumacc.cc:474:replace_alu$16121
  creating $alu cell for $techmap\common.pb.$add$profibus_phy_mod.v:1059$6266: $auto$alumacc.cc:474:replace_alu$16124
  creating $alu cell for $techmap\common.pb.$add$profibus_phy_mod.v:308$5383: $auto$alumacc.cc:474:replace_alu$16127
  creating $alu cell for $techmap\common.pb.$add$profibus_phy_mod.v:356$5384: $auto$alumacc.cc:474:replace_alu$16130
  creating $alu cell for $techmap\common.pb.$add$profibus_phy_mod.v:522$5404: $auto$alumacc.cc:474:replace_alu$16133
  creating $alu cell for $techmap\common.pb.$add$profibus_phy_mod.v:690$5537: $auto$alumacc.cc:474:replace_alu$16136
  creating $alu cell for $techmap\common.pb.$add$profibus_phy_mod.v:809$5660: $auto$alumacc.cc:474:replace_alu$16139
  creating $alu cell for $techmap\common.pb.$add$profibus_phy_mod.v:891$5910: $auto$alumacc.cc:474:replace_alu$16142
  creating $alu cell for $techmap\common.pb.$add$profibus_phy_mod.v:997$6256: $auto$alumacc.cc:474:replace_alu$16145
  creating $alu cell for $techmap\common.pb.$add$profibus_phy_mod.v:999$6258: $auto$alumacc.cc:474:replace_alu$16148
  creating $alu cell for $techmap\common.pb.spi.$add$spi_slave_mod.v:134$6486: $auto$alumacc.cc:474:replace_alu$16151
  creating $alu cell for $techmap\common.pb.spirx_lencalc.$add$profibus_phy_mod.v:157$5343: $auto$alumacc.cc:474:replace_alu$16154
  creating $alu cell for $techmap\common.pb.uart.rx_mod.$add$uart_mod.v:195$9179: $auto$alumacc.cc:474:replace_alu$16157
  creating $alu cell for $techmap\common.pb.uart.rx_mod.$sub$uart_mod.v:216$9199: $auto$alumacc.cc:474:replace_alu$16160
  creating $alu cell for $techmap\common.pb.uart.rx_mod.symclk.$add$uart_mod.v:74$18: $auto$alumacc.cc:474:replace_alu$16163
  creating $alu cell for $techmap\common.pb.uart.rx_mod.symclk.$sub$uart_mod.v:78$19: $auto$alumacc.cc:474:replace_alu$16166
  creating $alu cell for $techmap\common.pb.uart.rx_mod.symclk.$sub$uart_mod.v:83$22: $auto$alumacc.cc:474:replace_alu$16169
  creating $alu cell for $techmap\common.pb.uart.tx_mod.$add$uart_mod.v:335$9104: $auto$alumacc.cc:474:replace_alu$16172
  creating $alu cell for $techmap\common.pb.uart.tx_mod.$sub$uart_mod.v:356$9124: $auto$alumacc.cc:474:replace_alu$16175
  creating $alu cell for $techmap\common.pb.uart.tx_mod.symclk.$add$uart_mod.v:74$18: $auto$alumacc.cc:474:replace_alu$16178
  created 34 $alu and 0 $macc cells.

2.19. Executing OPT pass (performing simple optimizations).

2.19.1. Executing OPT_EXPR pass (perform const folding).
Optimizing module top_module.
<suppressed ~1 debug messages>

2.19.2. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\top_module'.
Removed a total of 0 cells.

2.19.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
Running muxtree optimizer on module \top_module..
  Creating internal representation of mux trees.
  Evaluating internal representation of mux trees.
  Analyzing evaluation results.
Removed 0 multiplexer ports.
<suppressed ~101 debug messages>

2.19.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
  Optimizing cells in module \top_module.
    New input vector for $reduce_or cell $auto$alumacc.cc:509:replace_alu$16005: { $auto$rtlil.cc:1832:Not$16004 $auto$rtlil.cc:1835:ReduceAnd$16002 }
    New input vector for $reduce_or cell $auto$alumacc.cc:509:replace_alu$16014: { $auto$rtlil.cc:1832:Not$16011 $auto$rtlil.cc:1835:ReduceAnd$16013 }
    New input vector for $reduce_or cell $auto$alumacc.cc:509:replace_alu$16063: { $auto$rtlil.cc:1832:Not$16062 $auto$rtlil.cc:1835:ReduceAnd$16060 }
    New input vector for $reduce_or cell $auto$alumacc.cc:509:replace_alu$16072: { $auto$rtlil.cc:1832:Not$16069 $auto$rtlil.cc:1835:ReduceAnd$16071 }
    New input vector for $reduce_or cell $auto$alumacc.cc:509:replace_alu$16081: { $auto$rtlil.cc:1832:Not$16078 $auto$rtlil.cc:1835:ReduceAnd$16080 }
    New input vector for $reduce_or cell $auto$alumacc.cc:509:replace_alu$16090: { $auto$rtlil.cc:1832:Not$16087 $auto$rtlil.cc:1835:ReduceAnd$16089 }
    New input vector for $reduce_or cell $auto$alumacc.cc:509:replace_alu$16116: { $auto$rtlil.cc:1832:Not$16115 $auto$rtlil.cc:1835:ReduceAnd$16113 }
    New input vector for $reduce_or cell $auto$opt_reduce.cc:126:opt_mux$15875: { $auto$rtlil.cc:1835:ReduceAnd$16071 $techmap\common.pb.$procmux$10686_CMP $techmap\common.pb.$procmux$10685_CMP $techmap\common.pb.$procmux$10684_CMP $techmap\common.pb.$eq$profibus_phy_mod.v:970$6215_Y $techmap\common.pb.$eq$profibus_phy_mod.v:964$6192_Y $auto$rtlil.cc:1835:ReduceAnd$16080 }
    New input vector for $reduce_or cell $auto$alumacc.cc:509:replace_alu$16041: { $auto$rtlil.cc:1832:Not$16038 $auto$rtlil.cc:1835:ReduceAnd$16040 }
    New input vector for $reduce_and cell $auto$alumacc.cc:64:get_eq$16079: { $auto$alumacc.cc:490:replace_alu$16075 [0] $auto$alumacc.cc:490:replace_alu$16075 [1] $auto$alumacc.cc:490:replace_alu$16075 [2] $auto$alumacc.cc:490:replace_alu$16075 [3] $auto$alumacc.cc:490:replace_alu$16075 [4] $auto$alumacc.cc:490:replace_alu$16075 [5] $auto$alumacc.cc:490:replace_alu$16075 [6] $auto$alumacc.cc:490:replace_alu$16075 [7] }
    New input vector for $reduce_and cell $auto$alumacc.cc:64:get_eq$16070: { $auto$alumacc.cc:490:replace_alu$16066 [0] $auto$alumacc.cc:490:replace_alu$16066 [1] $auto$alumacc.cc:490:replace_alu$16066 [2] $auto$alumacc.cc:490:replace_alu$16066 [3] $auto$alumacc.cc:490:replace_alu$16066 [4] $auto$alumacc.cc:490:replace_alu$16066 [5] $auto$alumacc.cc:490:replace_alu$16066 [6] $auto$alumacc.cc:490:replace_alu$16066 [7] }
    New input vector for $reduce_and cell $auto$alumacc.cc:64:get_eq$15988: { $auto$alumacc.cc:490:replace_alu$15982 [0] $auto$alumacc.cc:490:replace_alu$15982 [1] $auto$alumacc.cc:490:replace_alu$15982 [2] $auto$alumacc.cc:490:replace_alu$15982 [3] $auto$alumacc.cc:490:replace_alu$15982 [4] $auto$alumacc.cc:490:replace_alu$15982 [5] $auto$alumacc.cc:490:replace_alu$15982 [6] $auto$alumacc.cc:490:replace_alu$15982 [7] $auto$alumacc.cc:490:replace_alu$15982 [8] $auto$alumacc.cc:490:replace_alu$15982 [9] $auto$alumacc.cc:490:replace_alu$15982 [10] $auto$alumacc.cc:490:replace_alu$15982 [11] $auto$alumacc.cc:490:replace_alu$15982 [12] $auto$alumacc.cc:490:replace_alu$15982 [13] $auto$alumacc.cc:490:replace_alu$15982 [14] $auto$alumacc.cc:490:replace_alu$15982 [15] $auto$alumacc.cc:490:replace_alu$15982 [16] $auto$alumacc.cc:490:replace_alu$15982 [17] $auto$alumacc.cc:490:replace_alu$15982 [18] $auto$alumacc.cc:490:replace_alu$15982 [19] $auto$alumacc.cc:490:replace_alu$15982 [20] $auto$alumacc.cc:490:replace_alu$15982 [21] $auto$alumacc.cc:490:replace_alu$15982 [22] $auto$alumacc.cc:490:replace_alu$15982 [23] $auto$alumacc.cc:490:replace_alu$15982 [24] $auto$alumacc.cc:490:replace_alu$15982 [25] $auto$alumacc.cc:490:replace_alu$15982 [26] $auto$alumacc.cc:490:replace_alu$15982 [27] $auto$alumacc.cc:490:replace_alu$15982 [28] $auto$alumacc.cc:490:replace_alu$15982 [29] $auto$alumacc.cc:490:replace_alu$15982 [30] $auto$alumacc.cc:490:replace_alu$15982 [31] }
    New input vector for $reduce_and cell $auto$alumacc.cc:64:get_eq$16001: { $auto$alumacc.cc:490:replace_alu$15995 [0] $auto$alumacc.cc:490:replace_alu$15995 [1] $auto$alumacc.cc:490:replace_alu$15995 [2] $auto$alumacc.cc:490:replace_alu$15995 [3] $auto$alumacc.cc:490:replace_alu$15995 [4] $auto$alumacc.cc:490:replace_alu$15995 [5] $auto$alumacc.cc:490:replace_alu$15995 [6] $auto$alumacc.cc:490:replace_alu$15995 [7] $auto$alumacc.cc:490:replace_alu$15995 [8] $auto$alumacc.cc:490:replace_alu$15995 [9] $auto$alumacc.cc:490:replace_alu$15995 [10] $auto$alumacc.cc:490:replace_alu$15995 [11] $auto$alumacc.cc:490:replace_alu$15995 [12] $auto$alumacc.cc:490:replace_alu$15995 [13] $auto$alumacc.cc:490:replace_alu$15995 [14] $auto$alumacc.cc:490:replace_alu$15995 [15] $auto$alumacc.cc:490:replace_alu$15995 [16] $auto$alumacc.cc:490:replace_alu$15995 [17] $auto$alumacc.cc:490:replace_alu$15995 [18] $auto$alumacc.cc:490:replace_alu$15995 [19] $auto$alumacc.cc:490:replace_alu$15995 [20] $auto$alumacc.cc:490:replace_alu$15995 [21] $auto$alumacc.cc:490:replace_alu$15995 [22] $auto$alumacc.cc:490:replace_alu$15995 [23] $auto$alumacc.cc:490:replace_alu$15995 [24] $auto$alumacc.cc:490:replace_alu$15995 [25] $auto$alumacc.cc:490:replace_alu$15995 [26] $auto$alumacc.cc:490:replace_alu$15995 [27] $auto$alumacc.cc:490:replace_alu$15995 [28] $auto$alumacc.cc:490:replace_alu$15995 [29] $auto$alumacc.cc:490:replace_alu$15995 [30] $auto$alumacc.cc:490:replace_alu$15995 [31] }
    New input vector for $reduce_and cell $auto$alumacc.cc:64:get_eq$16012: { $auto$alumacc.cc:490:replace_alu$16008 [0] $auto$alumacc.cc:490:replace_alu$16008 [1] $auto$alumacc.cc:490:replace_alu$16008 [2] $auto$alumacc.cc:490:replace_alu$16008 [3] $auto$alumacc.cc:490:replace_alu$16008 [4] $auto$alumacc.cc:490:replace_alu$16008 [5] $auto$alumacc.cc:490:replace_alu$16008 [6] $auto$alumacc.cc:490:replace_alu$16008 [7] $auto$alumacc.cc:490:replace_alu$16008 [8] $auto$alumacc.cc:490:replace_alu$16008 [9] $auto$alumacc.cc:490:replace_alu$16008 [10] $auto$alumacc.cc:490:replace_alu$16008 [11] $auto$alumacc.cc:490:replace_alu$16008 [12] $auto$alumacc.cc:490:replace_alu$16008 [13] $auto$alumacc.cc:490:replace_alu$16008 [14] $auto$alumacc.cc:490:replace_alu$16008 [15] $auto$alumacc.cc:490:replace_alu$16008 [16] $auto$alumacc.cc:490:replace_alu$16008 [17] $auto$alumacc.cc:490:replace_alu$16008 [18] $auto$alumacc.cc:490:replace_alu$16008 [19] $auto$alumacc.cc:490:replace_alu$16008 [20] $auto$alumacc.cc:490:replace_alu$16008 [21] $auto$alumacc.cc:490:replace_alu$16008 [22] $auto$alumacc.cc:490:replace_alu$16008 [23] }
    New input vector for $reduce_and cell $auto$alumacc.cc:64:get_eq$16021: { $auto$alumacc.cc:490:replace_alu$16017 [0] $auto$alumacc.cc:490:replace_alu$16017 [1] $auto$alumacc.cc:490:replace_alu$16017 [2] $auto$alumacc.cc:490:replace_alu$16017 [3] $auto$alumacc.cc:490:replace_alu$16017 [4] $auto$alumacc.cc:490:replace_alu$16017 [5] $auto$alumacc.cc:490:replace_alu$16017 [6] $auto$alumacc.cc:490:replace_alu$16017 [7] }
    New input vector for $reduce_and cell $auto$alumacc.cc:64:get_eq$16030: { $auto$alumacc.cc:490:replace_alu$16026 [0] $auto$alumacc.cc:490:replace_alu$16026 [1] $auto$alumacc.cc:490:replace_alu$16026 [2] $auto$alumacc.cc:490:replace_alu$16026 [3] $auto$alumacc.cc:490:replace_alu$16026 [4] $auto$alumacc.cc:490:replace_alu$16026 [5] $auto$alumacc.cc:490:replace_alu$16026 [6] $auto$alumacc.cc:490:replace_alu$16026 [7] }
    New input vector for $reduce_and cell $auto$alumacc.cc:64:get_eq$16039: { $auto$alumacc.cc:490:replace_alu$16035 [0] $auto$alumacc.cc:490:replace_alu$16035 [1] $auto$alumacc.cc:490:replace_alu$16035 [2] $auto$alumacc.cc:490:replace_alu$16035 [3] $auto$alumacc.cc:490:replace_alu$16035 [4] $auto$alumacc.cc:490:replace_alu$16035 [5] }
    New input vector for $reduce_and cell $auto$alumacc.cc:64:get_eq$16059: { $auto$alumacc.cc:490:replace_alu$16053 [0] $auto$alumacc.cc:490:replace_alu$16053 [1] $auto$alumacc.cc:490:replace_alu$16053 [2] $auto$alumacc.cc:490:replace_alu$16053 [3] $auto$alumacc.cc:490:replace_alu$16053 [4] $auto$alumacc.cc:490:replace_alu$16053 [5] $auto$alumacc.cc:490:replace_alu$16053 [6] $auto$alumacc.cc:490:replace_alu$16053 [7] }
    New input vector for $reduce_and cell $auto$alumacc.cc:64:get_eq$16088: { $auto$alumacc.cc:490:replace_alu$16084 [0] $auto$alumacc.cc:490:replace_alu$16084 [1] $auto$alumacc.cc:490:replace_alu$16084 [2] $auto$alumacc.cc:490:replace_alu$16084 [3] $auto$alumacc.cc:490:replace_alu$16084 [4] $auto$alumacc.cc:490:replace_alu$16084 [5] $auto$alumacc.cc:490:replace_alu$16084 [6] $auto$alumacc.cc:490:replace_alu$16084 [7] }
    New input vector for $reduce_and cell $auto$alumacc.cc:64:get_eq$16099: { $auto$alumacc.cc:490:replace_alu$16093 [0] $auto$alumacc.cc:490:replace_alu$16093 [1] $auto$alumacc.cc:490:replace_alu$16093 [2] $auto$alumacc.cc:490:replace_alu$16093 [3] $auto$alumacc.cc:490:replace_alu$16093 [4] $auto$alumacc.cc:490:replace_alu$16093 [5] $auto$alumacc.cc:490:replace_alu$16093 [6] $auto$alumacc.cc:490:replace_alu$16093 [7] }
    New input vector for $reduce_and cell $auto$alumacc.cc:64:get_eq$16112: { $auto$alumacc.cc:490:replace_alu$16106 [0] $auto$alumacc.cc:490:replace_alu$16106 [1] $auto$alumacc.cc:490:replace_alu$16106 [2] $auto$alumacc.cc:490:replace_alu$16106 [3] $auto$alumacc.cc:490:replace_alu$16106 [4] $auto$alumacc.cc:490:replace_alu$16106 [5] $auto$alumacc.cc:490:replace_alu$16106 [6] $auto$alumacc.cc:490:replace_alu$16106 [7] $auto$alumacc.cc:490:replace_alu$16106 [8] $auto$alumacc.cc:490:replace_alu$16106 [9] $auto$alumacc.cc:490:replace_alu$16106 [10] $auto$alumacc.cc:490:replace_alu$16106 [11] $auto$alumacc.cc:490:replace_alu$16106 [12] $auto$alumacc.cc:490:replace_alu$16106 [13] $auto$alumacc.cc:490:replace_alu$16106 [14] $auto$alumacc.cc:490:replace_alu$16106 [15] $auto$alumacc.cc:490:replace_alu$16106 [16] $auto$alumacc.cc:490:replace_alu$16106 [17] $auto$alumacc.cc:490:replace_alu$16106 [18] $auto$alumacc.cc:490:replace_alu$16106 [19] $auto$alumacc.cc:490:replace_alu$16106 [20] $auto$alumacc.cc:490:replace_alu$16106 [21] $auto$alumacc.cc:490:replace_alu$16106 [22] $auto$alumacc.cc:490:replace_alu$16106 [23] }
  Optimizing cells in module \top_module.
Performed a total of 21 changes.

2.19.5. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\top_module'.
<suppressed ~3 debug messages>
Removed a total of 1 cells.

2.19.6. Executing OPT_RMDFF pass (remove dff with constant values).
Promoting init spec \common.pb.spi.sync_ss.shiftreg [2] = 1'x to constant driver in module top_module.
Promoting init spec \common.pb.spi.sync_mosi.shiftreg [2] = 1'x to constant driver in module top_module.
Promoting init spec \common.pb.uart.sync_rx.shiftreg [2] = 1'x to constant driver in module top_module.
Promoted 3 init specs to constant drivers.

2.19.7. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \top_module..
Removed 1 unused cells and 18 unused wires.
<suppressed ~2 debug messages>

2.19.8. Executing OPT_EXPR pass (perform const folding).
Optimizing module top_module.

2.19.9. Rerunning OPT passes. (Maybe there is more to do..)

2.19.10. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
Running muxtree optimizer on module \top_module..
  Creating internal representation of mux trees.
  Evaluating internal representation of mux trees.
  Analyzing evaluation results.
Removed 0 multiplexer ports.
<suppressed ~102 debug messages>

2.19.11. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
  Optimizing cells in module \top_module.
Performed a total of 0 changes.

2.19.12. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\top_module'.
Removed a total of 0 cells.

2.19.13. Executing OPT_RMDFF pass (remove dff with constant values).

2.19.14. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \top_module..

2.19.15. Executing OPT_EXPR pass (perform const folding).
Optimizing module top_module.

2.19.16. Finished OPT passes. (There is nothing left to do.)

2.20. Executing FSM pass (extract and optimize FSM).

2.20.1. Executing FSM_DETECT pass (finding FSMs in design).
Not marking top_module.common.pb.spirx_lencalc.state as FSM state register:
    Users of register don't seem to benefit from recoding.
    Register has an initialization value.
Not marking top_module.common.pb.spirx_state as FSM state register:
    Users of register don't seem to benefit from recoding.
    Register has an initialization value.
Not marking top_module.common.pb.spitx_ctrl_reply as FSM state register:
    Users of register don't seem to benefit from recoding.
    Register has an initialization value.

2.20.2. Executing FSM_EXTRACT pass (extracting FSM from design).

2.20.3. Executing FSM_OPT pass (simple optimizations of FSMs).

2.20.4. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \top_module..

2.20.5. Executing FSM_OPT pass (simple optimizations of FSMs).

2.20.6. Executing FSM_RECODE pass (re-assigning FSM state encoding).

2.20.7. Executing FSM_INFO pass (dumping all available information on FSM cells).

2.20.8. Executing FSM_MAP pass (mapping FSMs to basic logic).

2.21. Executing OPT pass (performing simple optimizations).

2.21.1. Executing OPT_EXPR pass (perform const folding).
Optimizing module top_module.

2.21.2. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\top_module'.
Removed a total of 0 cells.

2.21.3. Executing OPT_RMDFF pass (remove dff with constant values).

2.21.4. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \top_module..

2.21.5. Finished fast OPT passes.

2.22. Executing MEMORY pass.

2.22.1. Executing MEMORY_DFF pass (merging $dff cells to $memrd and $memwr).
Checking cell `$techmap\common.pb.rx_buf.$memwr$\mem$block_ram_mod.v:52$7272' in module `\top_module': merged $dff to cell.
Checking cell `$techmap\common.pb.tx_buf.$memwr$\mem$block_ram_mod.v:52$8561' in module `\top_module': merged $dff to cell.
Checking cell `$techmap\common.pb.rx_buf.$memrd$\mem$block_ram_mod.v:55$7015' in module `\top_module': merged data $dff to cell.
Checking cell `$techmap\common.pb.tx_buf.$memrd$\mem$block_ram_mod.v:55$8304' in module `\top_module': merged data $dff to cell.

2.22.2. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \top_module..
Removed 8 unused cells and 10 unused wires.
<suppressed ~9 debug messages>

2.22.3. Executing MEMORY_SHARE pass (consolidating $memrd/$memwr cells).

2.22.4. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \top_module..

2.22.5. Executing MEMORY_COLLECT pass (generating $mem cells).
Collecting $memrd, $memwr and $meminit for memory `\common.pb.rx_buf.mem' in module `\top_module':
  $techmap\common.pb.rx_buf.$meminit$\mem$block_ram_mod.v:46$7016 ($meminit)
  $techmap\common.pb.rx_buf.$meminit$\mem$block_ram_mod.v:46$7017 ($meminit)
  $techmap\common.pb.rx_buf.$meminit$\mem$block_ram_mod.v:46$7018 ($meminit)
  $techmap\common.pb.rx_buf.$meminit$\mem$block_ram_mod.v:46$7019 ($meminit)
  $techmap\common.pb.rx_buf.$meminit$\mem$block_ram_mod.v:46$7020 ($meminit)
  $techmap\common.pb.rx_buf.$meminit$\mem$block_ram_mod.v:46$7021 ($meminit)
  $techmap\common.pb.rx_buf.$meminit$\mem$block_ram_mod.v:46$7022 ($meminit)
  $techmap\common.pb.rx_buf.$meminit$\mem$block_ram_mod.v:46$7023 ($meminit)
  $techmap\common.pb.rx_buf.$meminit$\mem$block_ram_mod.v:46$7024 ($meminit)
  $techmap\common.pb.rx_buf.$meminit$\mem$block_ram_mod.v:46$7025 ($meminit)
  $techmap\common.pb.rx_buf.$meminit$\mem$block_ram_mod.v:46$7026 ($meminit)
  $techmap\common.pb.rx_buf.$meminit$\mem$block_ram_mod.v:46$7027 ($meminit)
  $techmap\common.pb.rx_buf.$meminit$\mem$block_ram_mod.v:46$7028 ($meminit)
  $techmap\common.pb.rx_buf.$meminit$\mem$block_ram_mod.v:46$7029 ($meminit)
  $techmap\common.pb.rx_buf.$meminit$\mem$block_ram_mod.v:46$7030 ($meminit)
  $techmap\common.pb.rx_buf.$meminit$\mem$block_ram_mod.v:46$7031 ($meminit)
  $techmap\common.pb.rx_buf.$meminit$\mem$block_ram_mod.v:46$7032 ($meminit)
  $techmap\common.pb.rx_buf.$meminit$\mem$block_ram_mod.v:46$7033 ($meminit)
  $techmap\common.pb.rx_buf.$meminit$\mem$block_ram_mod.v:46$7034 ($meminit)
  $techmap\common.pb.rx_buf.$meminit$\mem$block_ram_mod.v:46$7035 ($meminit)
  $techmap\common.pb.rx_buf.$meminit$\mem$block_ram_mod.v:46$7036 ($meminit)
  $techmap\common.pb.rx_buf.$meminit$\mem$block_ram_mod.v:46$7037 ($meminit)
  $techmap\common.pb.rx_buf.$meminit$\mem$block_ram_mod.v:46$7038 ($meminit)
  $techmap\common.pb.rx_buf.$meminit$\mem$block_ram_mod.v:46$7039 ($meminit)
  $techmap\common.pb.rx_buf.$meminit$\mem$block_ram_mod.v:46$7040 ($meminit)
  $techmap\common.pb.rx_buf.$meminit$\mem$block_ram_mod.v:46$7041 ($meminit)
  $techmap\common.pb.rx_buf.$meminit$\mem$block_ram_mod.v:46$7042 ($meminit)
  $techmap\common.pb.rx_buf.$meminit$\mem$block_ram_mod.v:46$7043 ($meminit)
  $techmap\common.pb.rx_buf.$meminit$\mem$block_ram_mod.v:46$7044 ($meminit)
  $techmap\common.pb.rx_buf.$meminit$\mem$block_ram_mod.v:46$7045 ($meminit)
  $techmap\common.pb.rx_buf.$meminit$\mem$block_ram_mod.v:46$7046 ($meminit)
  $techmap\common.pb.rx_buf.$meminit$\mem$block_ram_mod.v:46$7047 ($meminit)
  $techmap\common.pb.rx_buf.$meminit$\mem$block_ram_mod.v:46$7048 ($meminit)
  $techmap\common.pb.rx_buf.$meminit$\mem$block_ram_mod.v:46$7049 ($meminit)
  $techmap\common.pb.rx_buf.$meminit$\mem$block_ram_mod.v:46$7050 ($meminit)
  $techmap\common.pb.rx_buf.$meminit$\mem$block_ram_mod.v:46$7051 ($meminit)
  $techmap\common.pb.rx_buf.$meminit$\mem$block_ram_mod.v:46$7052 ($meminit)
  $techmap\common.pb.rx_buf.$meminit$\mem$block_ram_mod.v:46$7053 ($meminit)
  $techmap\common.pb.rx_buf.$meminit$\mem$block_ram_mod.v:46$7054 ($meminit)
  $techmap\common.pb.rx_buf.$meminit$\mem$block_ram_mod.v:46$7055 ($meminit)
  $techmap\common.pb.rx_buf.$meminit$\mem$block_ram_mod.v:46$7056 ($meminit)
  $techmap\common.pb.rx_buf.$meminit$\mem$block_ram_mod.v:46$7057 ($meminit)
  $techmap\common.pb.rx_buf.$meminit$\mem$block_ram_mod.v:46$7058 ($meminit)
  $techmap\common.pb.rx_buf.$meminit$\mem$block_ram_mod.v:46$7059 ($meminit)
  $techmap\common.pb.rx_buf.$meminit$\mem$block_ram_mod.v:46$7060 ($meminit)
  $techmap\common.pb.rx_buf.$meminit$\mem$block_ram_mod.v:46$7061 ($meminit)
  $techmap\common.pb.rx_buf.$meminit$\mem$block_ram_mod.v:46$7062 ($meminit)
  $techmap\common.pb.rx_buf.$meminit$\mem$block_ram_mod.v:46$7063 ($meminit)
  $techmap\common.pb.rx_buf.$meminit$\mem$block_ram_mod.v:46$7064 ($meminit)
  $techmap\common.pb.rx_buf.$meminit$\mem$block_ram_mod.v:46$7065 ($meminit)
  $techmap\common.pb.rx_buf.$meminit$\mem$block_ram_mod.v:46$7066 ($meminit)
  $techmap\common.pb.rx_buf.$meminit$\mem$block_ram_mod.v:46$7067 ($meminit)
  $techmap\common.pb.rx_buf.$meminit$\mem$block_ram_mod.v:46$7068 ($meminit)
  $techmap\common.pb.rx_buf.$meminit$\mem$block_ram_mod.v:46$7069 ($meminit)
  $techmap\common.pb.rx_buf.$meminit$\mem$block_ram_mod.v:46$7070 ($meminit)
  $techmap\common.pb.rx_buf.$meminit$\mem$block_ram_mod.v:46$7071 ($meminit)
  $techmap\common.pb.rx_buf.$meminit$\mem$block_ram_mod.v:46$7072 ($meminit)
  $techmap\common.pb.rx_buf.$meminit$\mem$block_ram_mod.v:46$7073 ($meminit)
  $techmap\common.pb.rx_buf.$meminit$\mem$block_ram_mod.v:46$7074 ($meminit)
  $techmap\common.pb.rx_buf.$meminit$\mem$block_ram_mod.v:46$7075 ($meminit)
  $techmap\common.pb.rx_buf.$meminit$\mem$block_ram_mod.v:46$7076 ($meminit)
  $techmap\common.pb.rx_buf.$meminit$\mem$block_ram_mod.v:46$7077 ($meminit)
  $techmap\common.pb.rx_buf.$meminit$\mem$block_ram_mod.v:46$7078 ($meminit)
  $techmap\common.pb.rx_buf.$meminit$\mem$block_ram_mod.v:46$7079 ($meminit)
  $techmap\common.pb.rx_buf.$meminit$\mem$block_ram_mod.v:46$7080 ($meminit)
  $techmap\common.pb.rx_buf.$meminit$\mem$block_ram_mod.v:46$7081 ($meminit)
  $techmap\common.pb.rx_buf.$meminit$\mem$block_ram_mod.v:46$7082 ($meminit)
  $techmap\common.pb.rx_buf.$meminit$\mem$block_ram_mod.v:46$7083 ($meminit)
  $techmap\common.pb.rx_buf.$meminit$\mem$block_ram_mod.v:46$7084 ($meminit)
  $techmap\common.pb.rx_buf.$meminit$\mem$block_ram_mod.v:46$7085 ($meminit)
  $techmap\common.pb.rx_buf.$meminit$\mem$block_ram_mod.v:46$7086 ($meminit)
  $techmap\common.pb.rx_buf.$meminit$\mem$block_ram_mod.v:46$7087 ($meminit)
  $techmap\common.pb.rx_buf.$meminit$\mem$block_ram_mod.v:46$7088 ($meminit)
  $techmap\common.pb.rx_buf.$meminit$\mem$block_ram_mod.v:46$7089 ($meminit)
  $techmap\common.pb.rx_buf.$meminit$\mem$block_ram_mod.v:46$7090 ($meminit)
  $techmap\common.pb.rx_buf.$meminit$\mem$block_ram_mod.v:46$7091 ($meminit)
  $techmap\common.pb.rx_buf.$meminit$\mem$block_ram_mod.v:46$7092 ($meminit)
  $techmap\common.pb.rx_buf.$meminit$\mem$block_ram_mod.v:46$7093 ($meminit)
  $techmap\common.pb.rx_buf.$meminit$\mem$block_ram_mod.v:46$7094 ($meminit)
  $techmap\common.pb.rx_buf.$meminit$\mem$block_ram_mod.v:46$7095 ($meminit)
  $techmap\common.pb.rx_buf.$meminit$\mem$block_ram_mod.v:46$7096 ($meminit)
  $techmap\common.pb.rx_buf.$meminit$\mem$block_ram_mod.v:46$7097 ($meminit)
  $techmap\common.pb.rx_buf.$meminit$\mem$block_ram_mod.v:46$7098 ($meminit)
  $techmap\common.pb.rx_buf.$meminit$\mem$block_ram_mod.v:46$7099 ($meminit)
  $techmap\common.pb.rx_buf.$meminit$\mem$block_ram_mod.v:46$7100 ($meminit)
  $techmap\common.pb.rx_buf.$meminit$\mem$block_ram_mod.v:46$7101 ($meminit)
  $techmap\common.pb.rx_buf.$meminit$\mem$block_ram_mod.v:46$7102 ($meminit)
  $techmap\common.pb.rx_buf.$meminit$\mem$block_ram_mod.v:46$7103 ($meminit)
  $techmap\common.pb.rx_buf.$meminit$\mem$block_ram_mod.v:46$7104 ($meminit)
  $techmap\common.pb.rx_buf.$meminit$\mem$block_ram_mod.v:46$7105 ($meminit)
  $techmap\common.pb.rx_buf.$meminit$\mem$block_ram_mod.v:46$7106 ($meminit)
  $techmap\common.pb.rx_buf.$meminit$\mem$block_ram_mod.v:46$7107 ($meminit)
  $techmap\common.pb.rx_buf.$meminit$\mem$block_ram_mod.v:46$7108 ($meminit)
  $techmap\common.pb.rx_buf.$meminit$\mem$block_ram_mod.v:46$7109 ($meminit)
  $techmap\common.pb.rx_buf.$meminit$\mem$block_ram_mod.v:46$7110 ($meminit)
  $techmap\common.pb.rx_buf.$meminit$\mem$block_ram_mod.v:46$7111 ($meminit)
  $techmap\common.pb.rx_buf.$meminit$\mem$block_ram_mod.v:46$7112 ($meminit)
  $techmap\common.pb.rx_buf.$meminit$\mem$block_ram_mod.v:46$7113 ($meminit)
  $techmap\common.pb.rx_buf.$meminit$\mem$block_ram_mod.v:46$7114 ($meminit)
  $techmap\common.pb.rx_buf.$meminit$\mem$block_ram_mod.v:46$7115 ($meminit)
  $techmap\common.pb.rx_buf.$meminit$\mem$block_ram_mod.v:46$7116 ($meminit)
  $techmap\common.pb.rx_buf.$meminit$\mem$block_ram_mod.v:46$7117 ($meminit)
  $techmap\common.pb.rx_buf.$meminit$\mem$block_ram_mod.v:46$7118 ($meminit)
  $techmap\common.pb.rx_buf.$meminit$\mem$block_ram_mod.v:46$7119 ($meminit)
  $techmap\common.pb.rx_buf.$meminit$\mem$block_ram_mod.v:46$7120 ($meminit)
  $techmap\common.pb.rx_buf.$meminit$\mem$block_ram_mod.v:46$7121 ($meminit)
  $techmap\common.pb.rx_buf.$meminit$\mem$block_ram_mod.v:46$7122 ($meminit)
  $techmap\common.pb.rx_buf.$meminit$\mem$block_ram_mod.v:46$7123 ($meminit)
  $techmap\common.pb.rx_buf.$meminit$\mem$block_ram_mod.v:46$7124 ($meminit)
  $techmap\common.pb.rx_buf.$meminit$\mem$block_ram_mod.v:46$7125 ($meminit)
  $techmap\common.pb.rx_buf.$meminit$\mem$block_ram_mod.v:46$7126 ($meminit)
  $techmap\common.pb.rx_buf.$meminit$\mem$block_ram_mod.v:46$7127 ($meminit)
  $techmap\common.pb.rx_buf.$meminit$\mem$block_ram_mod.v:46$7128 ($meminit)
  $techmap\common.pb.rx_buf.$meminit$\mem$block_ram_mod.v:46$7129 ($meminit)
  $techmap\common.pb.rx_buf.$meminit$\mem$block_ram_mod.v:46$7130 ($meminit)
  $techmap\common.pb.rx_buf.$meminit$\mem$block_ram_mod.v:46$7131 ($meminit)
  $techmap\common.pb.rx_buf.$meminit$\mem$block_ram_mod.v:46$7132 ($meminit)
  $techmap\common.pb.rx_buf.$meminit$\mem$block_ram_mod.v:46$7133 ($meminit)
  $techmap\common.pb.rx_buf.$meminit$\mem$block_ram_mod.v:46$7134 ($meminit)
  $techmap\common.pb.rx_buf.$meminit$\mem$block_ram_mod.v:46$7135 ($meminit)
  $techmap\common.pb.rx_buf.$meminit$\mem$block_ram_mod.v:46$7136 ($meminit)
  $techmap\common.pb.rx_buf.$meminit$\mem$block_ram_mod.v:46$7137 ($meminit)
  $techmap\common.pb.rx_buf.$meminit$\mem$block_ram_mod.v:46$7138 ($meminit)
  $techmap\common.pb.rx_buf.$meminit$\mem$block_ram_mod.v:46$7139 ($meminit)
  $techmap\common.pb.rx_buf.$meminit$\mem$block_ram_mod.v:46$7140 ($meminit)
  $techmap\common.pb.rx_buf.$meminit$\mem$block_ram_mod.v:46$7141 ($meminit)
  $techmap\common.pb.rx_buf.$meminit$\mem$block_ram_mod.v:46$7142 ($meminit)
  $techmap\common.pb.rx_buf.$meminit$\mem$block_ram_mod.v:46$7143 ($meminit)
  $techmap\common.pb.rx_buf.$meminit$\mem$block_ram_mod.v:46$7144 ($meminit)
  $techmap\common.pb.rx_buf.$meminit$\mem$block_ram_mod.v:46$7145 ($meminit)
  $techmap\common.pb.rx_buf.$meminit$\mem$block_ram_mod.v:46$7146 ($meminit)
  $techmap\common.pb.rx_buf.$meminit$\mem$block_ram_mod.v:46$7147 ($meminit)
  $techmap\common.pb.rx_buf.$meminit$\mem$block_ram_mod.v:46$7148 ($meminit)
  $techmap\common.pb.rx_buf.$meminit$\mem$block_ram_mod.v:46$7149 ($meminit)
  $techmap\common.pb.rx_buf.$meminit$\mem$block_ram_mod.v:46$7150 ($meminit)
  $techmap\common.pb.rx_buf.$meminit$\mem$block_ram_mod.v:46$7151 ($meminit)
  $techmap\common.pb.rx_buf.$meminit$\mem$block_ram_mod.v:46$7152 ($meminit)
  $techmap\common.pb.rx_buf.$meminit$\mem$block_ram_mod.v:46$7153 ($meminit)
  $techmap\common.pb.rx_buf.$meminit$\mem$block_ram_mod.v:46$7154 ($meminit)
  $techmap\common.pb.rx_buf.$meminit$\mem$block_ram_mod.v:46$7155 ($meminit)
  $techmap\common.pb.rx_buf.$meminit$\mem$block_ram_mod.v:46$7156 ($meminit)
  $techmap\common.pb.rx_buf.$meminit$\mem$block_ram_mod.v:46$7157 ($meminit)
  $techmap\common.pb.rx_buf.$meminit$\mem$block_ram_mod.v:46$7158 ($meminit)
  $techmap\common.pb.rx_buf.$meminit$\mem$block_ram_mod.v:46$7159 ($meminit)
  $techmap\common.pb.rx_buf.$meminit$\mem$block_ram_mod.v:46$7160 ($meminit)
  $techmap\common.pb.rx_buf.$meminit$\mem$block_ram_mod.v:46$7161 ($meminit)
  $techmap\common.pb.rx_buf.$meminit$\mem$block_ram_mod.v:46$7162 ($meminit)
  $techmap\common.pb.rx_buf.$meminit$\mem$block_ram_mod.v:46$7163 ($meminit)
  $techmap\common.pb.rx_buf.$meminit$\mem$block_ram_mod.v:46$7164 ($meminit)
  $techmap\common.pb.rx_buf.$meminit$\mem$block_ram_mod.v:46$7165 ($meminit)
  $techmap\common.pb.rx_buf.$meminit$\mem$block_ram_mod.v:46$7166 ($meminit)
  $techmap\common.pb.rx_buf.$meminit$\mem$block_ram_mod.v:46$7167 ($meminit)
  $techmap\common.pb.rx_buf.$meminit$\mem$block_ram_mod.v:46$7168 ($meminit)
  $techmap\common.pb.rx_buf.$meminit$\mem$block_ram_mod.v:46$7169 ($meminit)
  $techmap\common.pb.rx_buf.$meminit$\mem$block_ram_mod.v:46$7170 ($meminit)
  $techmap\common.pb.rx_buf.$meminit$\mem$block_ram_mod.v:46$7171 ($meminit)
  $techmap\common.pb.rx_buf.$meminit$\mem$block_ram_mod.v:46$7172 ($meminit)
  $techmap\common.pb.rx_buf.$meminit$\mem$block_ram_mod.v:46$7173 ($meminit)
  $techmap\common.pb.rx_buf.$meminit$\mem$block_ram_mod.v:46$7174 ($meminit)
  $techmap\common.pb.rx_buf.$meminit$\mem$block_ram_mod.v:46$7175 ($meminit)
  $techmap\common.pb.rx_buf.$meminit$\mem$block_ram_mod.v:46$7176 ($meminit)
  $techmap\common.pb.rx_buf.$meminit$\mem$block_ram_mod.v:46$7177 ($meminit)
  $techmap\common.pb.rx_buf.$meminit$\mem$block_ram_mod.v:46$7178 ($meminit)
  $techmap\common.pb.rx_buf.$meminit$\mem$block_ram_mod.v:46$7179 ($meminit)
  $techmap\common.pb.rx_buf.$meminit$\mem$block_ram_mod.v:46$7180 ($meminit)
  $techmap\common.pb.rx_buf.$meminit$\mem$block_ram_mod.v:46$7181 ($meminit)
  $techmap\common.pb.rx_buf.$meminit$\mem$block_ram_mod.v:46$7182 ($meminit)
  $techmap\common.pb.rx_buf.$meminit$\mem$block_ram_mod.v:46$7183 ($meminit)
  $techmap\common.pb.rx_buf.$meminit$\mem$block_ram_mod.v:46$7184 ($meminit)
  $techmap\common.pb.rx_buf.$meminit$\mem$block_ram_mod.v:46$7185 ($meminit)
  $techmap\common.pb.rx_buf.$meminit$\mem$block_ram_mod.v:46$7186 ($meminit)
  $techmap\common.pb.rx_buf.$meminit$\mem$block_ram_mod.v:46$7187 ($meminit)
  $techmap\common.pb.rx_buf.$meminit$\mem$block_ram_mod.v:46$7188 ($meminit)
  $techmap\common.pb.rx_buf.$meminit$\mem$block_ram_mod.v:46$7189 ($meminit)
  $techmap\common.pb.rx_buf.$meminit$\mem$block_ram_mod.v:46$7190 ($meminit)
  $techmap\common.pb.rx_buf.$meminit$\mem$block_ram_mod.v:46$7191 ($meminit)
  $techmap\common.pb.rx_buf.$meminit$\mem$block_ram_mod.v:46$7192 ($meminit)
  $techmap\common.pb.rx_buf.$meminit$\mem$block_ram_mod.v:46$7193 ($meminit)
  $techmap\common.pb.rx_buf.$meminit$\mem$block_ram_mod.v:46$7194 ($meminit)
  $techmap\common.pb.rx_buf.$meminit$\mem$block_ram_mod.v:46$7195 ($meminit)
  $techmap\common.pb.rx_buf.$meminit$\mem$block_ram_mod.v:46$7196 ($meminit)
  $techmap\common.pb.rx_buf.$meminit$\mem$block_ram_mod.v:46$7197 ($meminit)
  $techmap\common.pb.rx_buf.$meminit$\mem$block_ram_mod.v:46$7198 ($meminit)
  $techmap\common.pb.rx_buf.$meminit$\mem$block_ram_mod.v:46$7199 ($meminit)
  $techmap\common.pb.rx_buf.$meminit$\mem$block_ram_mod.v:46$7200 ($meminit)
  $techmap\common.pb.rx_buf.$meminit$\mem$block_ram_mod.v:46$7201 ($meminit)
  $techmap\common.pb.rx_buf.$meminit$\mem$block_ram_mod.v:46$7202 ($meminit)
  $techmap\common.pb.rx_buf.$meminit$\mem$block_ram_mod.v:46$7203 ($meminit)
  $techmap\common.pb.rx_buf.$meminit$\mem$block_ram_mod.v:46$7204 ($meminit)
  $techmap\common.pb.rx_buf.$meminit$\mem$block_ram_mod.v:46$7205 ($meminit)
  $techmap\common.pb.rx_buf.$meminit$\mem$block_ram_mod.v:46$7206 ($meminit)
  $techmap\common.pb.rx_buf.$meminit$\mem$block_ram_mod.v:46$7207 ($meminit)
  $techmap\common.pb.rx_buf.$meminit$\mem$block_ram_mod.v:46$7208 ($meminit)
  $techmap\common.pb.rx_buf.$meminit$\mem$block_ram_mod.v:46$7209 ($meminit)
  $techmap\common.pb.rx_buf.$meminit$\mem$block_ram_mod.v:46$7210 ($meminit)
  $techmap\common.pb.rx_buf.$meminit$\mem$block_ram_mod.v:46$7211 ($meminit)
  $techmap\common.pb.rx_buf.$meminit$\mem$block_ram_mod.v:46$7212 ($meminit)
  $techmap\common.pb.rx_buf.$meminit$\mem$block_ram_mod.v:46$7213 ($meminit)
  $techmap\common.pb.rx_buf.$meminit$\mem$block_ram_mod.v:46$7214 ($meminit)
  $techmap\common.pb.rx_buf.$meminit$\mem$block_ram_mod.v:46$7215 ($meminit)
  $techmap\common.pb.rx_buf.$meminit$\mem$block_ram_mod.v:46$7216 ($meminit)
  $techmap\common.pb.rx_buf.$meminit$\mem$block_ram_mod.v:46$7217 ($meminit)
  $techmap\common.pb.rx_buf.$meminit$\mem$block_ram_mod.v:46$7218 ($meminit)
  $techmap\common.pb.rx_buf.$meminit$\mem$block_ram_mod.v:46$7219 ($meminit)
  $techmap\common.pb.rx_buf.$meminit$\mem$block_ram_mod.v:46$7220 ($meminit)
  $techmap\common.pb.rx_buf.$meminit$\mem$block_ram_mod.v:46$7221 ($meminit)
  $techmap\common.pb.rx_buf.$meminit$\mem$block_ram_mod.v:46$7222 ($meminit)
  $techmap\common.pb.rx_buf.$meminit$\mem$block_ram_mod.v:46$7223 ($meminit)
  $techmap\common.pb.rx_buf.$meminit$\mem$block_ram_mod.v:46$7224 ($meminit)
  $techmap\common.pb.rx_buf.$meminit$\mem$block_ram_mod.v:46$7225 ($meminit)
  $techmap\common.pb.rx_buf.$meminit$\mem$block_ram_mod.v:46$7226 ($meminit)
  $techmap\common.pb.rx_buf.$meminit$\mem$block_ram_mod.v:46$7227 ($meminit)
  $techmap\common.pb.rx_buf.$meminit$\mem$block_ram_mod.v:46$7228 ($meminit)
  $techmap\common.pb.rx_buf.$meminit$\mem$block_ram_mod.v:46$7229 ($meminit)
  $techmap\common.pb.rx_buf.$meminit$\mem$block_ram_mod.v:46$7230 ($meminit)
  $techmap\common.pb.rx_buf.$meminit$\mem$block_ram_mod.v:46$7231 ($meminit)
  $techmap\common.pb.rx_buf.$meminit$\mem$block_ram_mod.v:46$7232 ($meminit)
  $techmap\common.pb.rx_buf.$meminit$\mem$block_ram_mod.v:46$7233 ($meminit)
  $techmap\common.pb.rx_buf.$meminit$\mem$block_ram_mod.v:46$7234 ($meminit)
  $techmap\common.pb.rx_buf.$meminit$\mem$block_ram_mod.v:46$7235 ($meminit)
  $techmap\common.pb.rx_buf.$meminit$\mem$block_ram_mod.v:46$7236 ($meminit)
  $techmap\common.pb.rx_buf.$meminit$\mem$block_ram_mod.v:46$7237 ($meminit)
  $techmap\common.pb.rx_buf.$meminit$\mem$block_ram_mod.v:46$7238 ($meminit)
  $techmap\common.pb.rx_buf.$meminit$\mem$block_ram_mod.v:46$7239 ($meminit)
  $techmap\common.pb.rx_buf.$meminit$\mem$block_ram_mod.v:46$7240 ($meminit)
  $techmap\common.pb.rx_buf.$meminit$\mem$block_ram_mod.v:46$7241 ($meminit)
  $techmap\common.pb.rx_buf.$meminit$\mem$block_ram_mod.v:46$7242 ($meminit)
  $techmap\common.pb.rx_buf.$meminit$\mem$block_ram_mod.v:46$7243 ($meminit)
  $techmap\common.pb.rx_buf.$meminit$\mem$block_ram_mod.v:46$7244 ($meminit)
  $techmap\common.pb.rx_buf.$meminit$\mem$block_ram_mod.v:46$7245 ($meminit)
  $techmap\common.pb.rx_buf.$meminit$\mem$block_ram_mod.v:46$7246 ($meminit)
  $techmap\common.pb.rx_buf.$meminit$\mem$block_ram_mod.v:46$7247 ($meminit)
  $techmap\common.pb.rx_buf.$meminit$\mem$block_ram_mod.v:46$7248 ($meminit)
  $techmap\common.pb.rx_buf.$meminit$\mem$block_ram_mod.v:46$7249 ($meminit)
  $techmap\common.pb.rx_buf.$meminit$\mem$block_ram_mod.v:46$7250 ($meminit)
  $techmap\common.pb.rx_buf.$meminit$\mem$block_ram_mod.v:46$7251 ($meminit)
  $techmap\common.pb.rx_buf.$meminit$\mem$block_ram_mod.v:46$7252 ($meminit)
  $techmap\common.pb.rx_buf.$meminit$\mem$block_ram_mod.v:46$7253 ($meminit)
  $techmap\common.pb.rx_buf.$meminit$\mem$block_ram_mod.v:46$7254 ($meminit)
  $techmap\common.pb.rx_buf.$meminit$\mem$block_ram_mod.v:46$7255 ($meminit)
  $techmap\common.pb.rx_buf.$meminit$\mem$block_ram_mod.v:46$7256 ($meminit)
  $techmap\common.pb.rx_buf.$meminit$\mem$block_ram_mod.v:46$7257 ($meminit)
  $techmap\common.pb.rx_buf.$meminit$\mem$block_ram_mod.v:46$7258 ($meminit)
  $techmap\common.pb.rx_buf.$meminit$\mem$block_ram_mod.v:46$7259 ($meminit)
  $techmap\common.pb.rx_buf.$meminit$\mem$block_ram_mod.v:46$7260 ($meminit)
  $techmap\common.pb.rx_buf.$meminit$\mem$block_ram_mod.v:46$7261 ($meminit)
  $techmap\common.pb.rx_buf.$meminit$\mem$block_ram_mod.v:46$7262 ($meminit)
  $techmap\common.pb.rx_buf.$meminit$\mem$block_ram_mod.v:46$7263 ($meminit)
  $techmap\common.pb.rx_buf.$meminit$\mem$block_ram_mod.v:46$7264 ($meminit)
  $techmap\common.pb.rx_buf.$meminit$\mem$block_ram_mod.v:46$7265 ($meminit)
  $techmap\common.pb.rx_buf.$meminit$\mem$block_ram_mod.v:46$7266 ($meminit)
  $techmap\common.pb.rx_buf.$meminit$\mem$block_ram_mod.v:46$7267 ($meminit)
  $techmap\common.pb.rx_buf.$meminit$\mem$block_ram_mod.v:46$7268 ($meminit)
  $techmap\common.pb.rx_buf.$meminit$\mem$block_ram_mod.v:46$7269 ($meminit)
  $techmap\common.pb.rx_buf.$meminit$\mem$block_ram_mod.v:46$7270 ($meminit)
  $techmap\common.pb.rx_buf.$meminit$\mem$block_ram_mod.v:46$7271 ($meminit)
  $techmap\common.pb.rx_buf.$memwr$\mem$block_ram_mod.v:52$7272 ($memwr)
  $techmap\common.pb.rx_buf.$memrd$\mem$block_ram_mod.v:55$7015 ($memrd)
Collecting $memrd, $memwr and $meminit for memory `\common.pb.tx_buf.mem' in module `\top_module':
  $techmap\common.pb.tx_buf.$meminit$\mem$block_ram_mod.v:46$8305 ($meminit)
  $techmap\common.pb.tx_buf.$meminit$\mem$block_ram_mod.v:46$8306 ($meminit)
  $techmap\common.pb.tx_buf.$meminit$\mem$block_ram_mod.v:46$8307 ($meminit)
  $techmap\common.pb.tx_buf.$meminit$\mem$block_ram_mod.v:46$8308 ($meminit)
  $techmap\common.pb.tx_buf.$meminit$\mem$block_ram_mod.v:46$8309 ($meminit)
  $techmap\common.pb.tx_buf.$meminit$\mem$block_ram_mod.v:46$8310 ($meminit)
  $techmap\common.pb.tx_buf.$meminit$\mem$block_ram_mod.v:46$8311 ($meminit)
  $techmap\common.pb.tx_buf.$meminit$\mem$block_ram_mod.v:46$8312 ($meminit)
  $techmap\common.pb.tx_buf.$meminit$\mem$block_ram_mod.v:46$8313 ($meminit)
  $techmap\common.pb.tx_buf.$meminit$\mem$block_ram_mod.v:46$8314 ($meminit)
  $techmap\common.pb.tx_buf.$meminit$\mem$block_ram_mod.v:46$8315 ($meminit)
  $techmap\common.pb.tx_buf.$meminit$\mem$block_ram_mod.v:46$8316 ($meminit)
  $techmap\common.pb.tx_buf.$meminit$\mem$block_ram_mod.v:46$8317 ($meminit)
  $techmap\common.pb.tx_buf.$meminit$\mem$block_ram_mod.v:46$8318 ($meminit)
  $techmap\common.pb.tx_buf.$meminit$\mem$block_ram_mod.v:46$8319 ($meminit)
  $techmap\common.pb.tx_buf.$meminit$\mem$block_ram_mod.v:46$8320 ($meminit)
  $techmap\common.pb.tx_buf.$meminit$\mem$block_ram_mod.v:46$8321 ($meminit)
  $techmap\common.pb.tx_buf.$meminit$\mem$block_ram_mod.v:46$8322 ($meminit)
  $techmap\common.pb.tx_buf.$meminit$\mem$block_ram_mod.v:46$8323 ($meminit)
  $techmap\common.pb.tx_buf.$meminit$\mem$block_ram_mod.v:46$8324 ($meminit)
  $techmap\common.pb.tx_buf.$meminit$\mem$block_ram_mod.v:46$8325 ($meminit)
  $techmap\common.pb.tx_buf.$meminit$\mem$block_ram_mod.v:46$8326 ($meminit)
  $techmap\common.pb.tx_buf.$meminit$\mem$block_ram_mod.v:46$8327 ($meminit)
  $techmap\common.pb.tx_buf.$meminit$\mem$block_ram_mod.v:46$8328 ($meminit)
  $techmap\common.pb.tx_buf.$meminit$\mem$block_ram_mod.v:46$8329 ($meminit)
  $techmap\common.pb.tx_buf.$meminit$\mem$block_ram_mod.v:46$8330 ($meminit)
  $techmap\common.pb.tx_buf.$meminit$\mem$block_ram_mod.v:46$8331 ($meminit)
  $techmap\common.pb.tx_buf.$meminit$\mem$block_ram_mod.v:46$8332 ($meminit)
  $techmap\common.pb.tx_buf.$meminit$\mem$block_ram_mod.v:46$8333 ($meminit)
  $techmap\common.pb.tx_buf.$meminit$\mem$block_ram_mod.v:46$8334 ($meminit)
  $techmap\common.pb.tx_buf.$meminit$\mem$block_ram_mod.v:46$8335 ($meminit)
  $techmap\common.pb.tx_buf.$meminit$\mem$block_ram_mod.v:46$8336 ($meminit)
  $techmap\common.pb.tx_buf.$meminit$\mem$block_ram_mod.v:46$8337 ($meminit)
  $techmap\common.pb.tx_buf.$meminit$\mem$block_ram_mod.v:46$8338 ($meminit)
  $techmap\common.pb.tx_buf.$meminit$\mem$block_ram_mod.v:46$8339 ($meminit)
  $techmap\common.pb.tx_buf.$meminit$\mem$block_ram_mod.v:46$8340 ($meminit)
  $techmap\common.pb.tx_buf.$meminit$\mem$block_ram_mod.v:46$8341 ($meminit)
  $techmap\common.pb.tx_buf.$meminit$\mem$block_ram_mod.v:46$8342 ($meminit)
  $techmap\common.pb.tx_buf.$meminit$\mem$block_ram_mod.v:46$8343 ($meminit)
  $techmap\common.pb.tx_buf.$meminit$\mem$block_ram_mod.v:46$8344 ($meminit)
  $techmap\common.pb.tx_buf.$meminit$\mem$block_ram_mod.v:46$8345 ($meminit)
  $techmap\common.pb.tx_buf.$meminit$\mem$block_ram_mod.v:46$8346 ($meminit)
  $techmap\common.pb.tx_buf.$meminit$\mem$block_ram_mod.v:46$8347 ($meminit)
  $techmap\common.pb.tx_buf.$meminit$\mem$block_ram_mod.v:46$8348 ($meminit)
  $techmap\common.pb.tx_buf.$meminit$\mem$block_ram_mod.v:46$8349 ($meminit)
  $techmap\common.pb.tx_buf.$meminit$\mem$block_ram_mod.v:46$8350 ($meminit)
  $techmap\common.pb.tx_buf.$meminit$\mem$block_ram_mod.v:46$8351 ($meminit)
  $techmap\common.pb.tx_buf.$meminit$\mem$block_ram_mod.v:46$8352 ($meminit)
  $techmap\common.pb.tx_buf.$meminit$\mem$block_ram_mod.v:46$8353 ($meminit)
  $techmap\common.pb.tx_buf.$meminit$\mem$block_ram_mod.v:46$8354 ($meminit)
  $techmap\common.pb.tx_buf.$meminit$\mem$block_ram_mod.v:46$8355 ($meminit)
  $techmap\common.pb.tx_buf.$meminit$\mem$block_ram_mod.v:46$8356 ($meminit)
  $techmap\common.pb.tx_buf.$meminit$\mem$block_ram_mod.v:46$8357 ($meminit)
  $techmap\common.pb.tx_buf.$meminit$\mem$block_ram_mod.v:46$8358 ($meminit)
  $techmap\common.pb.tx_buf.$meminit$\mem$block_ram_mod.v:46$8359 ($meminit)
  $techmap\common.pb.tx_buf.$meminit$\mem$block_ram_mod.v:46$8360 ($meminit)
  $techmap\common.pb.tx_buf.$meminit$\mem$block_ram_mod.v:46$8361 ($meminit)
  $techmap\common.pb.tx_buf.$meminit$\mem$block_ram_mod.v:46$8362 ($meminit)
  $techmap\common.pb.tx_buf.$meminit$\mem$block_ram_mod.v:46$8363 ($meminit)
  $techmap\common.pb.tx_buf.$meminit$\mem$block_ram_mod.v:46$8364 ($meminit)
  $techmap\common.pb.tx_buf.$meminit$\mem$block_ram_mod.v:46$8365 ($meminit)
  $techmap\common.pb.tx_buf.$meminit$\mem$block_ram_mod.v:46$8366 ($meminit)
  $techmap\common.pb.tx_buf.$meminit$\mem$block_ram_mod.v:46$8367 ($meminit)
  $techmap\common.pb.tx_buf.$meminit$\mem$block_ram_mod.v:46$8368 ($meminit)
  $techmap\common.pb.tx_buf.$meminit$\mem$block_ram_mod.v:46$8369 ($meminit)
  $techmap\common.pb.tx_buf.$meminit$\mem$block_ram_mod.v:46$8370 ($meminit)
  $techmap\common.pb.tx_buf.$meminit$\mem$block_ram_mod.v:46$8371 ($meminit)
  $techmap\common.pb.tx_buf.$meminit$\mem$block_ram_mod.v:46$8372 ($meminit)
  $techmap\common.pb.tx_buf.$meminit$\mem$block_ram_mod.v:46$8373 ($meminit)
  $techmap\common.pb.tx_buf.$meminit$\mem$block_ram_mod.v:46$8374 ($meminit)
  $techmap\common.pb.tx_buf.$meminit$\mem$block_ram_mod.v:46$8375 ($meminit)
  $techmap\common.pb.tx_buf.$meminit$\mem$block_ram_mod.v:46$8376 ($meminit)
  $techmap\common.pb.tx_buf.$meminit$\mem$block_ram_mod.v:46$8377 ($meminit)
  $techmap\common.pb.tx_buf.$meminit$\mem$block_ram_mod.v:46$8378 ($meminit)
  $techmap\common.pb.tx_buf.$meminit$\mem$block_ram_mod.v:46$8379 ($meminit)
  $techmap\common.pb.tx_buf.$meminit$\mem$block_ram_mod.v:46$8380 ($meminit)
  $techmap\common.pb.tx_buf.$meminit$\mem$block_ram_mod.v:46$8381 ($meminit)
  $techmap\common.pb.tx_buf.$meminit$\mem$block_ram_mod.v:46$8382 ($meminit)
  $techmap\common.pb.tx_buf.$meminit$\mem$block_ram_mod.v:46$8383 ($meminit)
  $techmap\common.pb.tx_buf.$meminit$\mem$block_ram_mod.v:46$8384 ($meminit)
  $techmap\common.pb.tx_buf.$meminit$\mem$block_ram_mod.v:46$8385 ($meminit)
  $techmap\common.pb.tx_buf.$meminit$\mem$block_ram_mod.v:46$8386 ($meminit)
  $techmap\common.pb.tx_buf.$meminit$\mem$block_ram_mod.v:46$8387 ($meminit)
  $techmap\common.pb.tx_buf.$meminit$\mem$block_ram_mod.v:46$8388 ($meminit)
  $techmap\common.pb.tx_buf.$meminit$\mem$block_ram_mod.v:46$8389 ($meminit)
  $techmap\common.pb.tx_buf.$meminit$\mem$block_ram_mod.v:46$8390 ($meminit)
  $techmap\common.pb.tx_buf.$meminit$\mem$block_ram_mod.v:46$8391 ($meminit)
  $techmap\common.pb.tx_buf.$meminit$\mem$block_ram_mod.v:46$8392 ($meminit)
  $techmap\common.pb.tx_buf.$meminit$\mem$block_ram_mod.v:46$8393 ($meminit)
  $techmap\common.pb.tx_buf.$meminit$\mem$block_ram_mod.v:46$8394 ($meminit)
  $techmap\common.pb.tx_buf.$meminit$\mem$block_ram_mod.v:46$8395 ($meminit)
  $techmap\common.pb.tx_buf.$meminit$\mem$block_ram_mod.v:46$8396 ($meminit)
  $techmap\common.pb.tx_buf.$meminit$\mem$block_ram_mod.v:46$8397 ($meminit)
  $techmap\common.pb.tx_buf.$meminit$\mem$block_ram_mod.v:46$8398 ($meminit)
  $techmap\common.pb.tx_buf.$meminit$\mem$block_ram_mod.v:46$8399 ($meminit)
  $techmap\common.pb.tx_buf.$meminit$\mem$block_ram_mod.v:46$8400 ($meminit)
  $techmap\common.pb.tx_buf.$meminit$\mem$block_ram_mod.v:46$8401 ($meminit)
  $techmap\common.pb.tx_buf.$meminit$\mem$block_ram_mod.v:46$8402 ($meminit)
  $techmap\common.pb.tx_buf.$meminit$\mem$block_ram_mod.v:46$8403 ($meminit)
  $techmap\common.pb.tx_buf.$meminit$\mem$block_ram_mod.v:46$8404 ($meminit)
  $techmap\common.pb.tx_buf.$meminit$\mem$block_ram_mod.v:46$8405 ($meminit)
  $techmap\common.pb.tx_buf.$meminit$\mem$block_ram_mod.v:46$8406 ($meminit)
  $techmap\common.pb.tx_buf.$meminit$\mem$block_ram_mod.v:46$8407 ($meminit)
  $techmap\common.pb.tx_buf.$meminit$\mem$block_ram_mod.v:46$8408 ($meminit)
  $techmap\common.pb.tx_buf.$meminit$\mem$block_ram_mod.v:46$8409 ($meminit)
  $techmap\common.pb.tx_buf.$meminit$\mem$block_ram_mod.v:46$8410 ($meminit)
  $techmap\common.pb.tx_buf.$meminit$\mem$block_ram_mod.v:46$8411 ($meminit)
  $techmap\common.pb.tx_buf.$meminit$\mem$block_ram_mod.v:46$8412 ($meminit)
  $techmap\common.pb.tx_buf.$meminit$\mem$block_ram_mod.v:46$8413 ($meminit)
  $techmap\common.pb.tx_buf.$meminit$\mem$block_ram_mod.v:46$8414 ($meminit)
  $techmap\common.pb.tx_buf.$meminit$\mem$block_ram_mod.v:46$8415 ($meminit)
  $techmap\common.pb.tx_buf.$meminit$\mem$block_ram_mod.v:46$8416 ($meminit)
  $techmap\common.pb.tx_buf.$meminit$\mem$block_ram_mod.v:46$8417 ($meminit)
  $techmap\common.pb.tx_buf.$meminit$\mem$block_ram_mod.v:46$8418 ($meminit)
  $techmap\common.pb.tx_buf.$meminit$\mem$block_ram_mod.v:46$8419 ($meminit)
  $techmap\common.pb.tx_buf.$meminit$\mem$block_ram_mod.v:46$8420 ($meminit)
  $techmap\common.pb.tx_buf.$meminit$\mem$block_ram_mod.v:46$8421 ($meminit)
  $techmap\common.pb.tx_buf.$meminit$\mem$block_ram_mod.v:46$8422 ($meminit)
  $techmap\common.pb.tx_buf.$meminit$\mem$block_ram_mod.v:46$8423 ($meminit)
  $techmap\common.pb.tx_buf.$meminit$\mem$block_ram_mod.v:46$8424 ($meminit)
  $techmap\common.pb.tx_buf.$meminit$\mem$block_ram_mod.v:46$8425 ($meminit)
  $techmap\common.pb.tx_buf.$meminit$\mem$block_ram_mod.v:46$8426 ($meminit)
  $techmap\common.pb.tx_buf.$meminit$\mem$block_ram_mod.v:46$8427 ($meminit)
  $techmap\common.pb.tx_buf.$meminit$\mem$block_ram_mod.v:46$8428 ($meminit)
  $techmap\common.pb.tx_buf.$meminit$\mem$block_ram_mod.v:46$8429 ($meminit)
  $techmap\common.pb.tx_buf.$meminit$\mem$block_ram_mod.v:46$8430 ($meminit)
  $techmap\common.pb.tx_buf.$meminit$\mem$block_ram_mod.v:46$8431 ($meminit)
  $techmap\common.pb.tx_buf.$meminit$\mem$block_ram_mod.v:46$8432 ($meminit)
  $techmap\common.pb.tx_buf.$meminit$\mem$block_ram_mod.v:46$8433 ($meminit)
  $techmap\common.pb.tx_buf.$meminit$\mem$block_ram_mod.v:46$8434 ($meminit)
  $techmap\common.pb.tx_buf.$meminit$\mem$block_ram_mod.v:46$8435 ($meminit)
  $techmap\common.pb.tx_buf.$meminit$\mem$block_ram_mod.v:46$8436 ($meminit)
  $techmap\common.pb.tx_buf.$meminit$\mem$block_ram_mod.v:46$8437 ($meminit)
  $techmap\common.pb.tx_buf.$meminit$\mem$block_ram_mod.v:46$8438 ($meminit)
  $techmap\common.pb.tx_buf.$meminit$\mem$block_ram_mod.v:46$8439 ($meminit)
  $techmap\common.pb.tx_buf.$meminit$\mem$block_ram_mod.v:46$8440 ($meminit)
  $techmap\common.pb.tx_buf.$meminit$\mem$block_ram_mod.v:46$8441 ($meminit)
  $techmap\common.pb.tx_buf.$meminit$\mem$block_ram_mod.v:46$8442 ($meminit)
  $techmap\common.pb.tx_buf.$meminit$\mem$block_ram_mod.v:46$8443 ($meminit)
  $techmap\common.pb.tx_buf.$meminit$\mem$block_ram_mod.v:46$8444 ($meminit)
  $techmap\common.pb.tx_buf.$meminit$\mem$block_ram_mod.v:46$8445 ($meminit)
  $techmap\common.pb.tx_buf.$meminit$\mem$block_ram_mod.v:46$8446 ($meminit)
  $techmap\common.pb.tx_buf.$meminit$\mem$block_ram_mod.v:46$8447 ($meminit)
  $techmap\common.pb.tx_buf.$meminit$\mem$block_ram_mod.v:46$8448 ($meminit)
  $techmap\common.pb.tx_buf.$meminit$\mem$block_ram_mod.v:46$8449 ($meminit)
  $techmap\common.pb.tx_buf.$meminit$\mem$block_ram_mod.v:46$8450 ($meminit)
  $techmap\common.pb.tx_buf.$meminit$\mem$block_ram_mod.v:46$8451 ($meminit)
  $techmap\common.pb.tx_buf.$meminit$\mem$block_ram_mod.v:46$8452 ($meminit)
  $techmap\common.pb.tx_buf.$meminit$\mem$block_ram_mod.v:46$8453 ($meminit)
  $techmap\common.pb.tx_buf.$meminit$\mem$block_ram_mod.v:46$8454 ($meminit)
  $techmap\common.pb.tx_buf.$meminit$\mem$block_ram_mod.v:46$8455 ($meminit)
  $techmap\common.pb.tx_buf.$meminit$\mem$block_ram_mod.v:46$8456 ($meminit)
  $techmap\common.pb.tx_buf.$meminit$\mem$block_ram_mod.v:46$8457 ($meminit)
  $techmap\common.pb.tx_buf.$meminit$\mem$block_ram_mod.v:46$8458 ($meminit)
  $techmap\common.pb.tx_buf.$meminit$\mem$block_ram_mod.v:46$8459 ($meminit)
  $techmap\common.pb.tx_buf.$meminit$\mem$block_ram_mod.v:46$8460 ($meminit)
  $techmap\common.pb.tx_buf.$meminit$\mem$block_ram_mod.v:46$8461 ($meminit)
  $techmap\common.pb.tx_buf.$meminit$\mem$block_ram_mod.v:46$8462 ($meminit)
  $techmap\common.pb.tx_buf.$meminit$\mem$block_ram_mod.v:46$8463 ($meminit)
  $techmap\common.pb.tx_buf.$meminit$\mem$block_ram_mod.v:46$8464 ($meminit)
  $techmap\common.pb.tx_buf.$meminit$\mem$block_ram_mod.v:46$8465 ($meminit)
  $techmap\common.pb.tx_buf.$meminit$\mem$block_ram_mod.v:46$8466 ($meminit)
  $techmap\common.pb.tx_buf.$meminit$\mem$block_ram_mod.v:46$8467 ($meminit)
  $techmap\common.pb.tx_buf.$meminit$\mem$block_ram_mod.v:46$8468 ($meminit)
  $techmap\common.pb.tx_buf.$meminit$\mem$block_ram_mod.v:46$8469 ($meminit)
  $techmap\common.pb.tx_buf.$meminit$\mem$block_ram_mod.v:46$8470 ($meminit)
  $techmap\common.pb.tx_buf.$meminit$\mem$block_ram_mod.v:46$8471 ($meminit)
  $techmap\common.pb.tx_buf.$meminit$\mem$block_ram_mod.v:46$8472 ($meminit)
  $techmap\common.pb.tx_buf.$meminit$\mem$block_ram_mod.v:46$8473 ($meminit)
  $techmap\common.pb.tx_buf.$meminit$\mem$block_ram_mod.v:46$8474 ($meminit)
  $techmap\common.pb.tx_buf.$meminit$\mem$block_ram_mod.v:46$8475 ($meminit)
  $techmap\common.pb.tx_buf.$meminit$\mem$block_ram_mod.v:46$8476 ($meminit)
  $techmap\common.pb.tx_buf.$meminit$\mem$block_ram_mod.v:46$8477 ($meminit)
  $techmap\common.pb.tx_buf.$meminit$\mem$block_ram_mod.v:46$8478 ($meminit)
  $techmap\common.pb.tx_buf.$meminit$\mem$block_ram_mod.v:46$8479 ($meminit)
  $techmap\common.pb.tx_buf.$meminit$\mem$block_ram_mod.v:46$8480 ($meminit)
  $techmap\common.pb.tx_buf.$meminit$\mem$block_ram_mod.v:46$8481 ($meminit)
  $techmap\common.pb.tx_buf.$meminit$\mem$block_ram_mod.v:46$8482 ($meminit)
  $techmap\common.pb.tx_buf.$meminit$\mem$block_ram_mod.v:46$8483 ($meminit)
  $techmap\common.pb.tx_buf.$meminit$\mem$block_ram_mod.v:46$8484 ($meminit)
  $techmap\common.pb.tx_buf.$meminit$\mem$block_ram_mod.v:46$8485 ($meminit)
  $techmap\common.pb.tx_buf.$meminit$\mem$block_ram_mod.v:46$8486 ($meminit)
  $techmap\common.pb.tx_buf.$meminit$\mem$block_ram_mod.v:46$8487 ($meminit)
  $techmap\common.pb.tx_buf.$meminit$\mem$block_ram_mod.v:46$8488 ($meminit)
  $techmap\common.pb.tx_buf.$meminit$\mem$block_ram_mod.v:46$8489 ($meminit)
  $techmap\common.pb.tx_buf.$meminit$\mem$block_ram_mod.v:46$8490 ($meminit)
  $techmap\common.pb.tx_buf.$meminit$\mem$block_ram_mod.v:46$8491 ($meminit)
  $techmap\common.pb.tx_buf.$meminit$\mem$block_ram_mod.v:46$8492 ($meminit)
  $techmap\common.pb.tx_buf.$meminit$\mem$block_ram_mod.v:46$8493 ($meminit)
  $techmap\common.pb.tx_buf.$meminit$\mem$block_ram_mod.v:46$8494 ($meminit)
  $techmap\common.pb.tx_buf.$meminit$\mem$block_ram_mod.v:46$8495 ($meminit)
  $techmap\common.pb.tx_buf.$meminit$\mem$block_ram_mod.v:46$8496 ($meminit)
  $techmap\common.pb.tx_buf.$meminit$\mem$block_ram_mod.v:46$8497 ($meminit)
  $techmap\common.pb.tx_buf.$meminit$\mem$block_ram_mod.v:46$8498 ($meminit)
  $techmap\common.pb.tx_buf.$meminit$\mem$block_ram_mod.v:46$8499 ($meminit)
  $techmap\common.pb.tx_buf.$meminit$\mem$block_ram_mod.v:46$8500 ($meminit)
  $techmap\common.pb.tx_buf.$meminit$\mem$block_ram_mod.v:46$8501 ($meminit)
  $techmap\common.pb.tx_buf.$meminit$\mem$block_ram_mod.v:46$8502 ($meminit)
  $techmap\common.pb.tx_buf.$meminit$\mem$block_ram_mod.v:46$8503 ($meminit)
  $techmap\common.pb.tx_buf.$meminit$\mem$block_ram_mod.v:46$8504 ($meminit)
  $techmap\common.pb.tx_buf.$meminit$\mem$block_ram_mod.v:46$8505 ($meminit)
  $techmap\common.pb.tx_buf.$meminit$\mem$block_ram_mod.v:46$8506 ($meminit)
  $techmap\common.pb.tx_buf.$meminit$\mem$block_ram_mod.v:46$8507 ($meminit)
  $techmap\common.pb.tx_buf.$meminit$\mem$block_ram_mod.v:46$8508 ($meminit)
  $techmap\common.pb.tx_buf.$meminit$\mem$block_ram_mod.v:46$8509 ($meminit)
  $techmap\common.pb.tx_buf.$meminit$\mem$block_ram_mod.v:46$8510 ($meminit)
  $techmap\common.pb.tx_buf.$meminit$\mem$block_ram_mod.v:46$8511 ($meminit)
  $techmap\common.pb.tx_buf.$meminit$\mem$block_ram_mod.v:46$8512 ($meminit)
  $techmap\common.pb.tx_buf.$meminit$\mem$block_ram_mod.v:46$8513 ($meminit)
  $techmap\common.pb.tx_buf.$meminit$\mem$block_ram_mod.v:46$8514 ($meminit)
  $techmap\common.pb.tx_buf.$meminit$\mem$block_ram_mod.v:46$8515 ($meminit)
  $techmap\common.pb.tx_buf.$meminit$\mem$block_ram_mod.v:46$8516 ($meminit)
  $techmap\common.pb.tx_buf.$meminit$\mem$block_ram_mod.v:46$8517 ($meminit)
  $techmap\common.pb.tx_buf.$meminit$\mem$block_ram_mod.v:46$8518 ($meminit)
  $techmap\common.pb.tx_buf.$meminit$\mem$block_ram_mod.v:46$8519 ($meminit)
  $techmap\common.pb.tx_buf.$meminit$\mem$block_ram_mod.v:46$8520 ($meminit)
  $techmap\common.pb.tx_buf.$meminit$\mem$block_ram_mod.v:46$8521 ($meminit)
  $techmap\common.pb.tx_buf.$meminit$\mem$block_ram_mod.v:46$8522 ($meminit)
  $techmap\common.pb.tx_buf.$meminit$\mem$block_ram_mod.v:46$8523 ($meminit)
  $techmap\common.pb.tx_buf.$meminit$\mem$block_ram_mod.v:46$8524 ($meminit)
  $techmap\common.pb.tx_buf.$meminit$\mem$block_ram_mod.v:46$8525 ($meminit)
  $techmap\common.pb.tx_buf.$meminit$\mem$block_ram_mod.v:46$8526 ($meminit)
  $techmap\common.pb.tx_buf.$meminit$\mem$block_ram_mod.v:46$8527 ($meminit)
  $techmap\common.pb.tx_buf.$meminit$\mem$block_ram_mod.v:46$8528 ($meminit)
  $techmap\common.pb.tx_buf.$meminit$\mem$block_ram_mod.v:46$8529 ($meminit)
  $techmap\common.pb.tx_buf.$meminit$\mem$block_ram_mod.v:46$8530 ($meminit)
  $techmap\common.pb.tx_buf.$meminit$\mem$block_ram_mod.v:46$8531 ($meminit)
  $techmap\common.pb.tx_buf.$meminit$\mem$block_ram_mod.v:46$8532 ($meminit)
  $techmap\common.pb.tx_buf.$meminit$\mem$block_ram_mod.v:46$8533 ($meminit)
  $techmap\common.pb.tx_buf.$meminit$\mem$block_ram_mod.v:46$8534 ($meminit)
  $techmap\common.pb.tx_buf.$meminit$\mem$block_ram_mod.v:46$8535 ($meminit)
  $techmap\common.pb.tx_buf.$meminit$\mem$block_ram_mod.v:46$8536 ($meminit)
  $techmap\common.pb.tx_buf.$meminit$\mem$block_ram_mod.v:46$8537 ($meminit)
  $techmap\common.pb.tx_buf.$meminit$\mem$block_ram_mod.v:46$8538 ($meminit)
  $techmap\common.pb.tx_buf.$meminit$\mem$block_ram_mod.v:46$8539 ($meminit)
  $techmap\common.pb.tx_buf.$meminit$\mem$block_ram_mod.v:46$8540 ($meminit)
  $techmap\common.pb.tx_buf.$meminit$\mem$block_ram_mod.v:46$8541 ($meminit)
  $techmap\common.pb.tx_buf.$meminit$\mem$block_ram_mod.v:46$8542 ($meminit)
  $techmap\common.pb.tx_buf.$meminit$\mem$block_ram_mod.v:46$8543 ($meminit)
  $techmap\common.pb.tx_buf.$meminit$\mem$block_ram_mod.v:46$8544 ($meminit)
  $techmap\common.pb.tx_buf.$meminit$\mem$block_ram_mod.v:46$8545 ($meminit)
  $techmap\common.pb.tx_buf.$meminit$\mem$block_ram_mod.v:46$8546 ($meminit)
  $techmap\common.pb.tx_buf.$meminit$\mem$block_ram_mod.v:46$8547 ($meminit)
  $techmap\common.pb.tx_buf.$meminit$\mem$block_ram_mod.v:46$8548 ($meminit)
  $techmap\common.pb.tx_buf.$meminit$\mem$block_ram_mod.v:46$8549 ($meminit)
  $techmap\common.pb.tx_buf.$meminit$\mem$block_ram_mod.v:46$8550 ($meminit)
  $techmap\common.pb.tx_buf.$meminit$\mem$block_ram_mod.v:46$8551 ($meminit)
  $techmap\common.pb.tx_buf.$meminit$\mem$block_ram_mod.v:46$8552 ($meminit)
  $techmap\common.pb.tx_buf.$meminit$\mem$block_ram_mod.v:46$8553 ($meminit)
  $techmap\common.pb.tx_buf.$meminit$\mem$block_ram_mod.v:46$8554 ($meminit)
  $techmap\common.pb.tx_buf.$meminit$\mem$block_ram_mod.v:46$8555 ($meminit)
  $techmap\common.pb.tx_buf.$meminit$\mem$block_ram_mod.v:46$8556 ($meminit)
  $techmap\common.pb.tx_buf.$meminit$\mem$block_ram_mod.v:46$8557 ($meminit)
  $techmap\common.pb.tx_buf.$meminit$\mem$block_ram_mod.v:46$8558 ($meminit)
  $techmap\common.pb.tx_buf.$meminit$\mem$block_ram_mod.v:46$8559 ($meminit)
  $techmap\common.pb.tx_buf.$meminit$\mem$block_ram_mod.v:46$8560 ($meminit)
  $techmap\common.pb.tx_buf.$memwr$\mem$block_ram_mod.v:52$8561 ($memwr)
  $techmap\common.pb.tx_buf.$memrd$\mem$block_ram_mod.v:55$8304 ($memrd)

2.23. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \top_module..

2.24. Executing MEMORY_BRAM pass (mapping $mem cells to block memories).
Processing top_module.common.pb.rx_buf.mem:
  Properties: ports=2 bits=2304 rports=1 wports=1 dbits=9 abits=8 words=256
  Checking rule #1 for bram type $__ICE40_RAM4K_M0 (variant 1):
    Bram geometry: abits=8 dbits=16 wports=0 rports=0
    Estimated number of duplicates for more read ports: dups=1
    Metrics for $__ICE40_RAM4K_M0: awaste=0 dwaste=7 bwaste=1792 waste=1792 efficiency=56
    Rule #1 for bram type $__ICE40_RAM4K_M0 (variant 1) accepted.
    Mapping to bram type $__ICE40_RAM4K_M0 (variant 1):
      Write port #0 is in clock domain \common.led_blink.clk.
        Mapped to bram port B1.
      Read port #0 is in clock domain \common.led_blink.clk.
        Mapped to bram port A1.1.
      Updated properties: dups=1 waste=1792 efficiency=56
      Storing for later selection.
  Checking rule #2 for bram type $__ICE40_RAM4K_M123 (variant 1):
    Bram geometry: abits=9 dbits=8 wports=0 rports=0
    Estimated number of duplicates for more read ports: dups=1
    Metrics for $__ICE40_RAM4K_M123: awaste=256 dwaste=7 bwaste=3840 waste=3840 efficiency=28
    Rule #2 for bram type $__ICE40_RAM4K_M123 (variant 1) accepted.
    Mapping to bram type $__ICE40_RAM4K_M123 (variant 1):
      Write port #0 is in clock domain \common.led_blink.clk.
        Mapped to bram port B1.
      Read port #0 is in clock domain \common.led_blink.clk.
        Mapped to bram port A1.1.
      Updated properties: dups=1 waste=3840 efficiency=28
      Storing for later selection.
  Checking rule #2 for bram type $__ICE40_RAM4K_M123 (variant 2):
    Bram geometry: abits=10 dbits=4 wports=0 rports=0
    Estimated number of duplicates for more read ports: dups=1
    Metrics for $__ICE40_RAM4K_M123: awaste=768 dwaste=3 bwaste=3840 waste=3840 efficiency=18
    Rule #2 for bram type $__ICE40_RAM4K_M123 (variant 2) accepted.
    Mapping to bram type $__ICE40_RAM4K_M123 (variant 2):
      Write port #0 is in clock domain \common.led_blink.clk.
        Mapped to bram port B1.
      Read port #0 is in clock domain \common.led_blink.clk.
        Mapped to bram port A1.1.
      Updated properties: dups=1 waste=3840 efficiency=18
      Storing for later selection.
  Checking rule #2 for bram type $__ICE40_RAM4K_M123 (variant 3):
    Bram geometry: abits=11 dbits=2 wports=0 rports=0
    Estimated number of duplicates for more read ports: dups=1
    Metrics for $__ICE40_RAM4K_M123: awaste=1792 dwaste=1 bwaste=3840 waste=3840 efficiency=11
    Rule #2 for bram type $__ICE40_RAM4K_M123 (variant 3) accepted.
    Mapping to bram type $__ICE40_RAM4K_M123 (variant 3):
      Write port #0 is in clock domain \common.led_blink.clk.
        Mapped to bram port B1.
      Read port #0 is in clock domain \common.led_blink.clk.
        Mapped to bram port A1.1.
      Updated properties: dups=1 waste=3840 efficiency=11
      Storing for later selection.
  Selecting best of 4 rules:
    Efficiency for rule 2.3: efficiency=11, cells=5, acells=1
    Efficiency for rule 2.2: efficiency=18, cells=3, acells=1
    Efficiency for rule 2.1: efficiency=28, cells=2, acells=1
    Efficiency for rule 1.1: efficiency=56, cells=1, acells=1
    Selected rule 1.1 with efficiency 56.
    Mapping to bram type $__ICE40_RAM4K_M0 (variant 1):
      Write port #0 is in clock domain \common.led_blink.clk.
        Mapped to bram port B1.
      Read port #0 is in clock domain \common.led_blink.clk.
        Mapped to bram port A1.1.
      Creating $__ICE40_RAM4K_M0 cell at grid position <0 0 0>: common.pb.rx_buf.mem.0.0.0
Processing top_module.common.pb.tx_buf.mem:
  Properties: ports=2 bits=2048 rports=1 wports=1 dbits=8 abits=8 words=256
  Checking rule #1 for bram type $__ICE40_RAM4K_M0 (variant 1):
    Bram geometry: abits=8 dbits=16 wports=0 rports=0
    Estimated number of duplicates for more read ports: dups=1
    Metrics for $__ICE40_RAM4K_M0: awaste=0 dwaste=8 bwaste=2048 waste=2048 efficiency=50
    Rule #1 for bram type $__ICE40_RAM4K_M0 (variant 1) accepted.
    Mapping to bram type $__ICE40_RAM4K_M0 (variant 1):
      Write port #0 is in clock domain \common.led_blink.clk.
        Mapped to bram port B1.
      Read port #0 is in clock domain \common.led_blink.clk.
        Mapped to bram port A1.1.
      Updated properties: dups=1 waste=2048 efficiency=50
      Storing for later selection.
  Checking rule #2 for bram type $__ICE40_RAM4K_M123 (variant 1):
    Bram geometry: abits=9 dbits=8 wports=0 rports=0
    Estimated number of duplicates for more read ports: dups=1
    Metrics for $__ICE40_RAM4K_M123: awaste=256 dwaste=0 bwaste=2048 waste=2048 efficiency=50
    Rule #2 for bram type $__ICE40_RAM4K_M123 (variant 1) accepted.
    Mapping to bram type $__ICE40_RAM4K_M123 (variant 1):
      Write port #0 is in clock domain \common.led_blink.clk.
        Mapped to bram port B1.
      Read port #0 is in clock domain \common.led_blink.clk.
        Mapped to bram port A1.1.
      Updated properties: dups=1 waste=2048 efficiency=50
      Storing for later selection.
  Checking rule #2 for bram type $__ICE40_RAM4K_M123 (variant 2):
    Bram geometry: abits=10 dbits=4 wports=0 rports=0
    Estimated number of duplicates for more read ports: dups=1
    Metrics for $__ICE40_RAM4K_M123: awaste=768 dwaste=0 bwaste=3072 waste=3072 efficiency=25
    Rule #2 for bram type $__ICE40_RAM4K_M123 (variant 2) accepted.
    Mapping to bram type $__ICE40_RAM4K_M123 (variant 2):
      Write port #0 is in clock domain \common.led_blink.clk.
        Mapped to bram port B1.
      Read port #0 is in clock domain \common.led_blink.clk.
        Mapped to bram port A1.1.
      Updated properties: dups=1 waste=3072 efficiency=25
      Storing for later selection.
  Checking rule #2 for bram type $__ICE40_RAM4K_M123 (variant 3):
    Bram geometry: abits=11 dbits=2 wports=0 rports=0
    Estimated number of duplicates for more read ports: dups=1
    Metrics for $__ICE40_RAM4K_M123: awaste=1792 dwaste=0 bwaste=3584 waste=3584 efficiency=12
    Rule #2 for bram type $__ICE40_RAM4K_M123 (variant 3) accepted.
    Mapping to bram type $__ICE40_RAM4K_M123 (variant 3):
      Write port #0 is in clock domain \common.led_blink.clk.
        Mapped to bram port B1.
      Read port #0 is in clock domain \common.led_blink.clk.
        Mapped to bram port A1.1.
      Updated properties: dups=1 waste=3584 efficiency=12
      Storing for later selection.
  Selecting best of 4 rules:
    Efficiency for rule 2.3: efficiency=12, cells=4, acells=1
    Efficiency for rule 2.2: efficiency=25, cells=2, acells=1
    Efficiency for rule 2.1: efficiency=50, cells=1, acells=1
    Efficiency for rule 1.1: efficiency=50, cells=1, acells=1
    Selected rule 2.1 with efficiency 50.
    Mapping to bram type $__ICE40_RAM4K_M123 (variant 1):
      Write port #0 is in clock domain \common.led_blink.clk.
        Mapped to bram port B1.
      Read port #0 is in clock domain \common.led_blink.clk.
        Mapped to bram port A1.1.
      Creating $__ICE40_RAM4K_M123 cell at grid position <0 0 0>: common.pb.tx_buf.mem.0.0.0

2.25. Executing TECHMAP pass (map to technology primitives).

2.25.1. Executing Verilog-2005 frontend: /home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/brams_map.v
Parsing Verilog input from `/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/brams_map.v' to AST representation.
Generating RTLIL representation for module `\$__ICE40_RAM4K'.
Generating RTLIL representation for module `\$__ICE40_RAM4K_M0'.
Generating RTLIL representation for module `\$__ICE40_RAM4K_M123'.
Successfully finished Verilog frontend.

2.25.2. Continuing TECHMAP pass.
Using template $paramod$4384d7ed2119d67aeaadc70206cd4fc43ea863ab\$__ICE40_RAM4K_M123 for cells of type $__ICE40_RAM4K_M123.
Using template $paramod$7075c9758ff91d763506ddcbf8f63b9c2eb3f91d\$__ICE40_RAM4K_M0 for cells of type $__ICE40_RAM4K_M0.
Using template $paramod$07486b11768f43d0fab1caac7a90171723751772\$__ICE40_RAM4K for cells of type $__ICE40_RAM4K.
Using template $paramod$ed2a028a6899fe57df2a2c6ef708e50c8e93f7bf\$__ICE40_RAM4K for cells of type $__ICE40_RAM4K.
No more expansions possible.
<suppressed ~88 debug messages>

2.26. Executing ICE40_BRAMINIT pass.

2.27. Executing OPT pass (performing simple optimizations).

2.27.1. Executing OPT_EXPR pass (perform const folding).
Optimizing module top_module.
<suppressed ~34 debug messages>

2.27.2. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\top_module'.
Removed a total of 0 cells.

2.27.3. Executing OPT_RMDFF pass (remove dff with constant values).

2.27.4. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \top_module..
Removed 0 unused cells and 65 unused wires.
<suppressed ~1 debug messages>

2.27.5. Finished fast OPT passes.

2.28. Executing MEMORY_MAP pass (converting $mem cells to logic and flip-flops).

2.29. Executing OPT pass (performing simple optimizations).

2.29.1. Executing OPT_EXPR pass (perform const folding).
Optimizing module top_module.

2.29.2. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\top_module'.
Removed a total of 0 cells.

2.29.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
Running muxtree optimizer on module \top_module..
  Creating internal representation of mux trees.
  Evaluating internal representation of mux trees.
  Analyzing evaluation results.
Removed 0 multiplexer ports.
<suppressed ~99 debug messages>

2.29.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
  Optimizing cells in module \top_module.
    Consolidated identical input bits for $mux cell $techmap\common.pb.$procmux$14447:
      Old ports: A=3'000, B=3'110, Y=$techmap\common.pb.$procmux$14447_Y
      New ports: A=1'0, B=1'1, Y=$techmap\common.pb.$procmux$14447_Y [1]
      New connections: { $techmap\common.pb.$procmux$14447_Y [2] $techmap\common.pb.$procmux$14447_Y [0] } = { $techmap\common.pb.$procmux$14447_Y [1] 1'0 }
    Consolidated identical input bits for $mux cell $techmap\common.pb.$procmux$14476:
      Old ports: A={ 2'01 \common.pb.spi.rx_data_r [1] }, B=3'000, Y=$techmap\common.pb.$procmux$14476_Y
      New ports: A={ 1'1 \common.pb.spi.rx_data_r [1] }, B=2'00, Y=$techmap\common.pb.$procmux$14476_Y [1:0]
      New connections: $techmap\common.pb.$procmux$14476_Y [2] = 1'0
    Consolidated identical input bits for $mux cell $techmap\common.pb.spirx_lencalc.$procmux$14754:
      Old ports: A={ 7'0000000 $techmap\common.pb.spirx_lencalc.$eq$profibus_phy_mod.v:131$5338_Y }, B=8'00000011, Y=$techmap\common.pb.spirx_lencalc.$procmux$14754_Y
      New ports: A={ 1'0 $techmap\common.pb.spirx_lencalc.$eq$profibus_phy_mod.v:131$5338_Y }, B=2'11, Y=$techmap\common.pb.spirx_lencalc.$procmux$14754_Y [1:0]
      New connections: $techmap\common.pb.spirx_lencalc.$procmux$14754_Y [7:2] = 6'000000
    Consolidated identical input bits for $mux cell $techmap\common.pb.spirx_lencalc.$procmux$14779:
      Old ports: A=2'00, B=2'10, Y=$techmap\common.pb.spirx_lencalc.$procmux$14779_Y
      New ports: A=1'0, B=1'1, Y=$techmap\common.pb.spirx_lencalc.$procmux$14779_Y [1]
      New connections: $techmap\common.pb.spirx_lencalc.$procmux$14779_Y [0] = 1'0
  Optimizing cells in module \top_module.
    Consolidated identical input bits for $mux cell $techmap\common.pb.spirx_lencalc.$procmux$14757:
      Old ports: A=$techmap\common.pb.spirx_lencalc.$procmux$14754_Y, B=8'00001110, Y=$techmap\common.pb.spirx_lencalc.$procmux$14757_Y
      New ports: A={ 1'0 $techmap\common.pb.spirx_lencalc.$procmux$14754_Y [1:0] }, B=3'110, Y=$techmap\common.pb.spirx_lencalc.$procmux$14757_Y [2:0]
      New connections: $techmap\common.pb.spirx_lencalc.$procmux$14757_Y [7:3] = { 4'0000 $techmap\common.pb.spirx_lencalc.$procmux$14757_Y [2] }
  Optimizing cells in module \top_module.
    Consolidated identical input bits for $mux cell $techmap\common.pb.spirx_lencalc.$procmux$14760:
      Old ports: A=$techmap\common.pb.spirx_lencalc.$procmux$14757_Y, B=8'00000000, Y=$techmap\common.pb.spirx_lencalc.$procmux$14760_Y
      New ports: A=$techmap\common.pb.spirx_lencalc.$procmux$14757_Y [2:0], B=3'000, Y=$techmap\common.pb.spirx_lencalc.$procmux$14760_Y [2:0]
      New connections: $techmap\common.pb.spirx_lencalc.$procmux$14760_Y [7:3] = { 4'0000 $techmap\common.pb.spirx_lencalc.$procmux$14760_Y [2] }
  Optimizing cells in module \top_module.
    Consolidated identical input bits for $mux cell $techmap\common.pb.spirx_lencalc.$procmux$14763:
      Old ports: A=$techmap\common.pb.spirx_lencalc.$procmux$14760_Y, B=8'00000110, Y=$techmap\common.pb.spirx_lencalc.$procmux$14763_Y
      New ports: A={ $techmap\common.pb.spirx_lencalc.$procmux$14760_Y [2] $techmap\common.pb.spirx_lencalc.$procmux$14760_Y [2:0] }, B=4'0110, Y=$techmap\common.pb.spirx_lencalc.$procmux$14763_Y [3:0]
      New connections: $techmap\common.pb.spirx_lencalc.$procmux$14763_Y [7:4] = 4'0000
  Optimizing cells in module \top_module.
Performed a total of 7 changes.

2.29.5. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\top_module'.
Removed a total of 0 cells.

2.29.6. Executing OPT_RMDFF pass (remove dff with constant values).

2.29.7. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \top_module..

2.29.8. Executing OPT_EXPR pass (perform const folding).
Optimizing module top_module.

2.29.9. Rerunning OPT passes. (Maybe there is more to do..)

2.29.10. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
Running muxtree optimizer on module \top_module..
  Creating internal representation of mux trees.
  Evaluating internal representation of mux trees.
  Analyzing evaluation results.
Removed 0 multiplexer ports.
<suppressed ~99 debug messages>

2.29.11. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
  Optimizing cells in module \top_module.
Performed a total of 0 changes.

2.29.12. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\top_module'.
Removed a total of 0 cells.

2.29.13. Executing OPT_RMDFF pass (remove dff with constant values).

2.29.14. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \top_module..

2.29.15. Executing OPT_EXPR pass (perform const folding).
Optimizing module top_module.

2.29.16. Finished OPT passes. (There is nothing left to do.)

2.30. Executing TECHMAP pass (map to technology primitives).

2.30.1. Executing Verilog-2005 frontend: /home/mb/fpga-toolchain/yosys/bin/../share/yosys/techmap.v
Parsing Verilog input from `/home/mb/fpga-toolchain/yosys/bin/../share/yosys/techmap.v' to AST representation.
Generating RTLIL representation for module `\_90_simplemap_bool_ops'.
Generating RTLIL representation for module `\_90_simplemap_reduce_ops'.
Generating RTLIL representation for module `\_90_simplemap_logic_ops'.
Generating RTLIL representation for module `\_90_simplemap_compare_ops'.
Generating RTLIL representation for module `\_90_simplemap_various'.
Generating RTLIL representation for module `\_90_simplemap_registers'.
Generating RTLIL representation for module `\_90_shift_ops_shr_shl_sshl_sshr'.
Generating RTLIL representation for module `\_90_shift_shiftx'.
Generating RTLIL representation for module `\_90_fa'.
Generating RTLIL representation for module `\_90_lcu'.
Generating RTLIL representation for module `\_90_alu'.
Generating RTLIL representation for module `\_90_macc'.
Generating RTLIL representation for module `\_90_alumacc'.
Generating RTLIL representation for module `\$__div_mod_u'.
Generating RTLIL representation for module `\$__div_mod'.
Generating RTLIL representation for module `\_90_div'.
Generating RTLIL representation for module `\_90_mod'.
Generating RTLIL representation for module `\_90_pow'.
Generating RTLIL representation for module `\_90_pmux'.
Generating RTLIL representation for module `\_90_lut'.
Successfully finished Verilog frontend.

2.30.2. Executing Verilog-2005 frontend: /home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/arith_map.v
Parsing Verilog input from `/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/arith_map.v' to AST representation.
Generating RTLIL representation for module `\_80_ice40_alu'.
Successfully finished Verilog frontend.

2.30.3. Continuing TECHMAP pass.
Using extmapper simplemap for cells of type $and.
Using extmapper simplemap for cells of type $or.
Using extmapper simplemap for cells of type $tribuf.
Using extmapper simplemap for cells of type $dff.
Using extmapper simplemap for cells of type $mux.
Using template $paramod\_80_ice40_alu\A_SIGNED=0\B_SIGNED=0\A_WIDTH=1\B_WIDTH=24\Y_WIDTH=24 for cells of type $alu.
Using extmapper simplemap for cells of type $logic_not.
Using template $paramod\_80_ice40_alu\A_SIGNED=0\B_SIGNED=0\A_WIDTH=32\B_WIDTH=1\Y_WIDTH=32 for cells of type $alu.
Using extmapper simplemap for cells of type $reduce_and.
Using extmapper simplemap for cells of type $not.
Using extmapper simplemap for cells of type $lut.
Using template $paramod\_80_ice40_alu\A_SIGNED=0\B_SIGNED=0\A_WIDTH=24\B_WIDTH=1\Y_WIDTH=32 for cells of type $alu.
Using template $paramod\_80_ice40_alu\A_SIGNED=0\B_SIGNED=0\A_WIDTH=24\B_WIDTH=32\Y_WIDTH=32 for cells of type $alu.
Using extmapper simplemap for cells of type $reduce_or.
Using extmapper simplemap for cells of type $eq.
Using template $paramod\_90_pmux\WIDTH=8\S_WIDTH=2 for cells of type $pmux.
Using template $paramod\_90_pmux\WIDTH=1\S_WIDTH=2 for cells of type $pmux.
Using template $paramod\_90_pmux\WIDTH=3\S_WIDTH=7 for cells of type $pmux.
Using template $paramod\_90_pmux\WIDTH=8\S_WIDTH=3 for cells of type $pmux.
Using template $paramod\_90_pmux\WIDTH=32\S_WIDTH=3 for cells of type $pmux.
Using template $paramod\_90_pmux\WIDTH=1\S_WIDTH=3 for cells of type $pmux.
Using template $paramod\_90_pmux\WIDTH=18\S_WIDTH=2 for cells of type $pmux.
Using template $paramod\_90_pmux\WIDTH=8\S_WIDTH=6 for cells of type $pmux.
Using template $paramod\_90_pmux\WIDTH=1\S_WIDTH=8 for cells of type $pmux.
Using template $paramod\_90_pmux\WIDTH=1\S_WIDTH=7 for cells of type $pmux.
Using template $paramod\_80_ice40_alu\A_SIGNED=0\B_SIGNED=0\A_WIDTH=2\B_WIDTH=8\Y_WIDTH=8 for cells of type $alu.
Using template $paramod\_80_ice40_alu\A_SIGNED=0\B_SIGNED=0\A_WIDTH=1\B_WIDTH=8\Y_WIDTH=8 for cells of type $alu.
Using template $paramod\_80_ice40_alu\A_SIGNED=0\B_SIGNED=0\A_WIDTH=4\B_WIDTH=8\Y_WIDTH=8 for cells of type $alu.
Using template $paramod\_80_ice40_alu\A_SIGNED=0\B_SIGNED=0\A_WIDTH=1\B_WIDTH=6\Y_WIDTH=6 for cells of type $alu.
Using extmapper simplemap for cells of type $logic_or.
Using extmapper simplemap for cells of type $logic_and.
Using extmapper simplemap for cells of type $xor.
Using extmapper simplemap for cells of type $ne.
Using template $paramod\_80_ice40_alu\A_SIGNED=0\B_SIGNED=0\A_WIDTH=8\B_WIDTH=8\Y_WIDTH=8 for cells of type $alu.
Using template $paramod\_80_ice40_alu\A_SIGNED=0\B_SIGNED=0\A_WIDTH=24\B_WIDTH=24\Y_WIDTH=24 for cells of type $alu.
Using template $paramod\_90_pmux\WIDTH=2\S_WIDTH=3 for cells of type $pmux.
Using template $paramod\_80_ice40_alu\A_SIGNED=0\B_SIGNED=0\A_WIDTH=1\B_WIDTH=4\Y_WIDTH=4 for cells of type $alu.
Using template $paramod\_80_ice40_alu\A_SIGNED=0\B_SIGNED=0\A_WIDTH=3\B_WIDTH=8\Y_WIDTH=8 for cells of type $alu.
Using template $paramod\_80_ice40_alu\A_SIGNED=0\B_SIGNED=0\A_WIDTH=4\B_WIDTH=6\Y_WIDTH=6 for cells of type $alu.
Using template $paramod\_80_ice40_alu\A_SIGNED=0\B_SIGNED=0\A_WIDTH=4\B_WIDTH=2\Y_WIDTH=32 for cells of type $alu.
Using template $paramod$constmap:4b5649afbfb8c4c87464bb2a8089455e481b1596$paramod$c93dff91361b8229cab066c0b64da176df19eeef\_90_shift_shiftx for cells of type $shiftx.
Using template $paramod\_80_ice40_alu\A_SIGNED=0\B_SIGNED=0\A_WIDTH=3\B_WIDTH=24\Y_WIDTH=24 for cells of type $alu.
Using template $paramod\_80_ice40_alu\A_SIGNED=0\B_SIGNED=0\A_WIDTH=23\B_WIDTH=1\Y_WIDTH=32 for cells of type $alu.
Using extmapper simplemap for cells of type $pos.
No more expansions possible.
<suppressed ~2237 debug messages>

2.31. Executing ICE40_OPT pass (performing simple optimizations).

2.31.1. Running ICE40 specific optimizations.

2.31.2. Executing OPT_EXPR pass (perform const folding).
Optimizing module top_module.
<suppressed ~2509 debug messages>

2.31.3. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\top_module'.
<suppressed ~1722 debug messages>
Removed a total of 574 cells.

2.31.4. Executing OPT_RMDFF pass (remove dff with constant values).

2.31.5. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \top_module..
Removed 679 unused cells and 1478 unused wires.
<suppressed ~680 debug messages>

2.31.6. Rerunning OPT passes. (Removed registers in this run.)

2.31.7. Running ICE40 specific optimizations.
Optimized away SB_CARRY cell top_module.$auto$alumacc.cc:474:replace_alu$16007.slice[0].carry: CO=$auto$alumacc.cc:474:replace_alu$16007.BB [0]
Optimized away SB_CARRY cell top_module.$auto$alumacc.cc:474:replace_alu$16016.slice[0].carry: CO=\common.pb.spirx_lencalc_byte [0]
Optimized away SB_CARRY cell top_module.$auto$alumacc.cc:474:replace_alu$16025.slice[0].carry: CO=$auto$alumacc.cc:474:replace_alu$16025.BB [0]
Optimized away SB_CARRY cell top_module.$auto$alumacc.cc:474:replace_alu$16034.slice[0].carry: CO=$auto$alumacc.cc:474:replace_alu$16034.BB [0]
Optimized away SB_CARRY cell top_module.$auto$alumacc.cc:474:replace_alu$16047.slice[0].carry: CO=\common.pb.timer_idle [0]
Optimized away SB_CARRY cell top_module.$auto$alumacc.cc:474:replace_alu$16052.slice[0].carry: CO=1'1
Optimized away SB_CARRY cell top_module.$auto$alumacc.cc:474:replace_alu$16065.slice[0].carry: CO=1'1
Optimized away SB_CARRY cell top_module.$auto$alumacc.cc:474:replace_alu$16074.slice[0].carry: CO=$auto$alumacc.cc:474:replace_alu$16052.BB [0]
Optimized away SB_CARRY cell top_module.$auto$alumacc.cc:474:replace_alu$16083.slice[0].carry: CO=1'1
Optimized away SB_CARRY cell top_module.$auto$alumacc.cc:474:replace_alu$16118.slice[0].carry: CO=\common.led_blink.led_on_count [0]
Optimized away SB_CARRY cell top_module.$auto$alumacc.cc:474:replace_alu$16121.slice[0].carry: CO=\common.led_blink.led_off_count [0]
Optimized away SB_CARRY cell top_module.$auto$alumacc.cc:474:replace_alu$16124.slice[0].carry: CO=\common.pb.timer_idle [0]
Optimized away SB_CARRY cell top_module.$auto$alumacc.cc:474:replace_alu$16127.slice[0].carry: CO=\common.pb.tx_buf_wr_addr [0]
Optimized away SB_CARRY cell top_module.$auto$alumacc.cc:474:replace_alu$16130.slice[0].carry: CO=\common.pb.rx_buf_wr_addr [0]
Optimized away SB_CARRY cell top_module.$auto$alumacc.cc:474:replace_alu$16133.slice[0].carry: CO=\common.pb.tx_buf_rd_addr [0]
Optimized away SB_CARRY cell top_module.$auto$alumacc.cc:474:replace_alu$16136.slice[0].carry: CO=\common.pb.spirx_bytecount [0]
Optimized away SB_CARRY cell top_module.$auto$alumacc.cc:474:replace_alu$16139.slice[0].carry: CO=1'0
Optimized away SB_CARRY cell top_module.$auto$alumacc.cc:474:replace_alu$16142.slice[0].carry: CO=\common.pb.spitx_bytecount [0]
Optimized away SB_CARRY cell top_module.$auto$alumacc.cc:474:replace_alu$16145.slice[0].carry: CO=\common.pb.rx_buf_rd_addr [0]
Optimized away SB_CARRY cell top_module.$auto$alumacc.cc:474:replace_alu$16148.slice[0].carry: CO=\common.pb.spitx_len [0]
Optimized away SB_CARRY cell top_module.$auto$alumacc.cc:474:replace_alu$16151.slice[0].carry: CO=\common.pb.spi.bit_count [0]
Optimized away SB_CARRY cell top_module.$auto$alumacc.cc:474:replace_alu$16154.slice[0].carry: CO=1'0
Optimized away SB_CARRY cell top_module.$auto$alumacc.cc:474:replace_alu$16157.slice[0].carry: CO=\common.pb.uart.rx_mod.sym_count [0]
Optimized away SB_CARRY cell top_module.$auto$alumacc.cc:474:replace_alu$16160.slice[0].carry: CO=1'1
Optimized away SB_CARRY cell top_module.$auto$alumacc.cc:474:replace_alu$16160.slice[10].carry: CO=$auto$alumacc.cc:474:replace_alu$16160.C [10]
Optimized away SB_CARRY cell top_module.$auto$alumacc.cc:474:replace_alu$16160.slice[11].carry: CO=$auto$alumacc.cc:474:replace_alu$16160.C [11]
Optimized away SB_CARRY cell top_module.$auto$alumacc.cc:474:replace_alu$16160.slice[12].carry: CO=$auto$alumacc.cc:474:replace_alu$16160.C [12]
Optimized away SB_CARRY cell top_module.$auto$alumacc.cc:474:replace_alu$16160.slice[13].carry: CO=$auto$alumacc.cc:474:replace_alu$16160.C [13]
Optimized away SB_CARRY cell top_module.$auto$alumacc.cc:474:replace_alu$16160.slice[14].carry: CO=$auto$alumacc.cc:474:replace_alu$16160.C [14]
Optimized away SB_CARRY cell top_module.$auto$alumacc.cc:474:replace_alu$16160.slice[15].carry: CO=$auto$alumacc.cc:474:replace_alu$16160.C [15]
Optimized away SB_CARRY cell top_module.$auto$alumacc.cc:474:replace_alu$16160.slice[16].carry: CO=$auto$alumacc.cc:474:replace_alu$16160.C [16]
Optimized away SB_CARRY cell top_module.$auto$alumacc.cc:474:replace_alu$16160.slice[17].carry: CO=$auto$alumacc.cc:474:replace_alu$16160.C [17]
Optimized away SB_CARRY cell top_module.$auto$alumacc.cc:474:replace_alu$16160.slice[18].carry: CO=$auto$alumacc.cc:474:replace_alu$16160.C [18]
Optimized away SB_CARRY cell top_module.$auto$alumacc.cc:474:replace_alu$16160.slice[19].carry: CO=$auto$alumacc.cc:474:replace_alu$16160.C [19]
Optimized away SB_CARRY cell top_module.$auto$alumacc.cc:474:replace_alu$16160.slice[20].carry: CO=$auto$alumacc.cc:474:replace_alu$16160.C [20]
Optimized away SB_CARRY cell top_module.$auto$alumacc.cc:474:replace_alu$16160.slice[21].carry: CO=$auto$alumacc.cc:474:replace_alu$16160.C [21]
Optimized away SB_CARRY cell top_module.$auto$alumacc.cc:474:replace_alu$16160.slice[22].carry: CO=$auto$alumacc.cc:474:replace_alu$16160.C [22]
Optimized away SB_CARRY cell top_module.$auto$alumacc.cc:474:replace_alu$16160.slice[23].carry: CO=$auto$alumacc.cc:474:replace_alu$16160.C [23]
Optimized away SB_CARRY cell top_module.$auto$alumacc.cc:474:replace_alu$16160.slice[24].carry: CO=$auto$alumacc.cc:474:replace_alu$16160.C [24]
Optimized away SB_CARRY cell top_module.$auto$alumacc.cc:474:replace_alu$16160.slice[25].carry: CO=$auto$alumacc.cc:474:replace_alu$16160.C [25]
Optimized away SB_CARRY cell top_module.$auto$alumacc.cc:474:replace_alu$16160.slice[26].carry: CO=$auto$alumacc.cc:474:replace_alu$16160.C [26]
Optimized away SB_CARRY cell top_module.$auto$alumacc.cc:474:replace_alu$16160.slice[27].carry: CO=$auto$alumacc.cc:474:replace_alu$16160.C [27]
Optimized away SB_CARRY cell top_module.$auto$alumacc.cc:474:replace_alu$16160.slice[28].carry: CO=$auto$alumacc.cc:474:replace_alu$16160.C [28]
Optimized away SB_CARRY cell top_module.$auto$alumacc.cc:474:replace_alu$16160.slice[29].carry: CO=$auto$alumacc.cc:474:replace_alu$16160.C [29]
Optimized away SB_CARRY cell top_module.$auto$alumacc.cc:474:replace_alu$16160.slice[30].carry: CO=$auto$alumacc.cc:474:replace_alu$16160.C [30]
Optimized away SB_CARRY cell top_module.$auto$alumacc.cc:474:replace_alu$16160.slice[4].carry: CO=$auto$alumacc.cc:474:replace_alu$16160.C [4]
Optimized away SB_CARRY cell top_module.$auto$alumacc.cc:474:replace_alu$16160.slice[5].carry: CO=$auto$alumacc.cc:474:replace_alu$16160.C [5]
Optimized away SB_CARRY cell top_module.$auto$alumacc.cc:474:replace_alu$16160.slice[6].carry: CO=$auto$alumacc.cc:474:replace_alu$16160.C [6]
Optimized away SB_CARRY cell top_module.$auto$alumacc.cc:474:replace_alu$16160.slice[7].carry: CO=$auto$alumacc.cc:474:replace_alu$16160.C [7]
Optimized away SB_CARRY cell top_module.$auto$alumacc.cc:474:replace_alu$16160.slice[8].carry: CO=$auto$alumacc.cc:474:replace_alu$16160.C [8]
Optimized away SB_CARRY cell top_module.$auto$alumacc.cc:474:replace_alu$16160.slice[9].carry: CO=$auto$alumacc.cc:474:replace_alu$16160.C [9]
Optimized away SB_CARRY cell top_module.$auto$alumacc.cc:474:replace_alu$16163.slice[0].carry: CO=\common.pb.uart.rx_mod.symclk.count [0]
Optimized away SB_CARRY cell top_module.$auto$alumacc.cc:474:replace_alu$16166.slice[0].carry: CO=\common.pb.uart.tx_mod.symclk.clks_per_sym_limited [1]
Optimized away SB_CARRY cell top_module.$auto$alumacc.cc:474:replace_alu$16166.slice[23].carry: CO=$auto$alumacc.cc:474:replace_alu$16166.C [23]
Optimized away SB_CARRY cell top_module.$auto$alumacc.cc:474:replace_alu$16166.slice[24].carry: CO=$auto$alumacc.cc:474:replace_alu$16166.C [24]
Optimized away SB_CARRY cell top_module.$auto$alumacc.cc:474:replace_alu$16166.slice[25].carry: CO=$auto$alumacc.cc:474:replace_alu$16166.C [25]
Optimized away SB_CARRY cell top_module.$auto$alumacc.cc:474:replace_alu$16166.slice[26].carry: CO=$auto$alumacc.cc:474:replace_alu$16166.C [26]
Optimized away SB_CARRY cell top_module.$auto$alumacc.cc:474:replace_alu$16166.slice[27].carry: CO=$auto$alumacc.cc:474:replace_alu$16166.C [27]
Optimized away SB_CARRY cell top_module.$auto$alumacc.cc:474:replace_alu$16166.slice[28].carry: CO=$auto$alumacc.cc:474:replace_alu$16166.C [28]
Optimized away SB_CARRY cell top_module.$auto$alumacc.cc:474:replace_alu$16166.slice[29].carry: CO=$auto$alumacc.cc:474:replace_alu$16166.C [29]
Optimized away SB_CARRY cell top_module.$auto$alumacc.cc:474:replace_alu$16166.slice[30].carry: CO=$auto$alumacc.cc:474:replace_alu$16166.C [30]
Optimized away SB_CARRY cell top_module.$auto$alumacc.cc:474:replace_alu$16169.slice[0].carry: CO=\common.pb.uart.rx_mod.symclk.clks_per_sym_limited
Optimized away SB_CARRY cell top_module.$auto$alumacc.cc:474:replace_alu$16169.slice[24].carry: CO=$auto$alumacc.cc:474:replace_alu$16169.C [24]
Optimized away SB_CARRY cell top_module.$auto$alumacc.cc:474:replace_alu$16169.slice[25].carry: CO=$auto$alumacc.cc:474:replace_alu$16169.C [25]
Optimized away SB_CARRY cell top_module.$auto$alumacc.cc:474:replace_alu$16169.slice[26].carry: CO=$auto$alumacc.cc:474:replace_alu$16169.C [26]
Optimized away SB_CARRY cell top_module.$auto$alumacc.cc:474:replace_alu$16169.slice[27].carry: CO=$auto$alumacc.cc:474:replace_alu$16169.C [27]
Optimized away SB_CARRY cell top_module.$auto$alumacc.cc:474:replace_alu$16169.slice[28].carry: CO=$auto$alumacc.cc:474:replace_alu$16169.C [28]
Optimized away SB_CARRY cell top_module.$auto$alumacc.cc:474:replace_alu$16169.slice[29].carry: CO=$auto$alumacc.cc:474:replace_alu$16169.C [29]
Optimized away SB_CARRY cell top_module.$auto$alumacc.cc:474:replace_alu$16169.slice[30].carry: CO=$auto$alumacc.cc:474:replace_alu$16169.C [30]
Optimized away SB_CARRY cell top_module.$auto$alumacc.cc:474:replace_alu$16172.slice[0].carry: CO=\common.pb.uart.tx_mod.sym_count [0]
Optimized away SB_CARRY cell top_module.$auto$alumacc.cc:474:replace_alu$16175.slice[0].carry: CO=1'1
Optimized away SB_CARRY cell top_module.$auto$alumacc.cc:474:replace_alu$16178.slice[0].carry: CO=\common.pb.uart.tx_mod.symclk.count [0]
Mapping SB_LUT4 cell top_module.$auto$alumacc.cc:474:replace_alu$16118.slice[1].adder back to logic.
Mapping SB_LUT4 cell top_module.$auto$alumacc.cc:474:replace_alu$16121.slice[1].adder back to logic.
Mapping SB_LUT4 cell top_module.$auto$alumacc.cc:474:replace_alu$16124.slice[1].adder back to logic.
Mapping SB_LUT4 cell top_module.$auto$alumacc.cc:474:replace_alu$16127.slice[1].adder back to logic.
Mapping SB_LUT4 cell top_module.$auto$alumacc.cc:474:replace_alu$16130.slice[1].adder back to logic.
Mapping SB_LUT4 cell top_module.$auto$alumacc.cc:474:replace_alu$16133.slice[1].adder back to logic.
Mapping SB_LUT4 cell top_module.$auto$alumacc.cc:474:replace_alu$16136.slice[1].adder back to logic.
Mapping SB_LUT4 cell top_module.$auto$alumacc.cc:474:replace_alu$16139.slice[1].adder back to logic.
Mapping SB_LUT4 cell top_module.$auto$alumacc.cc:474:replace_alu$16142.slice[1].adder back to logic.
Mapping SB_LUT4 cell top_module.$auto$alumacc.cc:474:replace_alu$16145.slice[1].adder back to logic.
Mapping SB_LUT4 cell top_module.$auto$alumacc.cc:474:replace_alu$16148.slice[1].adder back to logic.
Mapping SB_LUT4 cell top_module.$auto$alumacc.cc:474:replace_alu$16151.slice[1].adder back to logic.
Mapping SB_LUT4 cell top_module.$auto$alumacc.cc:474:replace_alu$16154.slice[1].adder back to logic.
Mapping SB_LUT4 cell top_module.$auto$alumacc.cc:474:replace_alu$16157.slice[1].adder back to logic.
Mapping SB_LUT4 cell top_module.$auto$alumacc.cc:474:replace_alu$16160.slice[10].adder back to logic.
Mapping SB_LUT4 cell top_module.$auto$alumacc.cc:474:replace_alu$16160.slice[11].adder back to logic.
Mapping SB_LUT4 cell top_module.$auto$alumacc.cc:474:replace_alu$16160.slice[12].adder back to logic.
Mapping SB_LUT4 cell top_module.$auto$alumacc.cc:474:replace_alu$16160.slice[13].adder back to logic.
Mapping SB_LUT4 cell top_module.$auto$alumacc.cc:474:replace_alu$16160.slice[14].adder back to logic.
Mapping SB_LUT4 cell top_module.$auto$alumacc.cc:474:replace_alu$16160.slice[15].adder back to logic.
Mapping SB_LUT4 cell top_module.$auto$alumacc.cc:474:replace_alu$16160.slice[16].adder back to logic.
Mapping SB_LUT4 cell top_module.$auto$alumacc.cc:474:replace_alu$16160.slice[17].adder back to logic.
Mapping SB_LUT4 cell top_module.$auto$alumacc.cc:474:replace_alu$16160.slice[18].adder back to logic.
Mapping SB_LUT4 cell top_module.$auto$alumacc.cc:474:replace_alu$16160.slice[19].adder back to logic.
Mapping SB_LUT4 cell top_module.$auto$alumacc.cc:474:replace_alu$16160.slice[1].adder back to logic.
Mapping SB_LUT4 cell top_module.$auto$alumacc.cc:474:replace_alu$16160.slice[20].adder back to logic.
Mapping SB_LUT4 cell top_module.$auto$alumacc.cc:474:replace_alu$16160.slice[21].adder back to logic.
Mapping SB_LUT4 cell top_module.$auto$alumacc.cc:474:replace_alu$16160.slice[22].adder back to logic.
Mapping SB_LUT4 cell top_module.$auto$alumacc.cc:474:replace_alu$16160.slice[23].adder back to logic.
Mapping SB_LUT4 cell top_module.$auto$alumacc.cc:474:replace_alu$16160.slice[24].adder back to logic.
Mapping SB_LUT4 cell top_module.$auto$alumacc.cc:474:replace_alu$16160.slice[25].adder back to logic.
Mapping SB_LUT4 cell top_module.$auto$alumacc.cc:474:replace_alu$16160.slice[26].adder back to logic.
Mapping SB_LUT4 cell top_module.$auto$alumacc.cc:474:replace_alu$16160.slice[27].adder back to logic.
Mapping SB_LUT4 cell top_module.$auto$alumacc.cc:474:replace_alu$16160.slice[28].adder back to logic.
Mapping SB_LUT4 cell top_module.$auto$alumacc.cc:474:replace_alu$16160.slice[29].adder back to logic.
Mapping SB_LUT4 cell top_module.$auto$alumacc.cc:474:replace_alu$16160.slice[30].adder back to logic.
Mapping SB_LUT4 cell top_module.$auto$alumacc.cc:474:replace_alu$16160.slice[31].adder back to logic.
Mapping SB_LUT4 cell top_module.$auto$alumacc.cc:474:replace_alu$16160.slice[5].adder back to logic.
Mapping SB_LUT4 cell top_module.$auto$alumacc.cc:474:replace_alu$16160.slice[6].adder back to logic.
Mapping SB_LUT4 cell top_module.$auto$alumacc.cc:474:replace_alu$16160.slice[7].adder back to logic.
Mapping SB_LUT4 cell top_module.$auto$alumacc.cc:474:replace_alu$16160.slice[8].adder back to logic.
Mapping SB_LUT4 cell top_module.$auto$alumacc.cc:474:replace_alu$16160.slice[9].adder back to logic.
Mapping SB_LUT4 cell top_module.$auto$alumacc.cc:474:replace_alu$16163.slice[1].adder back to logic.
Mapping SB_LUT4 cell top_module.$auto$alumacc.cc:474:replace_alu$16166.slice[1].adder back to logic.
Mapping SB_LUT4 cell top_module.$auto$alumacc.cc:474:replace_alu$16166.slice[24].adder back to logic.
Mapping SB_LUT4 cell top_module.$auto$alumacc.cc:474:replace_alu$16166.slice[25].adder back to logic.
Mapping SB_LUT4 cell top_module.$auto$alumacc.cc:474:replace_alu$16166.slice[26].adder back to logic.
Mapping SB_LUT4 cell top_module.$auto$alumacc.cc:474:replace_alu$16166.slice[27].adder back to logic.
Mapping SB_LUT4 cell top_module.$auto$alumacc.cc:474:replace_alu$16166.slice[28].adder back to logic.
Mapping SB_LUT4 cell top_module.$auto$alumacc.cc:474:replace_alu$16166.slice[29].adder back to logic.
Mapping SB_LUT4 cell top_module.$auto$alumacc.cc:474:replace_alu$16166.slice[30].adder back to logic.
Mapping SB_LUT4 cell top_module.$auto$alumacc.cc:474:replace_alu$16166.slice[31].adder back to logic.
Mapping SB_LUT4 cell top_module.$auto$alumacc.cc:474:replace_alu$16169.slice[1].adder back to logic.
Mapping SB_LUT4 cell top_module.$auto$alumacc.cc:474:replace_alu$16169.slice[25].adder back to logic.
Mapping SB_LUT4 cell top_module.$auto$alumacc.cc:474:replace_alu$16169.slice[26].adder back to logic.
Mapping SB_LUT4 cell top_module.$auto$alumacc.cc:474:replace_alu$16169.slice[27].adder back to logic.
Mapping SB_LUT4 cell top_module.$auto$alumacc.cc:474:replace_alu$16169.slice[28].adder back to logic.
Mapping SB_LUT4 cell top_module.$auto$alumacc.cc:474:replace_alu$16169.slice[29].adder back to logic.
Mapping SB_LUT4 cell top_module.$auto$alumacc.cc:474:replace_alu$16169.slice[30].adder back to logic.
Mapping SB_LUT4 cell top_module.$auto$alumacc.cc:474:replace_alu$16169.slice[31].adder back to logic.
Mapping SB_LUT4 cell top_module.$auto$alumacc.cc:474:replace_alu$16172.slice[1].adder back to logic.
Mapping SB_LUT4 cell top_module.$auto$alumacc.cc:474:replace_alu$16175.slice[1].adder back to logic.
Mapping SB_LUT4 cell top_module.$auto$alumacc.cc:474:replace_alu$16178.slice[1].adder back to logic.

2.31.8. Executing OPT_EXPR pass (perform const folding).
Optimizing module top_module.
<suppressed ~880 debug messages>

2.31.9. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\top_module'.
<suppressed ~222 debug messages>
Removed a total of 74 cells.

2.31.10. Executing OPT_RMDFF pass (remove dff with constant values).

2.31.11. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \top_module..
Removed 2 unused cells and 224 unused wires.
<suppressed ~3 debug messages>

2.31.12. Rerunning OPT passes. (Removed registers in this run.)

2.31.13. Running ICE40 specific optimizations.
Optimized away SB_CARRY cell top_module.$auto$alumacc.cc:474:replace_alu$16052.slice[1].carry: CO=$auto$alumacc.cc:474:replace_alu$16052.BB [1]
Optimized away SB_CARRY cell top_module.$auto$alumacc.cc:474:replace_alu$16065.slice[1].carry: CO=1'1
Optimized away SB_CARRY cell top_module.$auto$alumacc.cc:474:replace_alu$16083.slice[1].carry: CO=1'1
Optimized away SB_CARRY cell top_module.$auto$alumacc.cc:474:replace_alu$16139.slice[1].carry: CO=1'0
Optimized away SB_CARRY cell top_module.$auto$alumacc.cc:474:replace_alu$16154.slice[1].carry: CO=\common.pb.spirx_lencalc.byte_le [1]
Optimized away SB_CARRY cell top_module.$auto$alumacc.cc:474:replace_alu$16160.slice[1].carry: CO=\common.pb.uart.rx_mod.sym_count [1]
Optimized away SB_CARRY cell top_module.$auto$alumacc.cc:474:replace_alu$16175.slice[1].carry: CO=\common.pb.uart.tx_mod.sym_count [1]
Mapping SB_LUT4 cell top_module.$auto$alumacc.cc:474:replace_alu$16139.slice[2].adder back to logic.
Mapping SB_LUT4 cell top_module.$auto$alumacc.cc:474:replace_alu$16154.slice[2].adder back to logic.
Mapping SB_LUT4 cell top_module.$auto$alumacc.cc:474:replace_alu$16160.slice[2].adder back to logic.
Mapping SB_LUT4 cell top_module.$auto$alumacc.cc:474:replace_alu$16175.slice[2].adder back to logic.

2.31.14. Executing OPT_EXPR pass (perform const folding).
Optimizing module top_module.
<suppressed ~57 debug messages>

2.31.15. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\top_module'.
<suppressed ~9 debug messages>
Removed a total of 3 cells.

2.31.16. Executing OPT_RMDFF pass (remove dff with constant values).

2.31.17. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \top_module..
Removed 1 unused cells and 12 unused wires.
<suppressed ~2 debug messages>

2.31.18. Rerunning OPT passes. (Removed registers in this run.)

2.31.19. Running ICE40 specific optimizations.
Optimized away SB_CARRY cell top_module.$auto$alumacc.cc:474:replace_alu$16065.slice[2].carry: CO=$auto$alumacc.cc:474:replace_alu$16052.BB [2]
Optimized away SB_CARRY cell top_module.$auto$alumacc.cc:474:replace_alu$16083.slice[2].carry: CO=$auto$alumacc.cc:474:replace_alu$16083.BB [2]
Optimized away SB_CARRY cell top_module.$auto$alumacc.cc:474:replace_alu$16139.slice[2].carry: CO=1'0
Mapping SB_LUT4 cell top_module.$auto$alumacc.cc:474:replace_alu$16139.slice[3].adder back to logic.

2.31.20. Executing OPT_EXPR pass (perform const folding).
Optimizing module top_module.
<suppressed ~13 debug messages>

2.31.21. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\top_module'.
<suppressed ~3 debug messages>
Removed a total of 1 cells.

2.31.22. Executing OPT_RMDFF pass (remove dff with constant values).

2.31.23. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \top_module..
Removed 1 unused cells and 4 unused wires.
<suppressed ~2 debug messages>

2.31.24. Rerunning OPT passes. (Removed registers in this run.)

2.31.25. Running ICE40 specific optimizations.
Optimized away SB_CARRY cell top_module.$auto$alumacc.cc:474:replace_alu$16139.slice[3].carry: CO=1'0
Mapping SB_LUT4 cell top_module.$auto$alumacc.cc:474:replace_alu$16139.slice[4].adder back to logic.

2.31.26. Executing OPT_EXPR pass (perform const folding).
Optimizing module top_module.
<suppressed ~13 debug messages>

2.31.27. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\top_module'.
<suppressed ~3 debug messages>
Removed a total of 1 cells.

2.31.28. Executing OPT_RMDFF pass (remove dff with constant values).

2.31.29. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \top_module..
Removed 1 unused cells and 4 unused wires.
<suppressed ~2 debug messages>

2.31.30. Rerunning OPT passes. (Removed registers in this run.)

2.31.31. Running ICE40 specific optimizations.
Optimized away SB_CARRY cell top_module.$auto$alumacc.cc:474:replace_alu$16139.slice[4].carry: CO=1'0
Mapping SB_LUT4 cell top_module.$auto$alumacc.cc:474:replace_alu$16139.slice[5].adder back to logic.

2.31.32. Executing OPT_EXPR pass (perform const folding).
Optimizing module top_module.
<suppressed ~11 debug messages>

2.31.33. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\top_module'.
<suppressed ~3 debug messages>
Removed a total of 1 cells.

2.31.34. Executing OPT_RMDFF pass (remove dff with constant values).

2.31.35. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \top_module..
Removed 1 unused cells and 2 unused wires.
<suppressed ~2 debug messages>

2.31.36. Rerunning OPT passes. (Removed registers in this run.)

2.31.37. Running ICE40 specific optimizations.

2.31.38. Executing OPT_EXPR pass (perform const folding).
Optimizing module top_module.

2.31.39. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\top_module'.
Removed a total of 0 cells.

2.31.40. Executing OPT_RMDFF pass (remove dff with constant values).

2.31.41. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \top_module..

2.31.42. Finished OPT passes. (There is nothing left to do.)

2.32. Executing DFFSR2DFF pass (mapping DFFSR cells to simpler FFs).

2.33. Executing DFF2DFFE pass (transform $dff to $dffe where applicable).
Selected cell types for direct conversion:
  $_DFF_PP1_ -> $__DFFE_PP1
  $_DFF_PP0_ -> $__DFFE_PP0
  $_DFF_PN1_ -> $__DFFE_PN1
  $_DFF_PN0_ -> $__DFFE_PN0
  $_DFF_NP1_ -> $__DFFE_NP1
  $_DFF_NP0_ -> $__DFFE_NP0
  $_DFF_NN1_ -> $__DFFE_NN1
  $_DFF_NN0_ -> $__DFFE_NN0
  $_DFF_N_ -> $_DFFE_NP_
  $_DFF_P_ -> $_DFFE_PP_
Transforming FF to FF+Enable cells in module top_module:
  converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$16253 to $_DFFE_PP_ for $techmap\common.led_blink.$0\led_off_count[31:0] [0] -> \common.led_blink.led_off_count [0].
  converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$16254 to $_DFFE_PP_ for $techmap\common.led_blink.$0\led_off_count[31:0] [1] -> \common.led_blink.led_off_count [1].
  converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$16255 to $_DFFE_PP_ for $techmap\common.led_blink.$0\led_off_count[31:0] [2] -> \common.led_blink.led_off_count [2].
  converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$16256 to $_DFFE_PP_ for $techmap\common.led_blink.$0\led_off_count[31:0] [3] -> \common.led_blink.led_off_count [3].
  converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$16257 to $_DFFE_PP_ for $techmap\common.led_blink.$0\led_off_count[31:0] [4] -> \common.led_blink.led_off_count [4].
  converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$16258 to $_DFFE_PP_ for $techmap\common.led_blink.$0\led_off_count[31:0] [5] -> \common.led_blink.led_off_count [5].
  converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$16259 to $_DFFE_PP_ for $techmap\common.led_blink.$0\led_off_count[31:0] [6] -> \common.led_blink.led_off_count [6].
  converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$16260 to $_DFFE_PP_ for $techmap\common.led_blink.$0\led_off_count[31:0] [7] -> \common.led_blink.led_off_count [7].
  converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$16261 to $_DFFE_PP_ for $techmap\common.led_blink.$0\led_off_count[31:0] [8] -> \common.led_blink.led_off_count [8].
  converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$16262 to $_DFFE_PP_ for $techmap\common.led_blink.$0\led_off_count[31:0] [9] -> \common.led_blink.led_off_count [9].
  converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$16263 to $_DFFE_PP_ for $techmap\common.led_blink.$0\led_off_count[31:0] [10] -> \common.led_blink.led_off_count [10].
  converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$16264 to $_DFFE_PP_ for $techmap\common.led_blink.$0\led_off_count[31:0] [11] -> \common.led_blink.led_off_count [11].
  converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$16265 to $_DFFE_PP_ for $techmap\common.led_blink.$0\led_off_count[31:0] [12] -> \common.led_blink.led_off_count [12].
  converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$16266 to $_DFFE_PP_ for $techmap\common.led_blink.$0\led_off_count[31:0] [13] -> \common.led_blink.led_off_count [13].
  converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$16267 to $_DFFE_PP_ for $techmap\common.led_blink.$0\led_off_count[31:0] [14] -> \common.led_blink.led_off_count [14].
  converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$16268 to $_DFFE_PP_ for $techmap\common.led_blink.$0\led_off_count[31:0] [15] -> \common.led_blink.led_off_count [15].
  converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$16269 to $_DFFE_PP_ for $techmap\common.led_blink.$0\led_off_count[31:0] [16] -> \common.led_blink.led_off_count [16].
  converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$16270 to $_DFFE_PP_ for $techmap\common.led_blink.$0\led_off_count[31:0] [17] -> \common.led_blink.led_off_count [17].
  converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$16271 to $_DFFE_PP_ for $techmap\common.led_blink.$0\led_off_count[31:0] [18] -> \common.led_blink.led_off_count [18].
  converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$16272 to $_DFFE_PP_ for $techmap\common.led_blink.$0\led_off_count[31:0] [19] -> \common.led_blink.led_off_count [19].
  converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$16273 to $_DFFE_PP_ for $techmap\common.led_blink.$0\led_off_count[31:0] [20] -> \common.led_blink.led_off_count [20].
  converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$16274 to $_DFFE_PP_ for $techmap\common.led_blink.$0\led_off_count[31:0] [21] -> \common.led_blink.led_off_count [21].
  converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$16275 to $_DFFE_PP_ for $techmap\common.led_blink.$0\led_off_count[31:0] [22] -> \common.led_blink.led_off_count [22].
  converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$16276 to $_DFFE_PP_ for $techmap\common.led_blink.$0\led_off_count[31:0] [23] -> \common.led_blink.led_off_count [23].
  converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$16277 to $_DFFE_PP_ for $techmap\common.led_blink.$0\led_off_count[31:0] [24] -> \common.led_blink.led_off_count [24].
  converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$16278 to $_DFFE_PP_ for $techmap\common.led_blink.$0\led_off_count[31:0] [25] -> \common.led_blink.led_off_count [25].
  converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$16279 to $_DFFE_PP_ for $techmap\common.led_blink.$0\led_off_count[31:0] [26] -> \common.led_blink.led_off_count [26].
  converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$16280 to $_DFFE_PP_ for $techmap\common.led_blink.$0\led_off_count[31:0] [27] -> \common.led_blink.led_off_count [27].
  converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$16281 to $_DFFE_PP_ for $techmap\common.led_blink.$0\led_off_count[31:0] [28] -> \common.led_blink.led_off_count [28].
  converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$16282 to $_DFFE_PP_ for $techmap\common.led_blink.$0\led_off_count[31:0] [29] -> \common.led_blink.led_off_count [29].
  converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$16283 to $_DFFE_PP_ for $techmap\common.led_blink.$0\led_off_count[31:0] [30] -> \common.led_blink.led_off_count [30].
  converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$16284 to $_DFFE_PP_ for $techmap\common.led_blink.$0\led_off_count[31:0] [31] -> \common.led_blink.led_off_count [31].
  converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$16285 to $_DFFE_PP_ for $techmap\common.led_blink.$0\led_on_count[31:0] [0] -> \common.led_blink.led_on_count [0].
  converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$16286 to $_DFFE_PP_ for $techmap\common.led_blink.$0\led_on_count[31:0] [1] -> \common.led_blink.led_on_count [1].
  converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$16287 to $_DFFE_PP_ for $techmap\common.led_blink.$0\led_on_count[31:0] [2] -> \common.led_blink.led_on_count [2].
  converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$16288 to $_DFFE_PP_ for $techmap\common.led_blink.$0\led_on_count[31:0] [3] -> \common.led_blink.led_on_count [3].
  converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$16289 to $_DFFE_PP_ for $techmap\common.led_blink.$0\led_on_count[31:0] [4] -> \common.led_blink.led_on_count [4].
  converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$16290 to $_DFFE_PP_ for $techmap\common.led_blink.$0\led_on_count[31:0] [5] -> \common.led_blink.led_on_count [5].
  converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$16291 to $_DFFE_PP_ for $techmap\common.led_blink.$0\led_on_count[31:0] [6] -> \common.led_blink.led_on_count [6].
  converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$16292 to $_DFFE_PP_ for $techmap\common.led_blink.$0\led_on_count[31:0] [7] -> \common.led_blink.led_on_count [7].
  converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$16293 to $_DFFE_PP_ for $techmap\common.led_blink.$0\led_on_count[31:0] [8] -> \common.led_blink.led_on_count [8].
  converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$16294 to $_DFFE_PP_ for $techmap\common.led_blink.$0\led_on_count[31:0] [9] -> \common.led_blink.led_on_count [9].
  converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$16295 to $_DFFE_PP_ for $techmap\common.led_blink.$0\led_on_count[31:0] [10] -> \common.led_blink.led_on_count [10].
  converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$16296 to $_DFFE_PP_ for $techmap\common.led_blink.$0\led_on_count[31:0] [11] -> \common.led_blink.led_on_count [11].
  converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$16297 to $_DFFE_PP_ for $techmap\common.led_blink.$0\led_on_count[31:0] [12] -> \common.led_blink.led_on_count [12].
  converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$16298 to $_DFFE_PP_ for $techmap\common.led_blink.$0\led_on_count[31:0] [13] -> \common.led_blink.led_on_count [13].
  converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$16299 to $_DFFE_PP_ for $techmap\common.led_blink.$0\led_on_count[31:0] [14] -> \common.led_blink.led_on_count [14].
  converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$16300 to $_DFFE_PP_ for $techmap\common.led_blink.$0\led_on_count[31:0] [15] -> \common.led_blink.led_on_count [15].
  converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$16301 to $_DFFE_PP_ for $techmap\common.led_blink.$0\led_on_count[31:0] [16] -> \common.led_blink.led_on_count [16].
  converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$16302 to $_DFFE_PP_ for $techmap\common.led_blink.$0\led_on_count[31:0] [17] -> \common.led_blink.led_on_count [17].
  converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$16303 to $_DFFE_PP_ for $techmap\common.led_blink.$0\led_on_count[31:0] [18] -> \common.led_blink.led_on_count [18].
  converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$16304 to $_DFFE_PP_ for $techmap\common.led_blink.$0\led_on_count[31:0] [19] -> \common.led_blink.led_on_count [19].
  converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$16305 to $_DFFE_PP_ for $techmap\common.led_blink.$0\led_on_count[31:0] [20] -> \common.led_blink.led_on_count [20].
  converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$16306 to $_DFFE_PP_ for $techmap\common.led_blink.$0\led_on_count[31:0] [21] -> \common.led_blink.led_on_count [21].
  converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$16307 to $_DFFE_PP_ for $techmap\common.led_blink.$0\led_on_count[31:0] [22] -> \common.led_blink.led_on_count [22].
  converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$16308 to $_DFFE_PP_ for $techmap\common.led_blink.$0\led_on_count[31:0] [23] -> \common.led_blink.led_on_count [23].
  converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$16309 to $_DFFE_PP_ for $techmap\common.led_blink.$0\led_on_count[31:0] [24] -> \common.led_blink.led_on_count [24].
  converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$16310 to $_DFFE_PP_ for $techmap\common.led_blink.$0\led_on_count[31:0] [25] -> \common.led_blink.led_on_count [25].
  converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$16311 to $_DFFE_PP_ for $techmap\common.led_blink.$0\led_on_count[31:0] [26] -> \common.led_blink.led_on_count [26].
  converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$16312 to $_DFFE_PP_ for $techmap\common.led_blink.$0\led_on_count[31:0] [27] -> \common.led_blink.led_on_count [27].
  converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$16313 to $_DFFE_PP_ for $techmap\common.led_blink.$0\led_on_count[31:0] [28] -> \common.led_blink.led_on_count [28].
  converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$16314 to $_DFFE_PP_ for $techmap\common.led_blink.$0\led_on_count[31:0] [29] -> \common.led_blink.led_on_count [29].
  converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$16315 to $_DFFE_PP_ for $techmap\common.led_blink.$0\led_on_count[31:0] [30] -> \common.led_blink.led_on_count [30].
  converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$16316 to $_DFFE_PP_ for $techmap\common.led_blink.$0\led_on_count[31:0] [31] -> \common.led_blink.led_on_count [31].
  converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$17382 to $_DFFE_PP_ for $techmap\common.pb.$0\rx_buf_overflow[0:0] -> \common.pb.rx_buf_overflow [0].
  converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$17383 to $_DFFE_PP_ for $techmap\common.pb.$0\rx_buf_wr[0:0] -> \common.pb.rx_buf_wr.
  converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$17384 to $_DFFE_PP_ for $techmap\common.pb.$0\rx_buf_wr_data[8:0] [0] -> \common.pb.rx_buf_wr_data [0].
  converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$17385 to $_DFFE_PP_ for $techmap\common.pb.$0\rx_buf_wr_data[8:0] [1] -> \common.pb.rx_buf_wr_data [1].
  converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$17386 to $_DFFE_PP_ for $techmap\common.pb.$0\rx_buf_wr_data[8:0] [2] -> \common.pb.rx_buf_wr_data [2].
  converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$17387 to $_DFFE_PP_ for $techmap\common.pb.$0\rx_buf_wr_data[8:0] [3] -> \common.pb.rx_buf_wr_data [3].
  converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$17388 to $_DFFE_PP_ for $techmap\common.pb.$0\rx_buf_wr_data[8:0] [4] -> \common.pb.rx_buf_wr_data [4].
  converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$17389 to $_DFFE_PP_ for $techmap\common.pb.$0\rx_buf_wr_data[8:0] [5] -> \common.pb.rx_buf_wr_data [5].
  converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$17390 to $_DFFE_PP_ for $techmap\common.pb.$0\rx_buf_wr_data[8:0] [6] -> \common.pb.rx_buf_wr_data [6].
  converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$17391 to $_DFFE_PP_ for $techmap\common.pb.$0\rx_buf_wr_data[8:0] [7] -> \common.pb.rx_buf_wr_data [7].
  converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$17392 to $_DFFE_PP_ for $techmap\common.pb.$0\rx_buf_wr_data[8:0] [8] -> \common.pb.rx_buf_wr_data [8].
  converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$17393 to $_DFFE_PP_ for $techmap\common.pb.$0\rx_buf_wr_addr[7:0] [0] -> \common.pb.rx_buf_wr_addr [0].
  converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$17394 to $_DFFE_PP_ for $techmap\common.pb.$0\rx_buf_wr_addr[7:0] [1] -> \common.pb.rx_buf_wr_addr [1].
  converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$17395 to $_DFFE_PP_ for $techmap\common.pb.$0\rx_buf_wr_addr[7:0] [2] -> \common.pb.rx_buf_wr_addr [2].
  converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$17396 to $_DFFE_PP_ for $techmap\common.pb.$0\rx_buf_wr_addr[7:0] [3] -> \common.pb.rx_buf_wr_addr [3].
  converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$17397 to $_DFFE_PP_ for $techmap\common.pb.$0\rx_buf_wr_addr[7:0] [4] -> \common.pb.rx_buf_wr_addr [4].
  converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$17398 to $_DFFE_PP_ for $techmap\common.pb.$0\rx_buf_wr_addr[7:0] [5] -> \common.pb.rx_buf_wr_addr [5].
  converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$17399 to $_DFFE_PP_ for $techmap\common.pb.$0\rx_buf_wr_addr[7:0] [6] -> \common.pb.rx_buf_wr_addr [6].
  converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$17400 to $_DFFE_PP_ for $techmap\common.pb.$0\rx_buf_wr_addr[7:0] [7] -> \common.pb.rx_buf_wr_addr [7].
  converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$17401 to $_DFFE_PP_ for $techmap\common.pb.$0\uart_tx_data[7:0] [0] -> \common.pb.uart_tx_data [0].
  converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$17402 to $_DFFE_PP_ for $techmap\common.pb.$0\uart_tx_data[7:0] [1] -> \common.pb.uart_tx_data [1].
  converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$17403 to $_DFFE_PP_ for $techmap\common.pb.$0\uart_tx_data[7:0] [2] -> \common.pb.uart_tx_data [2].
  converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$17404 to $_DFFE_PP_ for $techmap\common.pb.$0\uart_tx_data[7:0] [3] -> \common.pb.uart_tx_data [3].
  converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$17405 to $_DFFE_PP_ for $techmap\common.pb.$0\uart_tx_data[7:0] [4] -> \common.pb.uart_tx_data [4].
  converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$17406 to $_DFFE_PP_ for $techmap\common.pb.$0\uart_tx_data[7:0] [5] -> \common.pb.uart_tx_data [5].
  converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$17407 to $_DFFE_PP_ for $techmap\common.pb.$0\uart_tx_data[7:0] [6] -> \common.pb.uart_tx_data [6].
  converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$17408 to $_DFFE_PP_ for $techmap\common.pb.$0\uart_tx_data[7:0] [7] -> \common.pb.uart_tx_data [7].
  converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$17409 to $_DFFE_PP_ for $techmap\common.pb.$0\tx_buf_rd_addr[7:0] [0] -> \common.pb.tx_buf_rd_addr [0].
  converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$17410 to $_DFFE_PP_ for $techmap\common.pb.$0\tx_buf_rd_addr[7:0] [1] -> \common.pb.tx_buf_rd_addr [1].
  converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$17411 to $_DFFE_PP_ for $techmap\common.pb.$0\tx_buf_rd_addr[7:0] [2] -> \common.pb.tx_buf_rd_addr [2].
  converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$17412 to $_DFFE_PP_ for $techmap\common.pb.$0\tx_buf_rd_addr[7:0] [3] -> \common.pb.tx_buf_rd_addr [3].
  converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$17413 to $_DFFE_PP_ for $techmap\common.pb.$0\tx_buf_rd_addr[7:0] [4] -> \common.pb.tx_buf_rd_addr [4].
  converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$17414 to $_DFFE_PP_ for $techmap\common.pb.$0\tx_buf_rd_addr[7:0] [5] -> \common.pb.tx_buf_rd_addr [5].
  converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$17415 to $_DFFE_PP_ for $techmap\common.pb.$0\tx_buf_rd_addr[7:0] [6] -> \common.pb.tx_buf_rd_addr [6].
  converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$17416 to $_DFFE_PP_ for $techmap\common.pb.$0\tx_buf_rd_addr[7:0] [7] -> \common.pb.tx_buf_rd_addr [7].
  converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$17417 to $_DFFE_PP_ for $techmap\common.pb.$0\spitx_ctrl_pending[0:0] -> \common.pb.spitx_ctrl_pending.
  converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$17418 to $_DFFE_PP_ for $techmap\common.pb.$0\spitx_ctrl_reply_data[31:0] [0] -> \common.pb.spitx_ctrl_reply_data [0].
  converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$17419 to $_DFFE_PP_ for $techmap\common.pb.$0\spitx_ctrl_reply_data[31:0] [1] -> \common.pb.spitx_ctrl_reply_data [1].
  converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$17420 to $_DFFE_PP_ for $techmap\common.pb.$0\spitx_ctrl_reply_data[31:0] [2] -> \common.pb.spitx_ctrl_reply_data [2].
  converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$17421 to $_DFFE_PP_ for $techmap\common.pb.$0\spitx_ctrl_reply_data[31:0] [3] -> \common.pb.spitx_ctrl_reply_data [3].
  converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$17422 to $_DFFE_PP_ for $techmap\common.pb.$0\spitx_ctrl_reply_data[31:0] [4] -> \common.pb.spitx_ctrl_reply_data [4].
  converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$17423 to $_DFFE_PP_ for $techmap\common.pb.$0\spitx_ctrl_reply_data[31:0] [5] -> \common.pb.spitx_ctrl_reply_data [5].
  converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$17424 to $_DFFE_PP_ for $techmap\common.pb.$0\spitx_ctrl_reply_data[31:0] [6] -> \common.pb.spitx_ctrl_reply_data [6].
  converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$17425 to $_DFFE_PP_ for $techmap\common.pb.$0\spitx_ctrl_reply_data[31:0] [7] -> \common.pb.spitx_ctrl_reply_data [7].
  converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$17426 to $_DFFE_PP_ for $techmap\common.pb.$0\spitx_ctrl_reply_data[31:0] [8] -> \common.pb.spitx_ctrl_reply_data [8].
  converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$17427 to $_DFFE_PP_ for $techmap\common.pb.$0\spitx_ctrl_reply_data[31:0] [9] -> \common.pb.spitx_ctrl_reply_data [9].
  converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$17428 to $_DFFE_PP_ for $techmap\common.pb.$0\spitx_ctrl_reply_data[31:0] [10] -> \common.pb.spitx_ctrl_reply_data [10].
  converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$17429 to $_DFFE_PP_ for $techmap\common.pb.$0\spitx_ctrl_reply_data[31:0] [11] -> \common.pb.spitx_ctrl_reply_data [11].
  converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$17430 to $_DFFE_PP_ for $techmap\common.pb.$0\spitx_ctrl_reply_data[31:0] [12] -> \common.pb.spitx_ctrl_reply_data [12].
  converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$17431 to $_DFFE_PP_ for $techmap\common.pb.$0\spitx_ctrl_reply_data[31:0] [13] -> \common.pb.spitx_ctrl_reply_data [13].
  converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$17432 to $_DFFE_PP_ for $techmap\common.pb.$0\spitx_ctrl_reply_data[31:0] [14] -> \common.pb.spitx_ctrl_reply_data [14].
  converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$17433 to $_DFFE_PP_ for $techmap\common.pb.$0\spitx_ctrl_reply_data[31:0] [15] -> \common.pb.spitx_ctrl_reply_data [15].
  converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$17434 to $_DFFE_PP_ for $techmap\common.pb.$0\spitx_ctrl_reply_data[31:0] [16] -> \common.pb.spitx_ctrl_reply_data [16].
  converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$17435 to $_DFFE_PP_ for $techmap\common.pb.$0\spitx_ctrl_reply_data[31:0] [17] -> \common.pb.spitx_ctrl_reply_data [17].
  converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$17436 to $_DFFE_PP_ for $techmap\common.pb.$0\spitx_ctrl_reply_data[31:0] [18] -> \common.pb.spitx_ctrl_reply_data [18].
  converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$17437 to $_DFFE_PP_ for $techmap\common.pb.$0\spitx_ctrl_reply_data[31:0] [19] -> \common.pb.spitx_ctrl_reply_data [19].
  converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$17438 to $_DFFE_PP_ for $techmap\common.pb.$0\spitx_ctrl_reply_data[31:0] [20] -> \common.pb.spitx_ctrl_reply_data [20].
  converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$17439 to $_DFFE_PP_ for $techmap\common.pb.$0\spitx_ctrl_reply_data[31:0] [21] -> \common.pb.spitx_ctrl_reply_data [21].
  converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$17440 to $_DFFE_PP_ for $techmap\common.pb.$0\spitx_ctrl_reply_data[31:0] [22] -> \common.pb.spitx_ctrl_reply_data [22].
  converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$17441 to $_DFFE_PP_ for $techmap\common.pb.$0\spitx_ctrl_reply_data[31:0] [23] -> \common.pb.spitx_ctrl_reply_data [23].
  converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$17442 to $_DFFE_PP_ for $techmap\common.pb.$0\spitx_ctrl_reply_data[31:0] [24] -> \common.pb.spitx_ctrl_reply_data [24].
  converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$17443 to $_DFFE_PP_ for $techmap\common.pb.$0\spitx_ctrl_reply_data[31:0] [25] -> \common.pb.spitx_ctrl_reply_data [25].
  converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$17444 to $_DFFE_PP_ for $techmap\common.pb.$0\spitx_ctrl_reply_data[31:0] [26] -> \common.pb.spitx_ctrl_reply_data [26].
  converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$17445 to $_DFFE_PP_ for $techmap\common.pb.$0\spitx_ctrl_reply_data[31:0] [27] -> \common.pb.spitx_ctrl_reply_data [27].
  converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$17446 to $_DFFE_PP_ for $techmap\common.pb.$0\spitx_ctrl_reply_data[31:0] [28] -> \common.pb.spitx_ctrl_reply_data [28].
  converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$17447 to $_DFFE_PP_ for $techmap\common.pb.$0\spitx_ctrl_reply_data[31:0] [29] -> \common.pb.spitx_ctrl_reply_data [29].
  converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$17448 to $_DFFE_PP_ for $techmap\common.pb.$0\spitx_ctrl_reply_data[31:0] [30] -> \common.pb.spitx_ctrl_reply_data [30].
  converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$17449 to $_DFFE_PP_ for $techmap\common.pb.$0\spitx_ctrl_reply_data[31:0] [31] -> \common.pb.spitx_ctrl_reply_data [31].
  converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$17450 to $_DFFE_PP_ for $techmap\common.pb.$0\spitx_ctrl_reply[7:0] [0] -> \common.pb.spitx_ctrl_reply [0].
  converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$17451 to $_DFFE_PP_ for $techmap\common.pb.$0\spitx_ctrl_reply[7:0] [1] -> \common.pb.spitx_ctrl_reply [1].
  converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$17452 to $_DFFE_PP_ for $techmap\common.pb.$0\spitx_ctrl_reply[7:0] [2] -> \common.pb.spitx_ctrl_reply [2].
  converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$17453 to $_DFFE_PP_ for $techmap\common.pb.$0\spitx_ctrl_reply[7:0] [3] -> \common.pb.spitx_ctrl_reply [3].
  converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$17454 to $_DFFE_PP_ for $techmap\common.pb.$0\spitx_ctrl_reply[7:0] [4] -> \common.pb.spitx_ctrl_reply [4].
  converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$17455 to $_DFFE_PP_ for $techmap\common.pb.$0\spitx_ctrl_reply[7:0] [5] -> \common.pb.spitx_ctrl_reply [5].
  converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$17456 to $_DFFE_PP_ for $techmap\common.pb.$0\spitx_ctrl_reply[7:0] [6] -> \common.pb.spitx_ctrl_reply [6].
  converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$17457 to $_DFFE_PP_ for $techmap\common.pb.$0\spitx_ctrl_reply[7:0] [7] -> \common.pb.spitx_ctrl_reply [7].
  converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$17458 to $_DFFE_PP_ for $techmap\common.pb.$0\spirx_lencalc_new[0:0] -> \common.pb.spirx_lencalc_new.
  converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$17459 to $_DFFE_PP_ for $techmap\common.pb.$0\spirx_lencalc_byte[7:0] [0] -> \common.pb.spirx_lencalc_byte [0].
  converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$17460 to $_DFFE_PP_ for $techmap\common.pb.$0\spirx_lencalc_byte[7:0] [1] -> \common.pb.spirx_lencalc_byte [1].
  converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$17461 to $_DFFE_PP_ for $techmap\common.pb.$0\spirx_lencalc_byte[7:0] [2] -> \common.pb.spirx_lencalc_byte [2].
  converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$17462 to $_DFFE_PP_ for $techmap\common.pb.$0\spirx_lencalc_byte[7:0] [3] -> \common.pb.spirx_lencalc_byte [3].
  converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$17463 to $_DFFE_PP_ for $techmap\common.pb.$0\spirx_lencalc_byte[7:0] [4] -> \common.pb.spirx_lencalc_byte [4].
  converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$17464 to $_DFFE_PP_ for $techmap\common.pb.$0\spirx_lencalc_byte[7:0] [5] -> \common.pb.spirx_lencalc_byte [5].
  converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$17465 to $_DFFE_PP_ for $techmap\common.pb.$0\spirx_lencalc_byte[7:0] [6] -> \common.pb.spirx_lencalc_byte [6].
  converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$17466 to $_DFFE_PP_ for $techmap\common.pb.$0\spirx_lencalc_byte[7:0] [7] -> \common.pb.spirx_lencalc_byte [7].
  converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$17468 to $_DFFE_PP_ for $techmap\common.pb.$0\spirx_ctrl_crcerr[1:0] [0] -> \common.pb.spirx_ctrl_crcerr [0].
  converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$17469 to $_DFFE_PP_ for $techmap\common.pb.$0\spirx_ctrl_crcerr[1:0] [1] -> \common.pb.spirx_ctrl_crcerr [1].
  converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$17470 to $_DFFE_PP_ for $techmap\common.pb.$0\spirx_crc[7:0] [0] -> \common.pb.spirx_crc [0].
  converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$17471 to $_DFFE_PP_ for $techmap\common.pb.$0\spirx_crc[7:0] [1] -> \common.pb.spirx_crc [1].
  converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$17472 to $_DFFE_PP_ for $techmap\common.pb.$0\spirx_crc[7:0] [2] -> \common.pb.spirx_crc [2].
  converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$17473 to $_DFFE_PP_ for $techmap\common.pb.$0\spirx_crc[7:0] [3] -> \common.pb.spirx_crc [3].
  converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$17474 to $_DFFE_PP_ for $techmap\common.pb.$0\spirx_crc[7:0] [4] -> \common.pb.spirx_crc [4].
  converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$17475 to $_DFFE_PP_ for $techmap\common.pb.$0\spirx_crc[7:0] [5] -> \common.pb.spirx_crc [5].
  converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$17476 to $_DFFE_PP_ for $techmap\common.pb.$0\spirx_crc[7:0] [6] -> \common.pb.spirx_crc [6].
  converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$17477 to $_DFFE_PP_ for $techmap\common.pb.$0\spirx_crc[7:0] [7] -> \common.pb.spirx_crc [7].
  converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$17518 to $_DFFE_PP_ for $techmap\common.pb.$0\spirx_bytecount[7:0] [0] -> \common.pb.spirx_bytecount [0].
  converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$17519 to $_DFFE_PP_ for $techmap\common.pb.$0\spirx_bytecount[7:0] [1] -> \common.pb.spirx_bytecount [1].
  converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$17520 to $_DFFE_PP_ for $techmap\common.pb.$0\spirx_bytecount[7:0] [2] -> \common.pb.spirx_bytecount [2].
  converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$17521 to $_DFFE_PP_ for $techmap\common.pb.$0\spirx_bytecount[7:0] [3] -> \common.pb.spirx_bytecount [3].
  converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$17522 to $_DFFE_PP_ for $techmap\common.pb.$0\spirx_bytecount[7:0] [4] -> \common.pb.spirx_bytecount [4].
  converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$17523 to $_DFFE_PP_ for $techmap\common.pb.$0\spirx_bytecount[7:0] [5] -> \common.pb.spirx_bytecount [5].
  converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$17524 to $_DFFE_PP_ for $techmap\common.pb.$0\spirx_bytecount[7:0] [6] -> \common.pb.spirx_bytecount [6].
  converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$17525 to $_DFFE_PP_ for $techmap\common.pb.$0\spirx_bytecount[7:0] [7] -> \common.pb.spirx_bytecount [7].
  converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$17526 to $_DFFE_PP_ for $techmap\common.pb.$0\spirx_len_valid[0:0] -> \common.pb.spirx_len_valid.
  converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$17527 to $_DFFE_PP_ for $techmap\common.pb.$0\spirx_len[7:0] [0] -> \common.pb.spirx_len [0].
  converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$17528 to $_DFFE_PP_ for $techmap\common.pb.$0\spirx_len[7:0] [1] -> \common.pb.spirx_len [1].
  converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$17529 to $_DFFE_PP_ for $techmap\common.pb.$0\spirx_len[7:0] [2] -> \common.pb.spirx_len [2].
  converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$17530 to $_DFFE_PP_ for $techmap\common.pb.$0\spirx_len[7:0] [3] -> \common.pb.spirx_len [3].
  converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$17531 to $_DFFE_PP_ for $techmap\common.pb.$0\spirx_len[7:0] [4] -> \common.pb.spirx_len [4].
  converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$17532 to $_DFFE_PP_ for $techmap\common.pb.$0\spirx_len[7:0] [5] -> \common.pb.spirx_len [5].
  converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$17533 to $_DFFE_PP_ for $techmap\common.pb.$0\spirx_len[7:0] [6] -> \common.pb.spirx_len [6].
  converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$17534 to $_DFFE_PP_ for $techmap\common.pb.$0\spirx_len[7:0] [7] -> \common.pb.spirx_len [7].
  converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$17538 to $_DFFE_PP_ for $techmap\common.pb.$0\tsyn_clks[23:0] [0] -> \common.pb.tsyn_clks [0].
  converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$17539 to $_DFFE_PP_ for $techmap\common.pb.$0\tsyn_clks[23:0] [1] -> \common.pb.tsyn_clks [1].
  converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$17540 to $_DFFE_PP_ for $techmap\common.pb.$0\tsyn_clks[23:0] [2] -> \common.pb.tsyn_clks [2].
  converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$17541 to $_DFFE_PP_ for $techmap\common.pb.$0\tsyn_clks[23:0] [3] -> \common.pb.tsyn_clks [3].
  converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$17542 to $_DFFE_PP_ for $techmap\common.pb.$0\tsyn_clks[23:0] [4] -> \common.pb.tsyn_clks [4].
  converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$17543 to $_DFFE_PP_ for $techmap\common.pb.$0\tsyn_clks[23:0] [5] -> \common.pb.tsyn_clks [5].
  converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$17544 to $_DFFE_PP_ for $techmap\common.pb.$0\tsyn_clks[23:0] [6] -> \common.pb.tsyn_clks [6].
  converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$17545 to $_DFFE_PP_ for $techmap\common.pb.$0\tsyn_clks[23:0] [7] -> \common.pb.tsyn_clks [7].
  converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$17546 to $_DFFE_PP_ for $techmap\common.pb.$0\tsyn_clks[23:0] [8] -> \common.pb.tsyn_clks [8].
  converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$17547 to $_DFFE_PP_ for $techmap\common.pb.$0\tsyn_clks[23:0] [9] -> \common.pb.tsyn_clks [9].
  converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$17548 to $_DFFE_PP_ for $techmap\common.pb.$0\tsyn_clks[23:0] [10] -> \common.pb.tsyn_clks [10].
  converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$17549 to $_DFFE_PP_ for $techmap\common.pb.$0\tsyn_clks[23:0] [11] -> \common.pb.tsyn_clks [11].
  converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$17550 to $_DFFE_PP_ for $techmap\common.pb.$0\tsyn_clks[23:0] [12] -> \common.pb.tsyn_clks [12].
  converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$17551 to $_DFFE_PP_ for $techmap\common.pb.$0\tsyn_clks[23:0] [13] -> \common.pb.tsyn_clks [13].
  converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$17552 to $_DFFE_PP_ for $techmap\common.pb.$0\tsyn_clks[23:0] [14] -> \common.pb.tsyn_clks [14].
  converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$17553 to $_DFFE_PP_ for $techmap\common.pb.$0\tsyn_clks[23:0] [15] -> \common.pb.tsyn_clks [15].
  converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$17554 to $_DFFE_PP_ for $techmap\common.pb.$0\tsyn_clks[23:0] [16] -> \common.pb.tsyn_clks [16].
  converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$17555 to $_DFFE_PP_ for $techmap\common.pb.$0\tsyn_clks[23:0] [17] -> \common.pb.tsyn_clks [17].
  converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$17556 to $_DFFE_PP_ for $techmap\common.pb.$0\tsyn_clks[23:0] [18] -> \common.pb.tsyn_clks [18].
  converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$17557 to $_DFFE_PP_ for $techmap\common.pb.$0\tsyn_clks[23:0] [19] -> \common.pb.tsyn_clks [19].
  converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$17558 to $_DFFE_PP_ for $techmap\common.pb.$0\tsyn_clks[23:0] [20] -> \common.pb.tsyn_clks [20].
  converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$17559 to $_DFFE_PP_ for $techmap\common.pb.$0\tsyn_clks[23:0] [21] -> \common.pb.tsyn_clks [21].
  converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$17560 to $_DFFE_PP_ for $techmap\common.pb.$0\tsyn_clks[23:0] [22] -> \common.pb.tsyn_clks [22].
  converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$17561 to $_DFFE_PP_ for $techmap\common.pb.$0\tsyn_clks[23:0] [23] -> \common.pb.tsyn_clks [23].
  converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$17562 to $_DFFE_PP_ for $techmap\common.pb.$0\uart_clks_per_sym[23:0] [0] -> \common.pb.uart_clks_per_sym [0].
  converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$17563 to $_DFFE_PP_ for $techmap\common.pb.$0\uart_clks_per_sym[23:0] [1] -> \common.pb.uart_clks_per_sym [1].
  converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$17564 to $_DFFE_PP_ for $techmap\common.pb.$0\uart_clks_per_sym[23:0] [2] -> \common.pb.uart_clks_per_sym [2].
  converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$17565 to $_DFFE_PP_ for $techmap\common.pb.$0\uart_clks_per_sym[23:0] [3] -> \common.pb.uart_clks_per_sym [3].
  converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$17566 to $_DFFE_PP_ for $techmap\common.pb.$0\uart_clks_per_sym[23:0] [4] -> \common.pb.uart_clks_per_sym [4].
  converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$17567 to $_DFFE_PP_ for $techmap\common.pb.$0\uart_clks_per_sym[23:0] [5] -> \common.pb.uart_clks_per_sym [5].
  converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$17568 to $_DFFE_PP_ for $techmap\common.pb.$0\uart_clks_per_sym[23:0] [6] -> \common.pb.uart_clks_per_sym [6].
  converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$17569 to $_DFFE_PP_ for $techmap\common.pb.$0\uart_clks_per_sym[23:0] [7] -> \common.pb.uart_clks_per_sym [7].
  converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$17570 to $_DFFE_PP_ for $techmap\common.pb.$0\uart_clks_per_sym[23:0] [8] -> \common.pb.uart_clks_per_sym [8].
  converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$17571 to $_DFFE_PP_ for $techmap\common.pb.$0\uart_clks_per_sym[23:0] [9] -> \common.pb.uart_clks_per_sym [9].
  converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$17572 to $_DFFE_PP_ for $techmap\common.pb.$0\uart_clks_per_sym[23:0] [10] -> \common.pb.uart_clks_per_sym [10].
  converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$17573 to $_DFFE_PP_ for $techmap\common.pb.$0\uart_clks_per_sym[23:0] [11] -> \common.pb.uart_clks_per_sym [11].
  converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$17574 to $_DFFE_PP_ for $techmap\common.pb.$0\uart_clks_per_sym[23:0] [12] -> \common.pb.uart_clks_per_sym [12].
  converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$17575 to $_DFFE_PP_ for $techmap\common.pb.$0\uart_clks_per_sym[23:0] [13] -> \common.pb.uart_clks_per_sym [13].
  converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$17576 to $_DFFE_PP_ for $techmap\common.pb.$0\uart_clks_per_sym[23:0] [14] -> \common.pb.uart_clks_per_sym [14].
  converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$17577 to $_DFFE_PP_ for $techmap\common.pb.$0\uart_clks_per_sym[23:0] [15] -> \common.pb.uart_clks_per_sym [15].
  converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$17578 to $_DFFE_PP_ for $techmap\common.pb.$0\uart_clks_per_sym[23:0] [16] -> \common.pb.uart_clks_per_sym [16].
  converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$17579 to $_DFFE_PP_ for $techmap\common.pb.$0\uart_clks_per_sym[23:0] [17] -> \common.pb.uart_clks_per_sym [17].
  converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$17580 to $_DFFE_PP_ for $techmap\common.pb.$0\uart_clks_per_sym[23:0] [18] -> \common.pb.uart_clks_per_sym [18].
  converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$17581 to $_DFFE_PP_ for $techmap\common.pb.$0\uart_clks_per_sym[23:0] [19] -> \common.pb.uart_clks_per_sym [19].
  converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$17582 to $_DFFE_PP_ for $techmap\common.pb.$0\uart_clks_per_sym[23:0] [20] -> \common.pb.uart_clks_per_sym [20].
  converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$17583 to $_DFFE_PP_ for $techmap\common.pb.$0\uart_clks_per_sym[23:0] [21] -> \common.pb.uart_clks_per_sym [21].
  converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$17584 to $_DFFE_PP_ for $techmap\common.pb.$0\uart_clks_per_sym[23:0] [22] -> \common.pb.uart_clks_per_sym [22].
  converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$17585 to $_DFFE_PP_ for $techmap\common.pb.$0\uart_clks_per_sym[23:0] [23] -> \common.pb.uart_clks_per_sym [23].
  converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$17586 to $_DFFE_PP_ for $techmap\common.pb.$0\rx_buf_overflow[1:1] -> \common.pb.rx_buf_overflow [1].
  converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$17587 to $_DFFE_PP_ for $techmap\common.pb.$0\tx_buf_overflow[1:0] [0] -> \common.pb.tx_buf_overflow [0].
  converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$17588 to $_DFFE_PP_ for $techmap\common.pb.$0\tx_buf_overflow[1:0] [1] -> \common.pb.tx_buf_overflow [1].
  converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$17606 to $_DFFE_PP_ for $techmap\common.pb.$0\softreset[0:0] -> \common.pb.softreset.
  converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$17607 to $_DFFE_PP_ for $techmap\common.pb.$0\softreset_status[0:0] -> \common.pb.softreset_status.
  converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$17608 to $_DFFE_PP_ for $techmap\common.pb.$0\n_hardreset_status[0:0] -> \common.pb.n_hardreset_status.
  converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$17609 to $_DFFE_PP_ for $techmap\common.pb.$0\n_poweronreset_status[0:0] -> \common.pb.n_poweronreset_status.
  converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$17610 to $_DFFE_PP_ for $techmap\common.pb.$0\spitx_crc[7:0] [0] -> \common.pb.spitx_crc [0].
  converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$17611 to $_DFFE_PP_ for $techmap\common.pb.$0\spitx_crc[7:0] [1] -> \common.pb.spitx_crc [1].
  converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$17612 to $_DFFE_PP_ for $techmap\common.pb.$0\spitx_crc[7:0] [2] -> \common.pb.spitx_crc [2].
  converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$17613 to $_DFFE_PP_ for $techmap\common.pb.$0\spitx_crc[7:0] [3] -> \common.pb.spitx_crc [3].
  converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$17614 to $_DFFE_PP_ for $techmap\common.pb.$0\spitx_crc[7:0] [4] -> \common.pb.spitx_crc [4].
  converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$17615 to $_DFFE_PP_ for $techmap\common.pb.$0\spitx_crc[7:0] [5] -> \common.pb.spitx_crc [5].
  converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$17616 to $_DFFE_PP_ for $techmap\common.pb.$0\spitx_crc[7:0] [6] -> \common.pb.spitx_crc [6].
  converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$17617 to $_DFFE_PP_ for $techmap\common.pb.$0\spitx_crc[7:0] [7] -> \common.pb.spitx_crc [7].
  converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$17618 to $_DFFE_PP_ for $techmap\common.pb.$0\spitx_data_running[0:0] -> \common.pb.spitx_data_running.
  converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$17619 to $_DFFE_PP_ for $techmap\common.pb.$0\spitx_ctrl_running[0:0] -> \common.pb.spitx_ctrl_running.
  converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$17620 to $_DFFE_PP_ for $techmap\common.pb.$0\spitx_tail[0:0] -> \common.pb.spitx_tail.
  converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$17621 to $_DFFE_PP_ for $techmap\common.pb.$0\spitx_len[7:0] [0] -> \common.pb.spitx_len [0].
  converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$17622 to $_DFFE_PP_ for $techmap\common.pb.$0\spitx_len[7:0] [1] -> \common.pb.spitx_len [1].
  converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$17623 to $_DFFE_PP_ for $techmap\common.pb.$0\spitx_len[7:0] [2] -> \common.pb.spitx_len [2].
  converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$17624 to $_DFFE_PP_ for $techmap\common.pb.$0\spitx_len[7:0] [3] -> \common.pb.spitx_len [3].
  converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$17625 to $_DFFE_PP_ for $techmap\common.pb.$0\spitx_len[7:0] [4] -> \common.pb.spitx_len [4].
  converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$17626 to $_DFFE_PP_ for $techmap\common.pb.$0\spitx_len[7:0] [5] -> \common.pb.spitx_len [5].
  converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$17627 to $_DFFE_PP_ for $techmap\common.pb.$0\spitx_len[7:0] [6] -> \common.pb.spitx_len [6].
  converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$17628 to $_DFFE_PP_ for $techmap\common.pb.$0\spitx_len[7:0] [7] -> \common.pb.spitx_len [7].
  converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$17629 to $_DFFE_PP_ for $techmap\common.pb.$0\spitx_bytecount[7:0] [0] -> \common.pb.spitx_bytecount [0].
  converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$17630 to $_DFFE_PP_ for $techmap\common.pb.$0\spitx_bytecount[7:0] [1] -> \common.pb.spitx_bytecount [1].
  converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$17631 to $_DFFE_PP_ for $techmap\common.pb.$0\spitx_bytecount[7:0] [2] -> \common.pb.spitx_bytecount [2].
  converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$17632 to $_DFFE_PP_ for $techmap\common.pb.$0\spitx_bytecount[7:0] [3] -> \common.pb.spitx_bytecount [3].
  converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$17633 to $_DFFE_PP_ for $techmap\common.pb.$0\spitx_bytecount[7:0] [4] -> \common.pb.spitx_bytecount [4].
  converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$17634 to $_DFFE_PP_ for $techmap\common.pb.$0\spitx_bytecount[7:0] [5] -> \common.pb.spitx_bytecount [5].
  converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$17635 to $_DFFE_PP_ for $techmap\common.pb.$0\spitx_bytecount[7:0] [6] -> \common.pb.spitx_bytecount [6].
  converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$17636 to $_DFFE_PP_ for $techmap\common.pb.$0\spitx_bytecount[7:0] [7] -> \common.pb.spitx_bytecount [7].
  converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$17637 to $_DFFE_PP_ for $techmap\common.pb.$0\spitx_ctrl_pending_ack[0:0] -> \common.pb.spitx_ctrl_pending_ack.
  converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$17638 to $_DFFE_PP_ for $techmap\common.pb.$0\spi_tx_data[7:0] [0] -> \common.pb.spi_tx_data [0].
  converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$17639 to $_DFFE_PP_ for $techmap\common.pb.$0\spi_tx_data[7:0] [1] -> \common.pb.spi_tx_data [1].
  converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$17640 to $_DFFE_PP_ for $techmap\common.pb.$0\spi_tx_data[7:0] [2] -> \common.pb.spi_tx_data [2].
  converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$17641 to $_DFFE_PP_ for $techmap\common.pb.$0\spi_tx_data[7:0] [3] -> \common.pb.spi_tx_data [3].
  converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$17642 to $_DFFE_PP_ for $techmap\common.pb.$0\spi_tx_data[7:0] [4] -> \common.pb.spi_tx_data [4].
  converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$17643 to $_DFFE_PP_ for $techmap\common.pb.$0\spi_tx_data[7:0] [5] -> \common.pb.spi_tx_data [5].
  converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$17644 to $_DFFE_PP_ for $techmap\common.pb.$0\spi_tx_data[7:0] [6] -> \common.pb.spi_tx_data [6].
  converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$17645 to $_DFFE_PP_ for $techmap\common.pb.$0\spi_tx_data[7:0] [7] -> \common.pb.spi_tx_data [7].
  converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$17646 to $_DFFE_PP_ for $techmap\common.pb.$0\rx_buf_rd_addr[7:0] [0] -> \common.pb.rx_buf_rd_addr [0].
  converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$17647 to $_DFFE_PP_ for $techmap\common.pb.$0\rx_buf_rd_addr[7:0] [1] -> \common.pb.rx_buf_rd_addr [1].
  converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$17648 to $_DFFE_PP_ for $techmap\common.pb.$0\rx_buf_rd_addr[7:0] [2] -> \common.pb.rx_buf_rd_addr [2].
  converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$17649 to $_DFFE_PP_ for $techmap\common.pb.$0\rx_buf_rd_addr[7:0] [3] -> \common.pb.rx_buf_rd_addr [3].
  converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$17650 to $_DFFE_PP_ for $techmap\common.pb.$0\rx_buf_rd_addr[7:0] [4] -> \common.pb.rx_buf_rd_addr [4].
  converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$17651 to $_DFFE_PP_ for $techmap\common.pb.$0\rx_buf_rd_addr[7:0] [5] -> \common.pb.rx_buf_rd_addr [5].
  converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$17652 to $_DFFE_PP_ for $techmap\common.pb.$0\rx_buf_rd_addr[7:0] [6] -> \common.pb.rx_buf_rd_addr [6].
  converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$17653 to $_DFFE_PP_ for $techmap\common.pb.$0\rx_buf_rd_addr[7:0] [7] -> \common.pb.rx_buf_rd_addr [7].
  converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$17654 to $_DFFE_PP_ for $techmap\common.pb.$0\timer_idle_saved[23:0] [0] -> \common.pb.timer_idle_saved [0].
  converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$17655 to $_DFFE_PP_ for $techmap\common.pb.$0\timer_idle_saved[23:0] [1] -> \common.pb.timer_idle_saved [1].
  converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$17656 to $_DFFE_PP_ for $techmap\common.pb.$0\timer_idle_saved[23:0] [2] -> \common.pb.timer_idle_saved [2].
  converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$17657 to $_DFFE_PP_ for $techmap\common.pb.$0\timer_idle_saved[23:0] [3] -> \common.pb.timer_idle_saved [3].
  converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$17658 to $_DFFE_PP_ for $techmap\common.pb.$0\timer_idle_saved[23:0] [4] -> \common.pb.timer_idle_saved [4].
  converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$17659 to $_DFFE_PP_ for $techmap\common.pb.$0\timer_idle_saved[23:0] [5] -> \common.pb.timer_idle_saved [5].
  converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$17660 to $_DFFE_PP_ for $techmap\common.pb.$0\timer_idle_saved[23:0] [6] -> \common.pb.timer_idle_saved [6].
  converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$17661 to $_DFFE_PP_ for $techmap\common.pb.$0\timer_idle_saved[23:0] [7] -> \common.pb.timer_idle_saved [7].
  converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$17662 to $_DFFE_PP_ for $techmap\common.pb.$0\timer_idle_saved[23:0] [8] -> \common.pb.timer_idle_saved [8].
  converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$17663 to $_DFFE_PP_ for $techmap\common.pb.$0\timer_idle_saved[23:0] [9] -> \common.pb.timer_idle_saved [9].
  converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$17664 to $_DFFE_PP_ for $techmap\common.pb.$0\timer_idle_saved[23:0] [10] -> \common.pb.timer_idle_saved [10].
  converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$17665 to $_DFFE_PP_ for $techmap\common.pb.$0\timer_idle_saved[23:0] [11] -> \common.pb.timer_idle_saved [11].
  converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$17666 to $_DFFE_PP_ for $techmap\common.pb.$0\timer_idle_saved[23:0] [12] -> \common.pb.timer_idle_saved [12].
  converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$17667 to $_DFFE_PP_ for $techmap\common.pb.$0\timer_idle_saved[23:0] [13] -> \common.pb.timer_idle_saved [13].
  converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$17668 to $_DFFE_PP_ for $techmap\common.pb.$0\timer_idle_saved[23:0] [14] -> \common.pb.timer_idle_saved [14].
  converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$17669 to $_DFFE_PP_ for $techmap\common.pb.$0\timer_idle_saved[23:0] [15] -> \common.pb.timer_idle_saved [15].
  converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$17670 to $_DFFE_PP_ for $techmap\common.pb.$0\timer_idle_saved[23:0] [16] -> \common.pb.timer_idle_saved [16].
  converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$17671 to $_DFFE_PP_ for $techmap\common.pb.$0\timer_idle_saved[23:0] [17] -> \common.pb.timer_idle_saved [17].
  converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$17672 to $_DFFE_PP_ for $techmap\common.pb.$0\timer_idle_saved[23:0] [18] -> \common.pb.timer_idle_saved [18].
  converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$17673 to $_DFFE_PP_ for $techmap\common.pb.$0\timer_idle_saved[23:0] [19] -> \common.pb.timer_idle_saved [19].
  converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$17674 to $_DFFE_PP_ for $techmap\common.pb.$0\timer_idle_saved[23:0] [20] -> \common.pb.timer_idle_saved [20].
  converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$17675 to $_DFFE_PP_ for $techmap\common.pb.$0\timer_idle_saved[23:0] [21] -> \common.pb.timer_idle_saved [21].
  converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$17676 to $_DFFE_PP_ for $techmap\common.pb.$0\timer_idle_saved[23:0] [22] -> \common.pb.timer_idle_saved [22].
  converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$17677 to $_DFFE_PP_ for $techmap\common.pb.$0\timer_idle_saved[23:0] [23] -> \common.pb.timer_idle_saved [23].
  converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$17678 to $_DFFE_PP_ for $techmap\common.pb.$0\timer_idle[23:0] [0] -> \common.pb.timer_idle [0].
  converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$17679 to $_DFFE_PP_ for $techmap\common.pb.$0\timer_idle[23:0] [1] -> \common.pb.timer_idle [1].
  converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$17680 to $_DFFE_PP_ for $techmap\common.pb.$0\timer_idle[23:0] [2] -> \common.pb.timer_idle [2].
  converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$17681 to $_DFFE_PP_ for $techmap\common.pb.$0\timer_idle[23:0] [3] -> \common.pb.timer_idle [3].
  converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$17682 to $_DFFE_PP_ for $techmap\common.pb.$0\timer_idle[23:0] [4] -> \common.pb.timer_idle [4].
  converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$17683 to $_DFFE_PP_ for $techmap\common.pb.$0\timer_idle[23:0] [5] -> \common.pb.timer_idle [5].
  converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$17684 to $_DFFE_PP_ for $techmap\common.pb.$0\timer_idle[23:0] [6] -> \common.pb.timer_idle [6].
  converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$17685 to $_DFFE_PP_ for $techmap\common.pb.$0\timer_idle[23:0] [7] -> \common.pb.timer_idle [7].
  converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$17686 to $_DFFE_PP_ for $techmap\common.pb.$0\timer_idle[23:0] [8] -> \common.pb.timer_idle [8].
  converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$17687 to $_DFFE_PP_ for $techmap\common.pb.$0\timer_idle[23:0] [9] -> \common.pb.timer_idle [9].
  converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$17688 to $_DFFE_PP_ for $techmap\common.pb.$0\timer_idle[23:0] [10] -> \common.pb.timer_idle [10].
  converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$17689 to $_DFFE_PP_ for $techmap\common.pb.$0\timer_idle[23:0] [11] -> \common.pb.timer_idle [11].
  converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$17690 to $_DFFE_PP_ for $techmap\common.pb.$0\timer_idle[23:0] [12] -> \common.pb.timer_idle [12].
  converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$17691 to $_DFFE_PP_ for $techmap\common.pb.$0\timer_idle[23:0] [13] -> \common.pb.timer_idle [13].
  converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$17692 to $_DFFE_PP_ for $techmap\common.pb.$0\timer_idle[23:0] [14] -> \common.pb.timer_idle [14].
  converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$17693 to $_DFFE_PP_ for $techmap\common.pb.$0\timer_idle[23:0] [15] -> \common.pb.timer_idle [15].
  converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$17694 to $_DFFE_PP_ for $techmap\common.pb.$0\timer_idle[23:0] [16] -> \common.pb.timer_idle [16].
  converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$17695 to $_DFFE_PP_ for $techmap\common.pb.$0\timer_idle[23:0] [17] -> \common.pb.timer_idle [17].
  converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$17696 to $_DFFE_PP_ for $techmap\common.pb.$0\timer_idle[23:0] [18] -> \common.pb.timer_idle [18].
  converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$17697 to $_DFFE_PP_ for $techmap\common.pb.$0\timer_idle[23:0] [19] -> \common.pb.timer_idle [19].
  converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$17698 to $_DFFE_PP_ for $techmap\common.pb.$0\timer_idle[23:0] [20] -> \common.pb.timer_idle [20].
  converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$17699 to $_DFFE_PP_ for $techmap\common.pb.$0\timer_idle[23:0] [21] -> \common.pb.timer_idle [21].
  converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$17700 to $_DFFE_PP_ for $techmap\common.pb.$0\timer_idle[23:0] [22] -> \common.pb.timer_idle [22].
  converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$17701 to $_DFFE_PP_ for $techmap\common.pb.$0\timer_idle[23:0] [23] -> \common.pb.timer_idle [23].
  converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$20357 to $_DFFE_PP_ for $techmap\common.pb.spi.$0\bit_count[5:0] [0] -> \common.pb.spi.bit_count [0].
  converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$20358 to $_DFFE_PP_ for $techmap\common.pb.spi.$0\bit_count[5:0] [1] -> \common.pb.spi.bit_count [1].
  converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$20359 to $_DFFE_PP_ for $techmap\common.pb.spi.$0\bit_count[5:0] [2] -> \common.pb.spi.bit_count [2].
  converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$20360 to $_DFFE_PP_ for $techmap\common.pb.spi.$0\bit_count[5:0] [3] -> \common.pb.spi.bit_count [3].
  converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$20361 to $_DFFE_PP_ for $techmap\common.pb.spi.$0\bit_count[5:0] [4] -> \common.pb.spi.bit_count [4].
  converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$20362 to $_DFFE_PP_ for $techmap\common.pb.spi.$0\bit_count[5:0] [5] -> \common.pb.spi.bit_count [5].
  converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$20363 to $_DFFE_PP_ for $techmap\common.pb.spi.$0\tx_shiftreg[7:0] [0] -> \common.pb.spi.tx_shiftreg [0].
  converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$20364 to $_DFFE_PP_ for $techmap\common.pb.spi.$0\tx_shiftreg[7:0] [1] -> \common.pb.spi.tx_shiftreg [1].
  converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$20365 to $_DFFE_PP_ for $techmap\common.pb.spi.$0\tx_shiftreg[7:0] [2] -> \common.pb.spi.tx_shiftreg [2].
  converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$20366 to $_DFFE_PP_ for $techmap\common.pb.spi.$0\tx_shiftreg[7:0] [3] -> \common.pb.spi.tx_shiftreg [3].
  converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$20367 to $_DFFE_PP_ for $techmap\common.pb.spi.$0\tx_shiftreg[7:0] [4] -> \common.pb.spi.tx_shiftreg [4].
  converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$20368 to $_DFFE_PP_ for $techmap\common.pb.spi.$0\tx_shiftreg[7:0] [5] -> \common.pb.spi.tx_shiftreg [5].
  converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$20369 to $_DFFE_PP_ for $techmap\common.pb.spi.$0\tx_shiftreg[7:0] [6] -> \common.pb.spi.tx_shiftreg [6].
  converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$20370 to $_DFFE_PP_ for $techmap\common.pb.spi.$0\tx_shiftreg[7:0] [7] -> \common.pb.spi.tx_shiftreg [7].
  converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$20371 to $_DFFE_PP_ for $techmap\common.pb.spi.$0\rx_shiftreg[7:0] [0] -> \common.pb.spi.rx_shiftreg [0].
  converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$20372 to $_DFFE_PP_ for $techmap\common.pb.spi.$0\rx_shiftreg[7:0] [1] -> \common.pb.spi.rx_shiftreg [1].
  converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$20373 to $_DFFE_PP_ for $techmap\common.pb.spi.$0\rx_shiftreg[7:0] [2] -> \common.pb.spi.rx_shiftreg [2].
  converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$20374 to $_DFFE_PP_ for $techmap\common.pb.spi.$0\rx_shiftreg[7:0] [3] -> \common.pb.spi.rx_shiftreg [3].
  converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$20375 to $_DFFE_PP_ for $techmap\common.pb.spi.$0\rx_shiftreg[7:0] [4] -> \common.pb.spi.rx_shiftreg [4].
  converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$20376 to $_DFFE_PP_ for $techmap\common.pb.spi.$0\rx_shiftreg[7:0] [5] -> \common.pb.spi.rx_shiftreg [5].
  converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$20377 to $_DFFE_PP_ for $techmap\common.pb.spi.$0\rx_shiftreg[7:0] [6] -> \common.pb.spi.rx_shiftreg [6].
  converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$20378 to $_DFFE_PP_ for $techmap\common.pb.spi.$0\rx_shiftreg[7:0] [7] -> \common.pb.spi.rx_shiftreg [7].
  converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$20379 to $_DFFE_PP_ for $techmap\common.pb.spi.$0\rx_data_r[7:0] [0] -> \common.pb.spi.rx_data_r [0].
  converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$20380 to $_DFFE_PP_ for $techmap\common.pb.spi.$0\rx_data_r[7:0] [1] -> \common.pb.spi.rx_data_r [1].
  converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$20381 to $_DFFE_PP_ for $techmap\common.pb.spi.$0\rx_data_r[7:0] [2] -> \common.pb.spi.rx_data_r [2].
  converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$20382 to $_DFFE_PP_ for $techmap\common.pb.spi.$0\rx_data_r[7:0] [3] -> \common.pb.spi.rx_data_r [3].
  converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$20383 to $_DFFE_PP_ for $techmap\common.pb.spi.$0\rx_data_r[7:0] [4] -> \common.pb.spi.rx_data_r [4].
  converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$20384 to $_DFFE_PP_ for $techmap\common.pb.spi.$0\rx_data_r[7:0] [5] -> \common.pb.spi.rx_data_r [5].
  converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$20385 to $_DFFE_PP_ for $techmap\common.pb.spi.$0\rx_data_r[7:0] [6] -> \common.pb.spi.rx_data_r [6].
  converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$20386 to $_DFFE_PP_ for $techmap\common.pb.spi.$0\rx_data_r[7:0] [7] -> \common.pb.spi.rx_data_r [7].
  converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$20387 to $_DFFE_PP_ for $techmap\common.pb.spi.$0\miso_r[0:0] -> \common.pb.spi.miso_r.
  converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$20476 to $_DFFE_PP_ for $techmap\common.pb.uart.$0\tx_data_r[7:0] [0] -> \common.pb.uart.tx_data_r [0].
  converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$20477 to $_DFFE_PP_ for $techmap\common.pb.uart.$0\tx_data_r[7:0] [1] -> \common.pb.uart.tx_data_r [1].
  converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$20478 to $_DFFE_PP_ for $techmap\common.pb.uart.$0\tx_data_r[7:0] [2] -> \common.pb.uart.tx_data_r [2].
  converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$20479 to $_DFFE_PP_ for $techmap\common.pb.uart.$0\tx_data_r[7:0] [3] -> \common.pb.uart.tx_data_r [3].
  converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$20480 to $_DFFE_PP_ for $techmap\common.pb.uart.$0\tx_data_r[7:0] [4] -> \common.pb.uart.tx_data_r [4].
  converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$20481 to $_DFFE_PP_ for $techmap\common.pb.uart.$0\tx_data_r[7:0] [5] -> \common.pb.uart.tx_data_r [5].
  converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$20482 to $_DFFE_PP_ for $techmap\common.pb.uart.$0\tx_data_r[7:0] [6] -> \common.pb.uart.tx_data_r [6].
  converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$20483 to $_DFFE_PP_ for $techmap\common.pb.uart.$0\tx_data_r[7:0] [7] -> \common.pb.uart.tx_data_r [7].
  converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$20539 to $_DFFE_PP_ for $techmap\common.pb.uart.tx_mod.$0\symclk_n_reset[0:0] -> \common.pb.uart.tx_mod.symclk_n_reset.
  converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$20540 to $_DFFE_PP_ for $techmap\common.pb.uart.tx_mod.$0\tx_active[0:0] -> \common.pb.uart.tx_mod.tx_active.
  converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$20541 to $_DFFE_PP_ for $techmap\common.pb.uart.tx_mod.$0\tx_buf[7:0] [0] -> \common.pb.uart.tx_mod.tx_buf [0].
  converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$20542 to $_DFFE_PP_ for $techmap\common.pb.uart.tx_mod.$0\tx_buf[7:0] [1] -> \common.pb.uart.tx_mod.tx_buf [1].
  converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$20543 to $_DFFE_PP_ for $techmap\common.pb.uart.tx_mod.$0\tx_buf[7:0] [2] -> \common.pb.uart.tx_mod.tx_buf [2].
  converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$20544 to $_DFFE_PP_ for $techmap\common.pb.uart.tx_mod.$0\tx_buf[7:0] [3] -> \common.pb.uart.tx_mod.tx_buf [3].
  converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$20545 to $_DFFE_PP_ for $techmap\common.pb.uart.tx_mod.$0\tx_buf[7:0] [4] -> \common.pb.uart.tx_mod.tx_buf [4].
  converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$20546 to $_DFFE_PP_ for $techmap\common.pb.uart.tx_mod.$0\tx_buf[7:0] [5] -> \common.pb.uart.tx_mod.tx_buf [5].
  converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$20547 to $_DFFE_PP_ for $techmap\common.pb.uart.tx_mod.$0\tx_buf[7:0] [6] -> \common.pb.uart.tx_mod.tx_buf [6].
  converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$20548 to $_DFFE_PP_ for $techmap\common.pb.uart.tx_mod.$0\tx_buf[7:0] [7] -> \common.pb.uart.tx_mod.tx_buf [7].
  converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$20549 to $_DFFE_PP_ for $techmap\common.pb.uart.tx_mod.$0\tx_r[0:0] -> \common.pb.uart.tx_mod.tx_r.
  converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$20550 to $_DFFE_PP_ for $techmap\common.pb.uart.tx_mod.$0\tx_irq[0:0] -> \common.pb.uart.tx_mod.tx_irq.
  converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$20551 to $_DFFE_PP_ for $techmap\common.pb.uart.tx_mod.$0\sym_count[3:0] [0] -> \common.pb.uart.tx_mod.sym_count [0].
  converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$20552 to $_DFFE_PP_ for $techmap\common.pb.uart.tx_mod.$0\sym_count[3:0] [1] -> \common.pb.uart.tx_mod.sym_count [1].
  converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$20553 to $_DFFE_PP_ for $techmap\common.pb.uart.tx_mod.$0\sym_count[3:0] [2] -> \common.pb.uart.tx_mod.sym_count [2].
  converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$20554 to $_DFFE_PP_ for $techmap\common.pb.uart.tx_mod.$0\sym_count[3:0] [3] -> \common.pb.uart.tx_mod.sym_count [3].
  converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$20916 to $_DFFE_PP_ for $techmap\common.pb.uart.rx_mod.$0\rx_irq[0:0] -> \common.pb.uart.rx_mod.rx_irq.
  converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$20941 to $_DFFE_PP_ for $techmap\common.pb.uart.rx_mod.$0\symclk_n_reset[0:0] -> \common.pb.uart.rx_mod.symclk_n_reset.
  converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$20942 to $_DFFE_PP_ for $techmap\common.pb.uart.rx_mod.$0\rx_frame_error_start[0:0] -> \common.pb.uart.rx_mod.rx_frame_error_start.
  converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$20943 to $_DFFE_PP_ for $techmap\common.pb.uart.rx_mod.$0\rx_parity_buf[0:0] -> \common.pb.uart.rx_mod.rx_parity_buf.
  converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$20944 to $_DFFE_PP_ for $techmap\common.pb.uart.rx_mod.$0\rx_buf[7:0] [0] -> \common.pb.uart.rx_mod.rx_buf [0].
  converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$20945 to $_DFFE_PP_ for $techmap\common.pb.uart.rx_mod.$0\rx_buf[7:0] [1] -> \common.pb.uart.rx_mod.rx_buf [1].
  converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$20946 to $_DFFE_PP_ for $techmap\common.pb.uart.rx_mod.$0\rx_buf[7:0] [2] -> \common.pb.uart.rx_mod.rx_buf [2].
  converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$20947 to $_DFFE_PP_ for $techmap\common.pb.uart.rx_mod.$0\rx_buf[7:0] [3] -> \common.pb.uart.rx_mod.rx_buf [3].
  converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$20948 to $_DFFE_PP_ for $techmap\common.pb.uart.rx_mod.$0\rx_buf[7:0] [4] -> \common.pb.uart.rx_mod.rx_buf [4].
  converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$20949 to $_DFFE_PP_ for $techmap\common.pb.uart.rx_mod.$0\rx_buf[7:0] [5] -> \common.pb.uart.rx_mod.rx_buf [5].
  converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$20950 to $_DFFE_PP_ for $techmap\common.pb.uart.rx_mod.$0\rx_buf[7:0] [6] -> \common.pb.uart.rx_mod.rx_buf [6].
  converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$20951 to $_DFFE_PP_ for $techmap\common.pb.uart.rx_mod.$0\rx_buf[7:0] [7] -> \common.pb.uart.rx_mod.rx_buf [7].
  converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$20952 to $_DFFE_PP_ for $techmap\common.pb.uart.rx_mod.$0\sym_count[3:0] [0] -> \common.pb.uart.rx_mod.sym_count [0].
  converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$20953 to $_DFFE_PP_ for $techmap\common.pb.uart.rx_mod.$0\sym_count[3:0] [1] -> \common.pb.uart.rx_mod.sym_count [1].
  converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$20954 to $_DFFE_PP_ for $techmap\common.pb.uart.rx_mod.$0\sym_count[3:0] [2] -> \common.pb.uart.rx_mod.sym_count [2].
  converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$20955 to $_DFFE_PP_ for $techmap\common.pb.uart.rx_mod.$0\sym_count[3:0] [3] -> \common.pb.uart.rx_mod.sym_count [3].
  converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$20956 to $_DFFE_PP_ for $techmap\common.pb.uart.rx_mod.$0\rx_data[7:0] [0] -> \common.pb.uart.rx_mod.rx_data [0].
  converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$20957 to $_DFFE_PP_ for $techmap\common.pb.uart.rx_mod.$0\rx_data[7:0] [1] -> \common.pb.uart.rx_mod.rx_data [1].
  converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$20958 to $_DFFE_PP_ for $techmap\common.pb.uart.rx_mod.$0\rx_data[7:0] [2] -> \common.pb.uart.rx_mod.rx_data [2].
  converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$20959 to $_DFFE_PP_ for $techmap\common.pb.uart.rx_mod.$0\rx_data[7:0] [3] -> \common.pb.uart.rx_mod.rx_data [3].
  converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$20960 to $_DFFE_PP_ for $techmap\common.pb.uart.rx_mod.$0\rx_data[7:0] [4] -> \common.pb.uart.rx_mod.rx_data [4].
  converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$20961 to $_DFFE_PP_ for $techmap\common.pb.uart.rx_mod.$0\rx_data[7:0] [5] -> \common.pb.uart.rx_mod.rx_data [5].
  converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$20962 to $_DFFE_PP_ for $techmap\common.pb.uart.rx_mod.$0\rx_data[7:0] [6] -> \common.pb.uart.rx_mod.rx_data [6].
  converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$20963 to $_DFFE_PP_ for $techmap\common.pb.uart.rx_mod.$0\rx_data[7:0] [7] -> \common.pb.uart.rx_mod.rx_data [7].
  converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$20964 to $_DFFE_PP_ for $techmap\common.pb.uart.rx_mod.$0\rx_frame_error[0:0] -> \common.pb.uart.rx_mod.rx_frame_error.
  converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$20965 to $_DFFE_PP_ for $techmap\common.pb.uart.rx_mod.$0\rx_parity_ok[0:0] -> \common.pb.uart.rx_mod.rx_parity_ok.
  converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$20966 to $_DFFE_PP_ for $techmap\common.pb.uart.rx_mod.$0\rx_active[0:0] -> \common.pb.uart.rx_mod.rx_active.

2.34. Executing TECHMAP pass (map to technology primitives).

2.34.1. Executing Verilog-2005 frontend: /home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v
Parsing Verilog input from `/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v' to AST representation.
Generating RTLIL representation for module `\$_DFF_N_'.
Generating RTLIL representation for module `\$_DFF_P_'.
Generating RTLIL representation for module `\$_DFFE_NN_'.
Generating RTLIL representation for module `\$_DFFE_PN_'.
Generating RTLIL representation for module `\$_DFFE_NP_'.
Generating RTLIL representation for module `\$_DFFE_PP_'.
Generating RTLIL representation for module `\$_DFF_NN0_'.
Generating RTLIL representation for module `\$_DFF_NN1_'.
Generating RTLIL representation for module `\$_DFF_PN0_'.
Generating RTLIL representation for module `\$_DFF_PN1_'.
Generating RTLIL representation for module `\$_DFF_NP0_'.
Generating RTLIL representation for module `\$_DFF_NP1_'.
Generating RTLIL representation for module `\$_DFF_PP0_'.
Generating RTLIL representation for module `\$_DFF_PP1_'.
Generating RTLIL representation for module `\$__DFFE_NN0'.
Generating RTLIL representation for module `\$__DFFE_NN1'.
Generating RTLIL representation for module `\$__DFFE_PN0'.
Generating RTLIL representation for module `\$__DFFE_PN1'.
Generating RTLIL representation for module `\$__DFFE_NP0'.
Generating RTLIL representation for module `\$__DFFE_NP1'.
Generating RTLIL representation for module `\$__DFFE_PP0'.
Generating RTLIL representation for module `\$__DFFE_PP1'.
Successfully finished Verilog frontend.

2.34.2. Continuing TECHMAP pass.
Using template \$_DFF_P_ for cells of type $_DFF_P_.
Using template \$_DFFE_PP_ for cells of type $_DFFE_PP_.
No more expansions possible.
<suppressed ~545 debug messages>

2.35. Executing OPT_EXPR pass (perform const folding).
Optimizing module top_module.
<suppressed ~2784 debug messages>

2.36. Executing SIMPLEMAP pass (map simple cells to gate primitives).

2.37. Executing ICE40_FFINIT pass (implement FF init values).
Handling FF init values in top_module.
FF init value for cell $auto$simplemap.cc:420:simplemap_dff$16251 (SB_DFF): \common.led_blink.led = 0
FF init value for cell $auto$simplemap.cc:420:simplemap_dff$16252 (SB_DFF): \common.pb.uart_tx_trigger = 0
FF init value for cell $auto$simplemap.cc:420:simplemap_dff$21860 (SB_DFF): \common.pb.uart.tx_mod.symclk.count [6] = 0
FF init value for cell $auto$simplemap.cc:420:simplemap_dff$16254 (SB_DFFE): \common.led_blink.led_off_count [1] = 0
FF init value for cell $auto$simplemap.cc:420:simplemap_dff$16255 (SB_DFFE): \common.led_blink.led_off_count [2] = 0
FF init value for cell $auto$simplemap.cc:420:simplemap_dff$16256 (SB_DFFE): \common.led_blink.led_off_count [3] = 0
FF init value for cell $auto$simplemap.cc:420:simplemap_dff$16257 (SB_DFFE): \common.led_blink.led_off_count [4] = 0
FF init value for cell $auto$simplemap.cc:420:simplemap_dff$16258 (SB_DFFE): \common.led_blink.led_off_count [5] = 0
FF init value for cell $auto$simplemap.cc:420:simplemap_dff$16259 (SB_DFFE): \common.led_blink.led_off_count [6] = 0
FF init value for cell $auto$simplemap.cc:420:simplemap_dff$16260 (SB_DFFE): \common.led_blink.led_off_count [7] = 0
FF init value for cell $auto$simplemap.cc:420:simplemap_dff$16261 (SB_DFFE): \common.led_blink.led_off_count [8] = 0
FF init value for cell $auto$simplemap.cc:420:simplemap_dff$16262 (SB_DFFE): \common.led_blink.led_off_count [9] = 0
FF init value for cell $auto$simplemap.cc:420:simplemap_dff$16263 (SB_DFFE): \common.led_blink.led_off_count [10] = 0
FF init value for cell $auto$simplemap.cc:420:simplemap_dff$16264 (SB_DFFE): \common.led_blink.led_off_count [11] = 0
FF init value for cell $auto$simplemap.cc:420:simplemap_dff$16265 (SB_DFFE): \common.led_blink.led_off_count [12] = 0
FF init value for cell $auto$simplemap.cc:420:simplemap_dff$16266 (SB_DFFE): \common.led_blink.led_off_count [13] = 0
FF init value for cell $auto$simplemap.cc:420:simplemap_dff$16267 (SB_DFFE): \common.led_blink.led_off_count [14] = 0
FF init value for cell $auto$simplemap.cc:420:simplemap_dff$16268 (SB_DFFE): \common.led_blink.led_off_count [15] = 0
FF init value for cell $auto$simplemap.cc:420:simplemap_dff$16269 (SB_DFFE): \common.led_blink.led_off_count [16] = 0
FF init value for cell $auto$simplemap.cc:420:simplemap_dff$16270 (SB_DFFE): \common.led_blink.led_off_count [17] = 0
FF init value for cell $auto$simplemap.cc:420:simplemap_dff$16271 (SB_DFFE): \common.led_blink.led_off_count [18] = 0
FF init value for cell $auto$simplemap.cc:420:simplemap_dff$16272 (SB_DFFE): \common.led_blink.led_off_count [19] = 0
FF init value for cell $auto$simplemap.cc:420:simplemap_dff$16273 (SB_DFFE): \common.led_blink.led_off_count [20] = 0
FF init value for cell $auto$simplemap.cc:420:simplemap_dff$16274 (SB_DFFE): \common.led_blink.led_off_count [21] = 0
FF init value for cell $auto$simplemap.cc:420:simplemap_dff$16275 (SB_DFFE): \common.led_blink.led_off_count [22] = 0
FF init value for cell $auto$simplemap.cc:420:simplemap_dff$16276 (SB_DFFE): \common.led_blink.led_off_count [23] = 0
FF init value for cell $auto$simplemap.cc:420:simplemap_dff$16277 (SB_DFFE): \common.led_blink.led_off_count [24] = 0
FF init value for cell $auto$simplemap.cc:420:simplemap_dff$16278 (SB_DFFE): \common.led_blink.led_off_count [25] = 0
FF init value for cell $auto$simplemap.cc:420:simplemap_dff$16279 (SB_DFFE): \common.led_blink.led_off_count [26] = 0
FF init value for cell $auto$simplemap.cc:420:simplemap_dff$16280 (SB_DFFE): \common.led_blink.led_off_count [27] = 0
FF init value for cell $auto$simplemap.cc:420:simplemap_dff$16281 (SB_DFFE): \common.led_blink.led_off_count [28] = 0
FF init value for cell $auto$simplemap.cc:420:simplemap_dff$16282 (SB_DFFE): \common.led_blink.led_off_count [29] = 0
FF init value for cell $auto$simplemap.cc:420:simplemap_dff$16283 (SB_DFFE): \common.led_blink.led_off_count [30] = 0
FF init value for cell $auto$simplemap.cc:420:simplemap_dff$16253 (SB_DFFE): \common.led_blink.led_off_count [0] = 0
FF init value for cell $auto$simplemap.cc:420:simplemap_dff$16284 (SB_DFFE): \common.led_blink.led_off_count [31] = 0
FF init value for cell $auto$simplemap.cc:420:simplemap_dff$16286 (SB_DFFE): \common.led_blink.led_on_count [1] = 0
FF init value for cell $auto$simplemap.cc:420:simplemap_dff$16287 (SB_DFFE): \common.led_blink.led_on_count [2] = 0
FF init value for cell $auto$simplemap.cc:420:simplemap_dff$16288 (SB_DFFE): \common.led_blink.led_on_count [3] = 0
FF init value for cell $auto$simplemap.cc:420:simplemap_dff$16289 (SB_DFFE): \common.led_blink.led_on_count [4] = 0
FF init value for cell $auto$simplemap.cc:420:simplemap_dff$16290 (SB_DFFE): \common.led_blink.led_on_count [5] = 0
FF init value for cell $auto$simplemap.cc:420:simplemap_dff$16291 (SB_DFFE): \common.led_blink.led_on_count [6] = 0
FF init value for cell $auto$simplemap.cc:420:simplemap_dff$16292 (SB_DFFE): \common.led_blink.led_on_count [7] = 0
FF init value for cell $auto$simplemap.cc:420:simplemap_dff$16293 (SB_DFFE): \common.led_blink.led_on_count [8] = 0
FF init value for cell $auto$simplemap.cc:420:simplemap_dff$16294 (SB_DFFE): \common.led_blink.led_on_count [9] = 0
FF init value for cell $auto$simplemap.cc:420:simplemap_dff$16295 (SB_DFFE): \common.led_blink.led_on_count [10] = 0
FF init value for cell $auto$simplemap.cc:420:simplemap_dff$16296 (SB_DFFE): \common.led_blink.led_on_count [11] = 0
FF init value for cell $auto$simplemap.cc:420:simplemap_dff$16297 (SB_DFFE): \common.led_blink.led_on_count [12] = 0
FF init value for cell $auto$simplemap.cc:420:simplemap_dff$16298 (SB_DFFE): \common.led_blink.led_on_count [13] = 0
FF init value for cell $auto$simplemap.cc:420:simplemap_dff$16299 (SB_DFFE): \common.led_blink.led_on_count [14] = 0
FF init value for cell $auto$simplemap.cc:420:simplemap_dff$16300 (SB_DFFE): \common.led_blink.led_on_count [15] = 0
FF init value for cell $auto$simplemap.cc:420:simplemap_dff$16301 (SB_DFFE): \common.led_blink.led_on_count [16] = 0
FF init value for cell $auto$simplemap.cc:420:simplemap_dff$16302 (SB_DFFE): \common.led_blink.led_on_count [17] = 0
FF init value for cell $auto$simplemap.cc:420:simplemap_dff$16303 (SB_DFFE): \common.led_blink.led_on_count [18] = 0
FF init value for cell $auto$simplemap.cc:420:simplemap_dff$16304 (SB_DFFE): \common.led_blink.led_on_count [19] = 0
FF init value for cell $auto$simplemap.cc:420:simplemap_dff$16305 (SB_DFFE): \common.led_blink.led_on_count [20] = 0
FF init value for cell $auto$simplemap.cc:420:simplemap_dff$16306 (SB_DFFE): \common.led_blink.led_on_count [21] = 0
FF init value for cell $auto$simplemap.cc:420:simplemap_dff$16307 (SB_DFFE): \common.led_blink.led_on_count [22] = 0
FF init value for cell $auto$simplemap.cc:420:simplemap_dff$16308 (SB_DFFE): \common.led_blink.led_on_count [23] = 0
FF init value for cell $auto$simplemap.cc:420:simplemap_dff$16309 (SB_DFFE): \common.led_blink.led_on_count [24] = 0
FF init value for cell $auto$simplemap.cc:420:simplemap_dff$16310 (SB_DFFE): \common.led_blink.led_on_count [25] = 0
FF init value for cell $auto$simplemap.cc:420:simplemap_dff$16311 (SB_DFFE): \common.led_blink.led_on_count [26] = 0
FF init value for cell $auto$simplemap.cc:420:simplemap_dff$16312 (SB_DFFE): \common.led_blink.led_on_count [27] = 0
FF init value for cell $auto$simplemap.cc:420:simplemap_dff$16313 (SB_DFFE): \common.led_blink.led_on_count [28] = 0
FF init value for cell $auto$simplemap.cc:420:simplemap_dff$16314 (SB_DFFE): \common.led_blink.led_on_count [29] = 0
FF init value for cell $auto$simplemap.cc:420:simplemap_dff$16315 (SB_DFFE): \common.led_blink.led_on_count [30] = 0
FF init value for cell $auto$simplemap.cc:420:simplemap_dff$20068 (SB_DFF): \common.pb.spirx_lencalc.length [6] = 0
FF init value for cell $auto$simplemap.cc:420:simplemap_dff$17382 (SB_DFFE): \common.pb.rx_buf_overflow [0] = 0
FF init value for cell $auto$simplemap.cc:420:simplemap_dff$17383 (SB_DFFE): \common.pb.rx_buf_wr = 0
FF init value for cell $auto$simplemap.cc:420:simplemap_dff$17386 (SB_DFFE): \common.pb.rx_buf_wr_data [2] = 0
FF init value for cell $auto$simplemap.cc:420:simplemap_dff$17387 (SB_DFFE): \common.pb.rx_buf_wr_data [3] = 0
FF init value for cell $auto$simplemap.cc:420:simplemap_dff$17388 (SB_DFFE): \common.pb.rx_buf_wr_data [4] = 0
FF init value for cell $auto$simplemap.cc:420:simplemap_dff$17389 (SB_DFFE): \common.pb.rx_buf_wr_data [5] = 0
FF init value for cell $auto$simplemap.cc:420:simplemap_dff$17390 (SB_DFFE): \common.pb.rx_buf_wr_data [6] = 0
FF init value for cell $auto$simplemap.cc:420:simplemap_dff$17391 (SB_DFFE): \common.pb.rx_buf_wr_data [7] = 0
FF init value for cell $auto$simplemap.cc:420:simplemap_dff$17392 (SB_DFFE): \common.pb.rx_buf_wr_data [8] = 0
FF init value for cell $auto$simplemap.cc:420:simplemap_dff$17394 (SB_DFFE): \common.pb.rx_buf_wr_addr [1] = 0
FF init value for cell $auto$simplemap.cc:420:simplemap_dff$17384 (SB_DFFE): \common.pb.rx_buf_wr_data [0] = 0
FF init value for cell $auto$simplemap.cc:420:simplemap_dff$17395 (SB_DFFE): \common.pb.rx_buf_wr_addr [2] = 0
FF init value for cell $auto$simplemap.cc:420:simplemap_dff$17396 (SB_DFFE): \common.pb.rx_buf_wr_addr [3] = 0
FF init value for cell $auto$simplemap.cc:420:simplemap_dff$17397 (SB_DFFE): \common.pb.rx_buf_wr_addr [4] = 0
FF init value for cell $auto$simplemap.cc:420:simplemap_dff$17398 (SB_DFFE): \common.pb.rx_buf_wr_addr [5] = 0
FF init value for cell $auto$simplemap.cc:420:simplemap_dff$17399 (SB_DFFE): \common.pb.rx_buf_wr_addr [6] = 0
FF init value for cell $auto$simplemap.cc:420:simplemap_dff$17400 (SB_DFFE): \common.pb.rx_buf_wr_addr [7] = 0
FF init value for cell $auto$simplemap.cc:420:simplemap_dff$17402 (SB_DFFE): \common.pb.uart_tx_data [1] = 0
FF init value for cell $auto$simplemap.cc:420:simplemap_dff$17393 (SB_DFFE): \common.pb.rx_buf_wr_addr [0] = 0
FF init value for cell $auto$simplemap.cc:420:simplemap_dff$17403 (SB_DFFE): \common.pb.uart_tx_data [2] = 0
FF init value for cell $auto$simplemap.cc:420:simplemap_dff$17404 (SB_DFFE): \common.pb.uart_tx_data [3] = 0
FF init value for cell $auto$simplemap.cc:420:simplemap_dff$17405 (SB_DFFE): \common.pb.uart_tx_data [4] = 0
FF init value for cell $auto$simplemap.cc:420:simplemap_dff$17406 (SB_DFFE): \common.pb.uart_tx_data [5] = 0
FF init value for cell $auto$simplemap.cc:420:simplemap_dff$17407 (SB_DFFE): \common.pb.uart_tx_data [6] = 0
FF init value for cell $auto$simplemap.cc:420:simplemap_dff$17408 (SB_DFFE): \common.pb.uart_tx_data [7] = 0
FF init value for cell $auto$simplemap.cc:420:simplemap_dff$17410 (SB_DFFE): \common.pb.tx_buf_rd_addr [1] = 0
FF init value for cell $auto$simplemap.cc:420:simplemap_dff$17401 (SB_DFFE): \common.pb.uart_tx_data [0] = 0
FF init value for cell $auto$simplemap.cc:420:simplemap_dff$17411 (SB_DFFE): \common.pb.tx_buf_rd_addr [2] = 0
FF init value for cell $auto$simplemap.cc:420:simplemap_dff$17412 (SB_DFFE): \common.pb.tx_buf_rd_addr [3] = 0
FF init value for cell $auto$simplemap.cc:420:simplemap_dff$17413 (SB_DFFE): \common.pb.tx_buf_rd_addr [4] = 0
FF init value for cell $auto$simplemap.cc:420:simplemap_dff$17414 (SB_DFFE): \common.pb.tx_buf_rd_addr [5] = 0
FF init value for cell $auto$simplemap.cc:420:simplemap_dff$17415 (SB_DFFE): \common.pb.tx_buf_rd_addr [6] = 0
FF init value for cell $auto$simplemap.cc:420:simplemap_dff$17416 (SB_DFFE): \common.pb.tx_buf_rd_addr [7] = 0
FF init value for cell $auto$simplemap.cc:420:simplemap_dff$17419 (SB_DFFE): \common.pb.spitx_ctrl_reply_data [1] = 0
FF init value for cell $auto$simplemap.cc:420:simplemap_dff$17409 (SB_DFFE): \common.pb.tx_buf_rd_addr [0] = 0
FF init value for cell $auto$simplemap.cc:420:simplemap_dff$17417 (SB_DFFE): \common.pb.spitx_ctrl_pending = 0
FF init value for cell $auto$simplemap.cc:420:simplemap_dff$17420 (SB_DFFE): \common.pb.spitx_ctrl_reply_data [2] = 0
FF init value for cell $auto$simplemap.cc:420:simplemap_dff$17421 (SB_DFFE): \common.pb.spitx_ctrl_reply_data [3] = 0
FF init value for cell $auto$simplemap.cc:420:simplemap_dff$17422 (SB_DFFE): \common.pb.spitx_ctrl_reply_data [4] = 0
FF init value for cell $auto$simplemap.cc:420:simplemap_dff$17423 (SB_DFFE): \common.pb.spitx_ctrl_reply_data [5] = 0
FF init value for cell $auto$simplemap.cc:420:simplemap_dff$17424 (SB_DFFE): \common.pb.spitx_ctrl_reply_data [6] = 0
FF init value for cell $auto$simplemap.cc:420:simplemap_dff$17425 (SB_DFFE): \common.pb.spitx_ctrl_reply_data [7] = 0
FF init value for cell $auto$simplemap.cc:420:simplemap_dff$17426 (SB_DFFE): \common.pb.spitx_ctrl_reply_data [8] = 0
FF init value for cell $auto$simplemap.cc:420:simplemap_dff$17427 (SB_DFFE): \common.pb.spitx_ctrl_reply_data [9] = 0
FF init value for cell $auto$simplemap.cc:420:simplemap_dff$17428 (SB_DFFE): \common.pb.spitx_ctrl_reply_data [10] = 0
FF init value for cell $auto$simplemap.cc:420:simplemap_dff$17429 (SB_DFFE): \common.pb.spitx_ctrl_reply_data [11] = 0
FF init value for cell $auto$simplemap.cc:420:simplemap_dff$17430 (SB_DFFE): \common.pb.spitx_ctrl_reply_data [12] = 0
FF init value for cell $auto$simplemap.cc:420:simplemap_dff$17431 (SB_DFFE): \common.pb.spitx_ctrl_reply_data [13] = 0
FF init value for cell $auto$simplemap.cc:420:simplemap_dff$17432 (SB_DFFE): \common.pb.spitx_ctrl_reply_data [14] = 0
FF init value for cell $auto$simplemap.cc:420:simplemap_dff$17433 (SB_DFFE): \common.pb.spitx_ctrl_reply_data [15] = 0
FF init value for cell $auto$simplemap.cc:420:simplemap_dff$17434 (SB_DFFE): \common.pb.spitx_ctrl_reply_data [16] = 0
FF init value for cell $auto$simplemap.cc:420:simplemap_dff$17435 (SB_DFFE): \common.pb.spitx_ctrl_reply_data [17] = 0
FF init value for cell $auto$simplemap.cc:420:simplemap_dff$17436 (SB_DFFE): \common.pb.spitx_ctrl_reply_data [18] = 0
FF init value for cell $auto$simplemap.cc:420:simplemap_dff$17437 (SB_DFFE): \common.pb.spitx_ctrl_reply_data [19] = 0
FF init value for cell $auto$simplemap.cc:420:simplemap_dff$17438 (SB_DFFE): \common.pb.spitx_ctrl_reply_data [20] = 0
FF init value for cell $auto$simplemap.cc:420:simplemap_dff$17439 (SB_DFFE): \common.pb.spitx_ctrl_reply_data [21] = 0
FF init value for cell $auto$simplemap.cc:420:simplemap_dff$17440 (SB_DFFE): \common.pb.spitx_ctrl_reply_data [22] = 0
FF init value for cell $auto$simplemap.cc:420:simplemap_dff$17441 (SB_DFFE): \common.pb.spitx_ctrl_reply_data [23] = 0
FF init value for cell $auto$simplemap.cc:420:simplemap_dff$20916 (SB_DFFE): \common.pb.uart.rx_mod.rx_irq = 0
FF init value for cell $auto$simplemap.cc:420:simplemap_dff$17447 (SB_DFFE): \common.pb.spitx_ctrl_reply_data [29] = 0
FF init value for cell $auto$simplemap.cc:420:simplemap_dff$17444 (SB_DFFE): \common.pb.spitx_ctrl_reply_data [26] = 0
FF init value for cell $auto$simplemap.cc:420:simplemap_dff$17448 (SB_DFFE): \common.pb.spitx_ctrl_reply_data [30] = 0
FF init value for cell $auto$simplemap.cc:420:simplemap_dff$17449 (SB_DFFE): \common.pb.spitx_ctrl_reply_data [31] = 0
FF init value for cell $auto$simplemap.cc:420:simplemap_dff$17443 (SB_DFFE): \common.pb.spitx_ctrl_reply_data [25] = 0
FF init value for cell $auto$simplemap.cc:420:simplemap_dff$20484 (SB_DFF): \common.pb.uart.tx_trigger_req = 0
FF init value for cell $auto$simplemap.cc:420:simplemap_dff$17445 (SB_DFFE): \common.pb.spitx_ctrl_reply_data [27] = 0
FF init value for cell $auto$simplemap.cc:420:simplemap_dff$17418 (SB_DFFE): \common.pb.spitx_ctrl_reply_data [0] = 0
FF init value for cell $auto$simplemap.cc:420:simplemap_dff$17452 (SB_DFFE): \common.pb.spitx_ctrl_reply [2] = 0
FF init value for cell $auto$simplemap.cc:420:simplemap_dff$17453 (SB_DFFE): \common.pb.spitx_ctrl_reply [3] = 0
FF init value for cell $auto$simplemap.cc:420:simplemap_dff$17454 (SB_DFFE): \common.pb.spitx_ctrl_reply [4] = 0
FF init value for cell $auto$simplemap.cc:420:simplemap_dff$17455 (SB_DFFE): \common.pb.spitx_ctrl_reply [5] = 0
FF init value for cell $auto$simplemap.cc:420:simplemap_dff$20540 (SB_DFFE): \common.pb.uart.tx_mod.tx_active = 0
FF init value for cell $auto$simplemap.cc:420:simplemap_dff$17457 (SB_DFFE): \common.pb.spitx_ctrl_reply [7] = 0
FF init value for cell $auto$simplemap.cc:420:simplemap_dff$17460 (SB_DFFE): \common.pb.spirx_lencalc_byte [1] = 0
FF init value for cell $auto$simplemap.cc:420:simplemap_dff$17450 (SB_DFFE): \common.pb.spitx_ctrl_reply [0] = 0
FF init value for cell $auto$simplemap.cc:420:simplemap_dff$17458 (SB_DFFE): \common.pb.spirx_lencalc_new = 0
FF init value for cell $auto$simplemap.cc:420:simplemap_dff$17461 (SB_DFFE): \common.pb.spirx_lencalc_byte [2] = 0
FF init value for cell $auto$simplemap.cc:420:simplemap_dff$17462 (SB_DFFE): \common.pb.spirx_lencalc_byte [3] = 0
FF init value for cell $auto$simplemap.cc:420:simplemap_dff$17463 (SB_DFFE): \common.pb.spirx_lencalc_byte [4] = 0
FF init value for cell $auto$simplemap.cc:420:simplemap_dff$17464 (SB_DFFE): \common.pb.spirx_lencalc_byte [5] = 0
FF init value for cell $auto$simplemap.cc:420:simplemap_dff$17465 (SB_DFFE): \common.pb.spirx_lencalc_byte [6] = 0
FF init value for cell $auto$simplemap.cc:420:simplemap_dff$17466 (SB_DFFE): \common.pb.spirx_lencalc_byte [7] = 0
FF init value for cell $auto$simplemap.cc:420:simplemap_dff$17469 (SB_DFFE): \common.pb.spirx_ctrl_crcerr [1] = 0
FF init value for cell $auto$simplemap.cc:420:simplemap_dff$17459 (SB_DFFE): \common.pb.spirx_lencalc_byte [0] = 0
FF init value for cell $auto$simplemap.cc:420:simplemap_dff$17467 (SB_DFF): \common.pb.spirx_lencalc_n_reset = 0
FF init value for cell $auto$simplemap.cc:420:simplemap_dff$17471 (SB_DFFE): \common.pb.spirx_crc [1] = 0
FF init value for cell $auto$simplemap.cc:420:simplemap_dff$17468 (SB_DFFE): \common.pb.spirx_ctrl_crcerr [0] = 0
FF init value for cell $auto$simplemap.cc:420:simplemap_dff$17472 (SB_DFFE): \common.pb.spirx_crc [2] = 0
FF init value for cell $auto$simplemap.cc:420:simplemap_dff$17473 (SB_DFFE): \common.pb.spirx_crc [3] = 0
FF init value for cell $auto$simplemap.cc:420:simplemap_dff$17474 (SB_DFFE): \common.pb.spirx_crc [4] = 0
FF init value for cell $auto$simplemap.cc:420:simplemap_dff$17475 (SB_DFFE): \common.pb.spirx_crc [5] = 0
FF init value for cell $auto$simplemap.cc:420:simplemap_dff$17476 (SB_DFFE): \common.pb.spirx_crc [6] = 0
FF init value for cell $auto$simplemap.cc:420:simplemap_dff$17479 (SB_DFF): \common.pb.spirx_ctrl_data [1] = 0
FF init value for cell $auto$simplemap.cc:420:simplemap_dff$17470 (SB_DFFE): \common.pb.spirx_crc [0] = 0
FF init value for cell $auto$simplemap.cc:420:simplemap_dff$17480 (SB_DFF): \common.pb.spirx_ctrl_data [2] = 0
FF init value for cell $auto$simplemap.cc:420:simplemap_dff$17481 (SB_DFF): \common.pb.spirx_ctrl_data [3] = 0
FF init value for cell $auto$simplemap.cc:420:simplemap_dff$17482 (SB_DFF): \common.pb.spirx_ctrl_data [4] = 0
FF init value for cell $auto$simplemap.cc:420:simplemap_dff$17483 (SB_DFF): \common.pb.spirx_ctrl_data [5] = 0
FF init value for cell $auto$simplemap.cc:420:simplemap_dff$17484 (SB_DFF): \common.pb.spirx_ctrl_data [6] = 0
FF init value for cell $auto$simplemap.cc:420:simplemap_dff$17485 (SB_DFF): \common.pb.spirx_ctrl_data [7] = 0
FF init value for cell $auto$simplemap.cc:420:simplemap_dff$17486 (SB_DFF): \common.pb.spirx_ctrl_data [8] = 0
FF init value for cell $auto$simplemap.cc:420:simplemap_dff$17487 (SB_DFF): \common.pb.spirx_ctrl_data [9] = 0
FF init value for cell $auto$simplemap.cc:420:simplemap_dff$17488 (SB_DFF): \common.pb.spirx_ctrl_data [10] = 0
FF init value for cell $auto$simplemap.cc:420:simplemap_dff$17489 (SB_DFF): \common.pb.spirx_ctrl_data [11] = 0
FF init value for cell $auto$simplemap.cc:420:simplemap_dff$17490 (SB_DFF): \common.pb.spirx_ctrl_data [12] = 0
FF init value for cell $auto$simplemap.cc:420:simplemap_dff$17491 (SB_DFF): \common.pb.spirx_ctrl_data [13] = 0
FF init value for cell $auto$simplemap.cc:420:simplemap_dff$17492 (SB_DFF): \common.pb.spirx_ctrl_data [14] = 0
FF init value for cell $auto$simplemap.cc:420:simplemap_dff$17493 (SB_DFF): \common.pb.spirx_ctrl_data [15] = 0
FF init value for cell $auto$simplemap.cc:420:simplemap_dff$17494 (SB_DFF): \common.pb.spirx_ctrl_data [16] = 0
FF init value for cell $auto$simplemap.cc:420:simplemap_dff$17495 (SB_DFF): \common.pb.spirx_ctrl_data [17] = 0
FF init value for cell $auto$simplemap.cc:420:simplemap_dff$17496 (SB_DFF): \common.pb.spirx_ctrl_data [18] = 0
FF init value for cell $auto$simplemap.cc:420:simplemap_dff$17497 (SB_DFF): \common.pb.spirx_ctrl_data [19] = 0
FF init value for cell $auto$simplemap.cc:420:simplemap_dff$17498 (SB_DFF): \common.pb.spirx_ctrl_data [20] = 0
FF init value for cell $auto$simplemap.cc:420:simplemap_dff$17499 (SB_DFF): \common.pb.spirx_ctrl_data [21] = 0
FF init value for cell $auto$simplemap.cc:420:simplemap_dff$17500 (SB_DFF): \common.pb.spirx_ctrl_data [22] = 0
FF init value for cell $auto$simplemap.cc:420:simplemap_dff$17501 (SB_DFF): \common.pb.spirx_ctrl_data [23] = 0
FF init value for cell $auto$simplemap.cc:420:simplemap_dff$17511 (SB_DFF): \common.pb.spirx_ctrl [1] = 0
FF init value for cell $auto$simplemap.cc:420:simplemap_dff$17478 (SB_DFF): \common.pb.spirx_ctrl_data [0] = 0
FF init value for cell $auto$simplemap.cc:420:simplemap_dff$17512 (SB_DFF): \common.pb.spirx_ctrl [2] = 0
FF init value for cell $auto$simplemap.cc:420:simplemap_dff$17513 (SB_DFF): \common.pb.spirx_ctrl [3] = 0
FF init value for cell $auto$simplemap.cc:420:simplemap_dff$17514 (SB_DFF): \common.pb.spirx_ctrl [4] = 0
FF init value for cell $auto$simplemap.cc:420:simplemap_dff$17515 (SB_DFF): \common.pb.spirx_ctrl [5] = 0
FF init value for cell $auto$simplemap.cc:420:simplemap_dff$17516 (SB_DFF): \common.pb.spirx_ctrl [6] = 0
FF init value for cell $auto$simplemap.cc:420:simplemap_dff$17517 (SB_DFF): \common.pb.spirx_ctrl [7] = 0
FF init value for cell $auto$simplemap.cc:420:simplemap_dff$17519 (SB_DFFE): \common.pb.spirx_bytecount [1] = 0
FF init value for cell $auto$simplemap.cc:420:simplemap_dff$17510 (SB_DFF): \common.pb.spirx_ctrl [0] = 0
FF init value for cell $auto$simplemap.cc:420:simplemap_dff$17520 (SB_DFFE): \common.pb.spirx_bytecount [2] = 0
FF init value for cell $auto$simplemap.cc:420:simplemap_dff$17521 (SB_DFFE): \common.pb.spirx_bytecount [3] = 0
FF init value for cell $auto$simplemap.cc:420:simplemap_dff$17522 (SB_DFFE): \common.pb.spirx_bytecount [4] = 0
FF init value for cell $auto$simplemap.cc:420:simplemap_dff$17523 (SB_DFFE): \common.pb.spirx_bytecount [5] = 0
FF init value for cell $auto$simplemap.cc:420:simplemap_dff$17524 (SB_DFFE): \common.pb.spirx_bytecount [6] = 0
FF init value for cell $auto$simplemap.cc:420:simplemap_dff$17525 (SB_DFFE): \common.pb.spirx_bytecount [7] = 0
FF init value for cell $auto$simplemap.cc:420:simplemap_dff$17528 (SB_DFFE): \common.pb.spirx_len [1] = 0
FF init value for cell $auto$simplemap.cc:420:simplemap_dff$17518 (SB_DFFE): \common.pb.spirx_bytecount [0] = 0
FF init value for cell $auto$simplemap.cc:420:simplemap_dff$17526 (SB_DFFE): \common.pb.spirx_len_valid = 0
FF init value for cell $auto$simplemap.cc:420:simplemap_dff$17529 (SB_DFFE): \common.pb.spirx_len [2] = 0
FF init value for cell $auto$simplemap.cc:420:simplemap_dff$17530 (SB_DFFE): \common.pb.spirx_len [3] = 0
FF init value for cell $auto$simplemap.cc:420:simplemap_dff$17531 (SB_DFFE): \common.pb.spirx_len [4] = 0
FF init value for cell $auto$simplemap.cc:420:simplemap_dff$17532 (SB_DFFE): \common.pb.spirx_len [5] = 0
FF init value for cell $auto$simplemap.cc:420:simplemap_dff$17533 (SB_DFFE): \common.pb.spirx_len [6] = 0
FF init value for cell $auto$simplemap.cc:420:simplemap_dff$17534 (SB_DFFE): \common.pb.spirx_len [7] = 0
FF init value for cell $auto$simplemap.cc:420:simplemap_dff$17536 (SB_DFF): \common.pb.spirx_state [1] = 0
FF init value for cell $auto$simplemap.cc:420:simplemap_dff$17527 (SB_DFFE): \common.pb.spirx_len [0] = 0
FF init value for cell $auto$simplemap.cc:420:simplemap_dff$17537 (SB_DFF): \common.pb.spirx_state [2] = 0
FF init value for cell $auto$simplemap.cc:420:simplemap_dff$17539 (SB_DFFE): \common.pb.tsyn_clks [1] = 0
FF init value for cell $auto$simplemap.cc:420:simplemap_dff$17535 (SB_DFF): \common.pb.spirx_state [0] = 0
FF init value for cell $auto$simplemap.cc:420:simplemap_dff$17540 (SB_DFFE): \common.pb.tsyn_clks [2] = 0
FF init value for cell $auto$simplemap.cc:420:simplemap_dff$17541 (SB_DFFE): \common.pb.tsyn_clks [3] = 0
FF init value for cell $auto$simplemap.cc:420:simplemap_dff$17542 (SB_DFFE): \common.pb.tsyn_clks [4] = 0
FF init value for cell $auto$simplemap.cc:420:simplemap_dff$17543 (SB_DFFE): \common.pb.tsyn_clks [5] = 0
FF init value for cell $auto$simplemap.cc:420:simplemap_dff$17544 (SB_DFFE): \common.pb.tsyn_clks [6] = 0
FF init value for cell $auto$simplemap.cc:420:simplemap_dff$17545 (SB_DFFE): \common.pb.tsyn_clks [7] = 0
FF init value for cell $auto$simplemap.cc:420:simplemap_dff$17546 (SB_DFFE): \common.pb.tsyn_clks [8] = 0
FF init value for cell $auto$simplemap.cc:420:simplemap_dff$17547 (SB_DFFE): \common.pb.tsyn_clks [9] = 0
FF init value for cell $auto$simplemap.cc:420:simplemap_dff$17548 (SB_DFFE): \common.pb.tsyn_clks [10] = 0
FF init value for cell $auto$simplemap.cc:420:simplemap_dff$17549 (SB_DFFE): \common.pb.tsyn_clks [11] = 0
FF init value for cell $auto$simplemap.cc:420:simplemap_dff$17550 (SB_DFFE): \common.pb.tsyn_clks [12] = 0
FF init value for cell $auto$simplemap.cc:420:simplemap_dff$17551 (SB_DFFE): \common.pb.tsyn_clks [13] = 0
FF init value for cell $auto$simplemap.cc:420:simplemap_dff$17552 (SB_DFFE): \common.pb.tsyn_clks [14] = 0
FF init value for cell $auto$simplemap.cc:420:simplemap_dff$17553 (SB_DFFE): \common.pb.tsyn_clks [15] = 0
FF init value for cell $auto$simplemap.cc:420:simplemap_dff$17554 (SB_DFFE): \common.pb.tsyn_clks [16] = 0
FF init value for cell $auto$simplemap.cc:420:simplemap_dff$17555 (SB_DFFE): \common.pb.tsyn_clks [17] = 0
FF init value for cell $auto$simplemap.cc:420:simplemap_dff$17556 (SB_DFFE): \common.pb.tsyn_clks [18] = 0
FF init value for cell $auto$simplemap.cc:420:simplemap_dff$17557 (SB_DFFE): \common.pb.tsyn_clks [19] = 0
FF init value for cell $auto$simplemap.cc:420:simplemap_dff$17558 (SB_DFFE): \common.pb.tsyn_clks [20] = 0
FF init value for cell $auto$simplemap.cc:420:simplemap_dff$17559 (SB_DFFE): \common.pb.tsyn_clks [21] = 0
FF init value for cell $auto$simplemap.cc:420:simplemap_dff$17560 (SB_DFFE): \common.pb.tsyn_clks [22] = 0
FF init value for cell $auto$simplemap.cc:420:simplemap_dff$17561 (SB_DFFE): \common.pb.tsyn_clks [23] = 0
FF init value for cell $auto$simplemap.cc:420:simplemap_dff$17563 (SB_DFFE): \common.pb.uart_clks_per_sym [1] = 0
FF init value for cell $auto$simplemap.cc:420:simplemap_dff$17538 (SB_DFFE): \common.pb.tsyn_clks [0] = 0
FF init value for cell $auto$simplemap.cc:420:simplemap_dff$17564 (SB_DFFE): \common.pb.uart_clks_per_sym [2] = 0
FF init value for cell $auto$simplemap.cc:420:simplemap_dff$17565 (SB_DFFE): \common.pb.uart_clks_per_sym [3] = 0
FF init value for cell $auto$simplemap.cc:420:simplemap_dff$17566 (SB_DFFE): \common.pb.uart_clks_per_sym [4] = 0
FF init value for cell $auto$simplemap.cc:420:simplemap_dff$17567 (SB_DFFE): \common.pb.uart_clks_per_sym [5] = 0
FF init value for cell $auto$simplemap.cc:420:simplemap_dff$17568 (SB_DFFE): \common.pb.uart_clks_per_sym [6] = 0
FF init value for cell $auto$simplemap.cc:420:simplemap_dff$17569 (SB_DFFE): \common.pb.uart_clks_per_sym [7] = 0
FF init value for cell $auto$simplemap.cc:420:simplemap_dff$17570 (SB_DFFE): \common.pb.uart_clks_per_sym [8] = 0
FF init value for cell $auto$simplemap.cc:420:simplemap_dff$17571 (SB_DFFE): \common.pb.uart_clks_per_sym [9] = 0
FF init value for cell $auto$simplemap.cc:420:simplemap_dff$17572 (SB_DFFE): \common.pb.uart_clks_per_sym [10] = 0
FF init value for cell $auto$simplemap.cc:420:simplemap_dff$17573 (SB_DFFE): \common.pb.uart_clks_per_sym [11] = 0
FF init value for cell $auto$simplemap.cc:420:simplemap_dff$17574 (SB_DFFE): \common.pb.uart_clks_per_sym [12] = 0
FF init value for cell $auto$simplemap.cc:420:simplemap_dff$17575 (SB_DFFE): \common.pb.uart_clks_per_sym [13] = 0
FF init value for cell $auto$simplemap.cc:420:simplemap_dff$17576 (SB_DFFE): \common.pb.uart_clks_per_sym [14] = 0
FF init value for cell $auto$simplemap.cc:420:simplemap_dff$17577 (SB_DFFE): \common.pb.uart_clks_per_sym [15] = 0
FF init value for cell $auto$simplemap.cc:420:simplemap_dff$17578 (SB_DFFE): \common.pb.uart_clks_per_sym [16] = 0
FF init value for cell $auto$simplemap.cc:420:simplemap_dff$17579 (SB_DFFE): \common.pb.uart_clks_per_sym [17] = 0
FF init value for cell $auto$simplemap.cc:420:simplemap_dff$17580 (SB_DFFE): \common.pb.uart_clks_per_sym [18] = 0
FF init value for cell $auto$simplemap.cc:420:simplemap_dff$17581 (SB_DFFE): \common.pb.uart_clks_per_sym [19] = 0
FF init value for cell $auto$simplemap.cc:420:simplemap_dff$17582 (SB_DFFE): \common.pb.uart_clks_per_sym [20] = 0
FF init value for cell $auto$simplemap.cc:420:simplemap_dff$17583 (SB_DFFE): \common.pb.uart_clks_per_sym [21] = 0
FF init value for cell $auto$simplemap.cc:420:simplemap_dff$17584 (SB_DFFE): \common.pb.uart_clks_per_sym [22] = 0
FF init value for cell $auto$simplemap.cc:420:simplemap_dff$17585 (SB_DFFE): \common.pb.uart_clks_per_sym [23] = 0
FF init value for cell $auto$simplemap.cc:420:simplemap_dff$17588 (SB_DFFE): \common.pb.tx_buf_overflow [1] = 0
FF init value for cell $auto$simplemap.cc:420:simplemap_dff$17562 (SB_DFFE): \common.pb.uart_clks_per_sym [0] = 0
FF init value for cell $auto$simplemap.cc:420:simplemap_dff$17586 (SB_DFFE): \common.pb.rx_buf_overflow [1] = 0
FF init value for cell $auto$simplemap.cc:420:simplemap_dff$17591 (SB_DFF): \common.pb.tx_buf_wr_data [1] = 0
FF init value for cell $auto$simplemap.cc:420:simplemap_dff$17587 (SB_DFFE): \common.pb.tx_buf_overflow [0] = 0
FF init value for cell $auto$simplemap.cc:420:simplemap_dff$17589 (SB_DFF): \common.pb.tx_buf_wr = 0
FF init value for cell $auto$simplemap.cc:420:simplemap_dff$17592 (SB_DFF): \common.pb.tx_buf_wr_data [2] = 0
FF init value for cell $auto$simplemap.cc:420:simplemap_dff$17593 (SB_DFF): \common.pb.tx_buf_wr_data [3] = 0
FF init value for cell $auto$simplemap.cc:420:simplemap_dff$17594 (SB_DFF): \common.pb.tx_buf_wr_data [4] = 0
FF init value for cell $auto$simplemap.cc:420:simplemap_dff$17595 (SB_DFF): \common.pb.tx_buf_wr_data [5] = 0
FF init value for cell $auto$simplemap.cc:420:simplemap_dff$17596 (SB_DFF): \common.pb.tx_buf_wr_data [6] = 0
FF init value for cell $auto$simplemap.cc:420:simplemap_dff$17597 (SB_DFF): \common.pb.tx_buf_wr_data [7] = 0
FF init value for cell $auto$simplemap.cc:420:simplemap_dff$17599 (SB_DFF): \common.pb.tx_buf_wr_addr [1] = 0
FF init value for cell $auto$simplemap.cc:420:simplemap_dff$17590 (SB_DFF): \common.pb.tx_buf_wr_data [0] = 0
FF init value for cell $auto$simplemap.cc:420:simplemap_dff$17600 (SB_DFF): \common.pb.tx_buf_wr_addr [2] = 0
FF init value for cell $auto$simplemap.cc:420:simplemap_dff$17601 (SB_DFF): \common.pb.tx_buf_wr_addr [3] = 0
FF init value for cell $auto$simplemap.cc:420:simplemap_dff$17602 (SB_DFF): \common.pb.tx_buf_wr_addr [4] = 0
FF init value for cell $auto$simplemap.cc:420:simplemap_dff$17603 (SB_DFF): \common.pb.tx_buf_wr_addr [5] = 0
FF init value for cell $auto$simplemap.cc:420:simplemap_dff$17604 (SB_DFF): \common.pb.tx_buf_wr_addr [6] = 0
FF init value for cell $auto$simplemap.cc:420:simplemap_dff$17605 (SB_DFF): \common.pb.tx_buf_wr_addr [7] = 0
FF init value for cell $auto$simplemap.cc:420:simplemap_dff$17611 (SB_DFFE): \common.pb.spitx_crc [1] = 0
FF init value for cell $auto$simplemap.cc:420:simplemap_dff$17598 (SB_DFF): \common.pb.tx_buf_wr_addr [0] = 0
FF init value for cell $auto$simplemap.cc:420:simplemap_dff$17606 (SB_DFFE): \common.pb.softreset = 0
FF init value for cell $auto$simplemap.cc:420:simplemap_dff$17607 (SB_DFFE): \common.pb.softreset_status = 0
FF init value for cell $auto$simplemap.cc:420:simplemap_dff$17608 (SB_DFFE): \common.pb.n_hardreset_status = 0
FF init value for cell $auto$simplemap.cc:420:simplemap_dff$17609 (SB_DFFE): \common.pb.n_poweronreset_status = 0
FF init value for cell $auto$simplemap.cc:420:simplemap_dff$17612 (SB_DFFE): \common.pb.spitx_crc [2] = 0
FF init value for cell $auto$simplemap.cc:420:simplemap_dff$17613 (SB_DFFE): \common.pb.spitx_crc [3] = 0
FF init value for cell $auto$simplemap.cc:420:simplemap_dff$17614 (SB_DFFE): \common.pb.spitx_crc [4] = 0
FF init value for cell $auto$simplemap.cc:420:simplemap_dff$17617 (SB_DFFE): \common.pb.spitx_crc [7] = 0
FF init value for cell $auto$simplemap.cc:420:simplemap_dff$17626 (SB_DFFE): \common.pb.spitx_len [5] = 0
FF init value for cell $auto$simplemap.cc:420:simplemap_dff$17623 (SB_DFFE): \common.pb.spitx_len [2] = 0
FF init value for cell $auto$simplemap.cc:420:simplemap_dff$17616 (SB_DFFE): \common.pb.spitx_crc [6] = 0
FF init value for cell $auto$simplemap.cc:420:simplemap_dff$17610 (SB_DFFE): \common.pb.spitx_crc [0] = 0
FF init value for cell $auto$simplemap.cc:420:simplemap_dff$17618 (SB_DFFE): \common.pb.spitx_data_running = 0
FF init value for cell $auto$simplemap.cc:420:simplemap_dff$17619 (SB_DFFE): \common.pb.spitx_ctrl_running = 0
FF init value for cell $auto$simplemap.cc:420:simplemap_dff$17625 (SB_DFFE): \common.pb.spitx_len [4] = 0
FF init value for cell $auto$simplemap.cc:420:simplemap_dff$17624 (SB_DFFE): \common.pb.spitx_len [3] = 0
FF init value for cell $auto$simplemap.cc:420:simplemap_dff$17622 (SB_DFFE): \common.pb.spitx_len [1] = 0
FF init value for cell $auto$simplemap.cc:420:simplemap_dff$17630 (SB_DFFE): \common.pb.spitx_bytecount [1] = 0
FF init value for cell $auto$simplemap.cc:420:simplemap_dff$17632 (SB_DFFE): \common.pb.spitx_bytecount [3] = 0
FF init value for cell $auto$simplemap.cc:420:simplemap_dff$17628 (SB_DFFE): \common.pb.spitx_len [7] = 0
FF init value for cell $auto$simplemap.cc:420:simplemap_dff$17631 (SB_DFFE): \common.pb.spitx_bytecount [2] = 0
FF init value for cell $auto$simplemap.cc:420:simplemap_dff$17621 (SB_DFFE): \common.pb.spitx_len [0] = 0
FF init value for cell $auto$simplemap.cc:420:simplemap_dff$17627 (SB_DFFE): \common.pb.spitx_len [6] = 0
FF init value for cell $auto$simplemap.cc:420:simplemap_dff$21855 (SB_DFF): \common.pb.uart.tx_mod.symclk.count [1] = 0
FF init value for cell $auto$simplemap.cc:420:simplemap_dff$20476 (SB_DFFE): \common.pb.uart.tx_data_r [0] = 0
FF init value for cell $auto$simplemap.cc:420:simplemap_dff$17636 (SB_DFFE): \common.pb.spitx_bytecount [7] = 0
FF init value for cell $auto$simplemap.cc:420:simplemap_dff$17633 (SB_DFFE): \common.pb.spitx_bytecount [4] = 0
FF init value for cell $auto$simplemap.cc:420:simplemap_dff$17648 (SB_DFFE): \common.pb.rx_buf_rd_addr [2] = 0
FF init value for cell $auto$simplemap.cc:420:simplemap_dff$17639 (SB_DFFE): \common.pb.spi_tx_data [1] = 0
FF init value for cell $auto$simplemap.cc:420:simplemap_dff$17629 (SB_DFFE): \common.pb.spitx_bytecount [0] = 0
FF init value for cell $auto$simplemap.cc:420:simplemap_dff$17637 (SB_DFFE): \common.pb.spitx_ctrl_pending_ack = 0
FF init value for cell $auto$simplemap.cc:420:simplemap_dff$21859 (SB_DFF): \common.pb.uart.tx_mod.symclk.count [5] = 0
FF init value for cell $auto$simplemap.cc:420:simplemap_dff$20069 (SB_DFF): \common.pb.spirx_lencalc.length [7] = 0
FF init value for cell $auto$simplemap.cc:420:simplemap_dff$17642 (SB_DFFE): \common.pb.spi_tx_data [4] = 0
FF init value for cell $auto$simplemap.cc:420:simplemap_dff$17647 (SB_DFFE): \common.pb.rx_buf_rd_addr [1] = 0
FF init value for cell $auto$simplemap.cc:420:simplemap_dff$17644 (SB_DFFE): \common.pb.spi_tx_data [6] = 0
FF init value for cell $auto$simplemap.cc:420:simplemap_dff$17645 (SB_DFFE): \common.pb.spi_tx_data [7] = 0
FF init value for cell $auto$simplemap.cc:420:simplemap_dff$17635 (SB_DFFE): \common.pb.spitx_bytecount [6] = 0
FF init value for cell $auto$simplemap.cc:420:simplemap_dff$17638 (SB_DFFE): \common.pb.spi_tx_data [0] = 0
FF init value for cell $auto$simplemap.cc:420:simplemap_dff$17643 (SB_DFFE): \common.pb.spi_tx_data [5] = 0
FF init value for cell $auto$simplemap.cc:420:simplemap_dff$17649 (SB_DFFE): \common.pb.rx_buf_rd_addr [3] = 0
FF init value for cell $auto$simplemap.cc:420:simplemap_dff$17650 (SB_DFFE): \common.pb.rx_buf_rd_addr [4] = 0
FF init value for cell $auto$simplemap.cc:420:simplemap_dff$17651 (SB_DFFE): \common.pb.rx_buf_rd_addr [5] = 0
FF init value for cell $auto$simplemap.cc:420:simplemap_dff$17652 (SB_DFFE): \common.pb.rx_buf_rd_addr [6] = 0
FF init value for cell $auto$simplemap.cc:420:simplemap_dff$17653 (SB_DFFE): \common.pb.rx_buf_rd_addr [7] = 0
FF init value for cell $auto$simplemap.cc:420:simplemap_dff$17655 (SB_DFFE): \common.pb.timer_idle_saved [1] = 1
FF init value for cell $auto$simplemap.cc:420:simplemap_dff$17646 (SB_DFFE): \common.pb.rx_buf_rd_addr [0] = 0
FF init value for cell $auto$simplemap.cc:420:simplemap_dff$17656 (SB_DFFE): \common.pb.timer_idle_saved [2] = 1
FF init value for cell $auto$simplemap.cc:420:simplemap_dff$17657 (SB_DFFE): \common.pb.timer_idle_saved [3] = 1
FF init value for cell $auto$simplemap.cc:420:simplemap_dff$17658 (SB_DFFE): \common.pb.timer_idle_saved [4] = 1
FF init value for cell $auto$simplemap.cc:420:simplemap_dff$17659 (SB_DFFE): \common.pb.timer_idle_saved [5] = 1
FF init value for cell $auto$simplemap.cc:420:simplemap_dff$17660 (SB_DFFE): \common.pb.timer_idle_saved [6] = 1
FF init value for cell $auto$simplemap.cc:420:simplemap_dff$17661 (SB_DFFE): \common.pb.timer_idle_saved [7] = 1
FF init value for cell $auto$simplemap.cc:420:simplemap_dff$17662 (SB_DFFE): \common.pb.timer_idle_saved [8] = 1
FF init value for cell $auto$simplemap.cc:420:simplemap_dff$17663 (SB_DFFE): \common.pb.timer_idle_saved [9] = 1
FF init value for cell $auto$simplemap.cc:420:simplemap_dff$17664 (SB_DFFE): \common.pb.timer_idle_saved [10] = 1
FF init value for cell $auto$simplemap.cc:420:simplemap_dff$17665 (SB_DFFE): \common.pb.timer_idle_saved [11] = 1
FF init value for cell $auto$simplemap.cc:420:simplemap_dff$17666 (SB_DFFE): \common.pb.timer_idle_saved [12] = 1
FF init value for cell $auto$simplemap.cc:420:simplemap_dff$17667 (SB_DFFE): \common.pb.timer_idle_saved [13] = 1
FF init value for cell $auto$simplemap.cc:420:simplemap_dff$17668 (SB_DFFE): \common.pb.timer_idle_saved [14] = 1
FF init value for cell $auto$simplemap.cc:420:simplemap_dff$17669 (SB_DFFE): \common.pb.timer_idle_saved [15] = 1
FF init value for cell $auto$simplemap.cc:420:simplemap_dff$17670 (SB_DFFE): \common.pb.timer_idle_saved [16] = 1
FF init value for cell $auto$simplemap.cc:420:simplemap_dff$17671 (SB_DFFE): \common.pb.timer_idle_saved [17] = 1
FF init value for cell $auto$simplemap.cc:420:simplemap_dff$17672 (SB_DFFE): \common.pb.timer_idle_saved [18] = 1
FF init value for cell $auto$simplemap.cc:420:simplemap_dff$17673 (SB_DFFE): \common.pb.timer_idle_saved [19] = 1
FF init value for cell $auto$simplemap.cc:420:simplemap_dff$17674 (SB_DFFE): \common.pb.timer_idle_saved [20] = 1
FF init value for cell $auto$simplemap.cc:420:simplemap_dff$17675 (SB_DFFE): \common.pb.timer_idle_saved [21] = 1
FF init value for cell $auto$simplemap.cc:420:simplemap_dff$17676 (SB_DFFE): \common.pb.timer_idle_saved [22] = 1
FF init value for cell $auto$simplemap.cc:420:simplemap_dff$17677 (SB_DFFE): \common.pb.timer_idle_saved [23] = 1
FF init value for cell $auto$simplemap.cc:420:simplemap_dff$17679 (SB_DFFE): \common.pb.timer_idle [1] = 0
FF init value for cell $auto$simplemap.cc:420:simplemap_dff$17654 (SB_DFFE): \common.pb.timer_idle_saved [0] = 1
FF init value for cell $auto$simplemap.cc:420:simplemap_dff$17680 (SB_DFFE): \common.pb.timer_idle [2] = 0
FF init value for cell $auto$simplemap.cc:420:simplemap_dff$17681 (SB_DFFE): \common.pb.timer_idle [3] = 0
FF init value for cell $auto$simplemap.cc:420:simplemap_dff$17682 (SB_DFFE): \common.pb.timer_idle [4] = 0
FF init value for cell $auto$simplemap.cc:420:simplemap_dff$17683 (SB_DFFE): \common.pb.timer_idle [5] = 0
FF init value for cell $auto$simplemap.cc:420:simplemap_dff$17684 (SB_DFFE): \common.pb.timer_idle [6] = 0
FF init value for cell $auto$simplemap.cc:420:simplemap_dff$17685 (SB_DFFE): \common.pb.timer_idle [7] = 0
FF init value for cell $auto$simplemap.cc:420:simplemap_dff$17686 (SB_DFFE): \common.pb.timer_idle [8] = 0
FF init value for cell $auto$simplemap.cc:420:simplemap_dff$17687 (SB_DFFE): \common.pb.timer_idle [9] = 0
FF init value for cell $auto$simplemap.cc:420:simplemap_dff$17688 (SB_DFFE): \common.pb.timer_idle [10] = 0
FF init value for cell $auto$simplemap.cc:420:simplemap_dff$17689 (SB_DFFE): \common.pb.timer_idle [11] = 0
FF init value for cell $auto$simplemap.cc:420:simplemap_dff$17690 (SB_DFFE): \common.pb.timer_idle [12] = 0
FF init value for cell $auto$simplemap.cc:420:simplemap_dff$17691 (SB_DFFE): \common.pb.timer_idle [13] = 0
FF init value for cell $auto$simplemap.cc:420:simplemap_dff$17692 (SB_DFFE): \common.pb.timer_idle [14] = 0
FF init value for cell $auto$simplemap.cc:420:simplemap_dff$17693 (SB_DFFE): \common.pb.timer_idle [15] = 0
FF init value for cell $auto$simplemap.cc:420:simplemap_dff$17694 (SB_DFFE): \common.pb.timer_idle [16] = 0
FF init value for cell $auto$simplemap.cc:420:simplemap_dff$17695 (SB_DFFE): \common.pb.timer_idle [17] = 0
FF init value for cell $auto$simplemap.cc:420:simplemap_dff$17696 (SB_DFFE): \common.pb.timer_idle [18] = 0
FF init value for cell $auto$simplemap.cc:420:simplemap_dff$17697 (SB_DFFE): \common.pb.timer_idle [19] = 0
FF init value for cell $auto$simplemap.cc:420:simplemap_dff$17698 (SB_DFFE): \common.pb.timer_idle [20] = 0
FF init value for cell $auto$simplemap.cc:420:simplemap_dff$17699 (SB_DFFE): \common.pb.timer_idle [21] = 0
FF init value for cell $auto$simplemap.cc:420:simplemap_dff$17700 (SB_DFFE): \common.pb.timer_idle [22] = 0
FF init value for cell $auto$simplemap.cc:420:simplemap_dff$17701 (SB_DFFE): \common.pb.timer_idle [23] = 0
FF init value for cell $auto$simplemap.cc:420:simplemap_dff$21861 (SB_DFF): \common.pb.uart.tx_mod.symclk.count [7] = 0
FF init value for cell $auto$simplemap.cc:420:simplemap_dff$17678 (SB_DFFE): \common.pb.timer_idle [0] = 0
FF init value for cell $auto$simplemap.cc:420:simplemap_dff$20539 (SB_DFFE): \common.pb.uart.tx_mod.symclk_n_reset = 0
FF init value for cell $auto$simplemap.cc:420:simplemap_dff$20071 (SB_DFF): \common.pb.spirx_lencalc.state [1] = 0
FF init value for cell $auto$simplemap.cc:420:simplemap_dff$20063 (SB_DFF): \common.pb.spirx_lencalc.length [1] = 0
FF init value for cell $auto$simplemap.cc:420:simplemap_dff$20064 (SB_DFF): \common.pb.spirx_lencalc.length [2] = 0
FF init value for cell $auto$simplemap.cc:420:simplemap_dff$20065 (SB_DFF): \common.pb.spirx_lencalc.length [3] = 0
FF init value for cell $auto$simplemap.cc:420:simplemap_dff$20066 (SB_DFF): \common.pb.spirx_lencalc.length [4] = 0
FF init value for cell $auto$simplemap.cc:420:simplemap_dff$20067 (SB_DFF): \common.pb.spirx_lencalc.length [5] = 0
FF init value for cell $auto$simplemap.cc:420:simplemap_dff$21863 (SB_DFF): \common.pb.uart.tx_mod.symclk.count [9] = 0
FF init value for cell $auto$simplemap.cc:420:simplemap_dff$20062 (SB_DFF): \common.pb.spirx_lencalc.length [0] = 0
FF init value for cell $auto$simplemap.cc:420:simplemap_dff$20073 (SB_DFF): \common.pb.spirx_lencalc.byte_le [1] = 0
FF init value for cell $auto$simplemap.cc:420:simplemap_dff$20070 (SB_DFF): \common.pb.spirx_lencalc.state [0] = 0
FF init value for cell $auto$simplemap.cc:420:simplemap_dff$20074 (SB_DFF): \common.pb.spirx_lencalc.byte_le [2] = 0
FF init value for cell $auto$simplemap.cc:420:simplemap_dff$20075 (SB_DFF): \common.pb.spirx_lencalc.byte_le [3] = 0
FF init value for cell $auto$simplemap.cc:420:simplemap_dff$20076 (SB_DFF): \common.pb.spirx_lencalc.byte_le [4] = 0
FF init value for cell $auto$simplemap.cc:420:simplemap_dff$20077 (SB_DFF): \common.pb.spirx_lencalc.byte_le [5] = 0
FF init value for cell $auto$simplemap.cc:420:simplemap_dff$20078 (SB_DFF): \common.pb.spirx_lencalc.byte_le [6] = 0
FF init value for cell $auto$simplemap.cc:420:simplemap_dff$20079 (SB_DFF): \common.pb.spirx_lencalc.byte_le [7] = 0
FF init value for cell $auto$simplemap.cc:420:simplemap_dff$20358 (SB_DFFE): \common.pb.spi.bit_count [1] = 0
FF init value for cell $auto$simplemap.cc:420:simplemap_dff$20072 (SB_DFF): \common.pb.spirx_lencalc.byte_le [0] = 0
FF init value for cell $auto$simplemap.cc:420:simplemap_dff$20080 (SB_DFF): \common.pb.spirx_lencalc.error = 0
FF init value for cell $auto$simplemap.cc:420:simplemap_dff$20081 (SB_DFF): \common.pb.spirx_lencalc.length_valid = 0
FF init value for cell $auto$simplemap.cc:420:simplemap_dff$20356 (SB_DFF): \common.pb.spi.rx_irq_r = 0
FF init value for cell $auto$simplemap.cc:420:simplemap_dff$20359 (SB_DFFE): \common.pb.spi.bit_count [2] = 0
FF init value for cell $auto$simplemap.cc:420:simplemap_dff$20360 (SB_DFFE): \common.pb.spi.bit_count [3] = 0
FF init value for cell $auto$simplemap.cc:420:simplemap_dff$20361 (SB_DFFE): \common.pb.spi.bit_count [4] = 0
FF init value for cell $auto$simplemap.cc:420:simplemap_dff$20362 (SB_DFFE): \common.pb.spi.bit_count [5] = 0
FF init value for cell $auto$simplemap.cc:420:simplemap_dff$20364 (SB_DFFE): \common.pb.spi.tx_shiftreg [1] = 0
FF init value for cell $auto$simplemap.cc:420:simplemap_dff$20357 (SB_DFFE): \common.pb.spi.bit_count [0] = 0
FF init value for cell $auto$simplemap.cc:420:simplemap_dff$20365 (SB_DFFE): \common.pb.spi.tx_shiftreg [2] = 0
FF init value for cell $auto$simplemap.cc:420:simplemap_dff$20366 (SB_DFFE): \common.pb.spi.tx_shiftreg [3] = 0
FF init value for cell $auto$simplemap.cc:420:simplemap_dff$20367 (SB_DFFE): \common.pb.spi.tx_shiftreg [4] = 0
FF init value for cell $auto$simplemap.cc:420:simplemap_dff$20368 (SB_DFFE): \common.pb.spi.tx_shiftreg [5] = 0
FF init value for cell $auto$simplemap.cc:420:simplemap_dff$20369 (SB_DFFE): \common.pb.spi.tx_shiftreg [6] = 0
FF init value for cell $auto$simplemap.cc:420:simplemap_dff$20370 (SB_DFFE): \common.pb.spi.tx_shiftreg [7] = 0
FF init value for cell $auto$simplemap.cc:420:simplemap_dff$20372 (SB_DFFE): \common.pb.spi.rx_shiftreg [1] = 0
FF init value for cell $auto$simplemap.cc:420:simplemap_dff$20363 (SB_DFFE): \common.pb.spi.tx_shiftreg [0] = 0
FF init value for cell $auto$simplemap.cc:420:simplemap_dff$20373 (SB_DFFE): \common.pb.spi.rx_shiftreg [2] = 0
FF init value for cell $auto$simplemap.cc:420:simplemap_dff$20374 (SB_DFFE): \common.pb.spi.rx_shiftreg [3] = 0
FF init value for cell $auto$simplemap.cc:420:simplemap_dff$20375 (SB_DFFE): \common.pb.spi.rx_shiftreg [4] = 0
FF init value for cell $auto$simplemap.cc:420:simplemap_dff$20376 (SB_DFFE): \common.pb.spi.rx_shiftreg [5] = 0
FF init value for cell $auto$simplemap.cc:420:simplemap_dff$20377 (SB_DFFE): \common.pb.spi.rx_shiftreg [6] = 0
FF init value for cell $auto$simplemap.cc:420:simplemap_dff$20378 (SB_DFFE): \common.pb.spi.rx_shiftreg [7] = 0
FF init value for cell $auto$simplemap.cc:420:simplemap_dff$20380 (SB_DFFE): \common.pb.spi.rx_data_r [1] = 0
FF init value for cell $auto$simplemap.cc:420:simplemap_dff$20371 (SB_DFFE): \common.pb.spi.rx_shiftreg [0] = 0
FF init value for cell $auto$simplemap.cc:420:simplemap_dff$20381 (SB_DFFE): \common.pb.spi.rx_data_r [2] = 0
FF init value for cell $auto$simplemap.cc:420:simplemap_dff$20382 (SB_DFFE): \common.pb.spi.rx_data_r [3] = 0
FF init value for cell $auto$simplemap.cc:420:simplemap_dff$20383 (SB_DFFE): \common.pb.spi.rx_data_r [4] = 0
FF init value for cell $auto$simplemap.cc:420:simplemap_dff$20384 (SB_DFFE): \common.pb.spi.rx_data_r [5] = 0
FF init value for cell $auto$simplemap.cc:420:simplemap_dff$20385 (SB_DFFE): \common.pb.spi.rx_data_r [6] = 0
FF init value for cell $auto$simplemap.cc:420:simplemap_dff$20386 (SB_DFFE): \common.pb.spi.rx_data_r [7] = 0
FF init value for cell $auto$simplemap.cc:420:simplemap_dff$20477 (SB_DFFE): \common.pb.uart.tx_data_r [1] = 0
FF init value for cell $auto$simplemap.cc:420:simplemap_dff$20379 (SB_DFFE): \common.pb.spi.rx_data_r [0] = 0
FF init value for cell $auto$simplemap.cc:420:simplemap_dff$20387 (SB_DFFE): \common.pb.spi.miso_r = 0
FF init value for cell $auto$simplemap.cc:420:simplemap_dff$20478 (SB_DFFE): \common.pb.uart.tx_data_r [2] = 0
FF init value for cell $auto$simplemap.cc:420:simplemap_dff$20479 (SB_DFFE): \common.pb.uart.tx_data_r [3] = 0
FF init value for cell $auto$simplemap.cc:420:simplemap_dff$20480 (SB_DFFE): \common.pb.uart.tx_data_r [4] = 0
FF init value for cell $auto$simplemap.cc:420:simplemap_dff$20481 (SB_DFFE): \common.pb.uart.tx_data_r [5] = 0
FF init value for cell $auto$simplemap.cc:420:simplemap_dff$20482 (SB_DFFE): \common.pb.uart.tx_data_r [6] = 0
FF init value for cell $auto$simplemap.cc:420:simplemap_dff$20483 (SB_DFFE): \common.pb.uart.tx_data_r [7] = 0
FF init value for cell $auto$simplemap.cc:420:simplemap_dff$20520 (SB_DFF): \common.pb.spi.sync_ss.shiftreg [1] = 0
FF init value for cell $auto$simplemap.cc:420:simplemap_dff$17615 (SB_DFFE): \common.pb.spitx_crc [5] = 0
FF init value for cell $auto$simplemap.cc:420:simplemap_dff$20523 (SB_DFF): \common.pb.spi.sync_sck.shiftreg [2] = 0
FF init value for cell $auto$simplemap.cc:420:simplemap_dff$20519 (SB_DFF): \common.pb.spi.sync_ss.shiftreg [0] = 0
FF init value for cell $auto$simplemap.cc:420:simplemap_dff$20528 (SB_DFF): \common.pb.spi.sync_mosi.shiftreg [1] = 0
FF init value for cell $auto$simplemap.cc:420:simplemap_dff$20521 (SB_DFF): \common.pb.spi.sync_sck.shiftreg [0] = 0
FF init value for cell $auto$simplemap.cc:420:simplemap_dff$20522 (SB_DFF): \common.pb.spi.sync_sck.shiftreg [1] = 0
FF init value for cell $auto$simplemap.cc:420:simplemap_dff$20527 (SB_DFF): \common.pb.spi.sync_mosi.shiftreg [0] = 0
FF init value for cell $auto$simplemap.cc:420:simplemap_dff$17640 (SB_DFFE): \common.pb.spi_tx_data [2] = 0
FF init value for cell $auto$simplemap.cc:420:simplemap_dff$17456 (SB_DFFE): \common.pb.spitx_ctrl_reply [6] = 0
FF init value for cell $auto$simplemap.cc:420:simplemap_dff$17451 (SB_DFFE): \common.pb.spitx_ctrl_reply [1] = 0
FF init value for cell $auto$simplemap.cc:420:simplemap_dff$17477 (SB_DFFE): \common.pb.spirx_crc [7] = 0
FF init value for cell $auto$simplemap.cc:420:simplemap_dff$20549 (SB_DFFE): \common.pb.uart.tx_mod.tx_r = 1
FF init value for cell $auto$simplemap.cc:420:simplemap_dff$20550 (SB_DFFE): \common.pb.uart.tx_mod.tx_irq = 0
FF init value for cell $auto$simplemap.cc:420:simplemap_dff$20915 (SB_DFF): \common.pb.uart.sync_rx.shiftreg [1] = 0
FF init value for cell $auto$simplemap.cc:420:simplemap_dff$20945 (SB_DFFE): \common.pb.uart.rx_mod.rx_buf [1] = 0
FF init value for cell $auto$simplemap.cc:420:simplemap_dff$20914 (SB_DFF): \common.pb.uart.sync_rx.shiftreg [0] = 0
FF init value for cell $auto$simplemap.cc:420:simplemap_dff$17446 (SB_DFFE): \common.pb.spitx_ctrl_reply_data [28] = 0
FF init value for cell $auto$simplemap.cc:420:simplemap_dff$17385 (SB_DFFE): \common.pb.rx_buf_wr_data [1] = 0
FF init value for cell $auto$simplemap.cc:420:simplemap_dff$20941 (SB_DFFE): \common.pb.uart.rx_mod.symclk_n_reset = 0
FF init value for cell $auto$simplemap.cc:420:simplemap_dff$20942 (SB_DFFE): \common.pb.uart.rx_mod.rx_frame_error_start = 0
FF init value for cell $auto$simplemap.cc:420:simplemap_dff$20943 (SB_DFFE): \common.pb.uart.rx_mod.rx_parity_buf = 0
FF init value for cell $auto$simplemap.cc:420:simplemap_dff$20946 (SB_DFFE): \common.pb.uart.rx_mod.rx_buf [2] = 0
FF init value for cell $auto$simplemap.cc:420:simplemap_dff$20947 (SB_DFFE): \common.pb.uart.rx_mod.rx_buf [3] = 0
FF init value for cell $auto$simplemap.cc:420:simplemap_dff$20948 (SB_DFFE): \common.pb.uart.rx_mod.rx_buf [4] = 0
FF init value for cell $auto$simplemap.cc:420:simplemap_dff$20949 (SB_DFFE): \common.pb.uart.rx_mod.rx_buf [5] = 0
FF init value for cell $auto$simplemap.cc:420:simplemap_dff$20950 (SB_DFFE): \common.pb.uart.rx_mod.rx_buf [6] = 0
FF init value for cell $auto$simplemap.cc:420:simplemap_dff$20951 (SB_DFFE): \common.pb.uart.rx_mod.rx_buf [7] = 0
FF init value for cell $auto$simplemap.cc:420:simplemap_dff$20953 (SB_DFFE): \common.pb.uart.rx_mod.sym_count [1] = 0
FF init value for cell $auto$simplemap.cc:420:simplemap_dff$20944 (SB_DFFE): \common.pb.uart.rx_mod.rx_buf [0] = 0
FF init value for cell $auto$simplemap.cc:420:simplemap_dff$20954 (SB_DFFE): \common.pb.uart.rx_mod.sym_count [2] = 0
FF init value for cell $auto$simplemap.cc:420:simplemap_dff$20955 (SB_DFFE): \common.pb.uart.rx_mod.sym_count [3] = 0
FF init value for cell $auto$simplemap.cc:420:simplemap_dff$20957 (SB_DFFE): \common.pb.uart.rx_mod.rx_data [1] = 0
FF init value for cell $auto$simplemap.cc:420:simplemap_dff$20952 (SB_DFFE): \common.pb.uart.rx_mod.sym_count [0] = 0
FF init value for cell $auto$simplemap.cc:420:simplemap_dff$20958 (SB_DFFE): \common.pb.uart.rx_mod.rx_data [2] = 0
FF init value for cell $auto$simplemap.cc:420:simplemap_dff$20959 (SB_DFFE): \common.pb.uart.rx_mod.rx_data [3] = 0
FF init value for cell $auto$simplemap.cc:420:simplemap_dff$20960 (SB_DFFE): \common.pb.uart.rx_mod.rx_data [4] = 0
FF init value for cell $auto$simplemap.cc:420:simplemap_dff$20961 (SB_DFFE): \common.pb.uart.rx_mod.rx_data [5] = 0
FF init value for cell $auto$simplemap.cc:420:simplemap_dff$20962 (SB_DFFE): \common.pb.uart.rx_mod.rx_data [6] = 0
FF init value for cell $auto$simplemap.cc:420:simplemap_dff$20963 (SB_DFFE): \common.pb.uart.rx_mod.rx_data [7] = 0
FF init value for cell $auto$simplemap.cc:420:simplemap_dff$16285 (SB_DFFE): \common.led_blink.led_on_count [0] = 0
FF init value for cell $auto$simplemap.cc:420:simplemap_dff$20956 (SB_DFFE): \common.pb.uart.rx_mod.rx_data [0] = 0
FF init value for cell $auto$simplemap.cc:420:simplemap_dff$20964 (SB_DFFE): \common.pb.uart.rx_mod.rx_frame_error = 0
FF init value for cell $auto$simplemap.cc:420:simplemap_dff$20965 (SB_DFFE): \common.pb.uart.rx_mod.rx_parity_ok = 0
FF init value for cell $auto$simplemap.cc:420:simplemap_dff$20966 (SB_DFFE): \common.pb.uart.rx_mod.rx_active = 0
FF init value for cell $auto$simplemap.cc:420:simplemap_dff$21853 (SB_DFF): \common.pb.uart.tx_mod.symclk.setup = 0
FF init value for cell $auto$simplemap.cc:420:simplemap_dff$21856 (SB_DFF): \common.pb.uart.tx_mod.symclk.count [2] = 0
FF init value for cell $auto$simplemap.cc:420:simplemap_dff$21857 (SB_DFF): \common.pb.uart.tx_mod.symclk.count [3] = 0
FF init value for cell $auto$simplemap.cc:420:simplemap_dff$21858 (SB_DFF): \common.pb.uart.tx_mod.symclk.count [4] = 0
FF init value for cell $auto$simplemap.cc:420:simplemap_dff$17634 (SB_DFFE): \common.pb.spitx_bytecount [5] = 0
FF init value for cell $auto$simplemap.cc:420:simplemap_dff$16316 (SB_DFFE): \common.led_blink.led_on_count [31] = 0
FF init value for cell $auto$simplemap.cc:420:simplemap_dff$17641 (SB_DFFE): \common.pb.spi_tx_data [3] = 0
FF init value for cell $auto$simplemap.cc:420:simplemap_dff$21862 (SB_DFF): \common.pb.uart.tx_mod.symclk.count [8] = 0
FF init value for cell $auto$simplemap.cc:420:simplemap_dff$17442 (SB_DFFE): \common.pb.spitx_ctrl_reply_data [24] = 0
FF init value for cell $auto$simplemap.cc:420:simplemap_dff$21864 (SB_DFF): \common.pb.uart.tx_mod.symclk.count [10] = 0
FF init value for cell $auto$simplemap.cc:420:simplemap_dff$21865 (SB_DFF): \common.pb.uart.tx_mod.symclk.count [11] = 0
FF init value for cell $auto$simplemap.cc:420:simplemap_dff$21866 (SB_DFF): \common.pb.uart.tx_mod.symclk.count [12] = 0
FF init value for cell $auto$simplemap.cc:420:simplemap_dff$21867 (SB_DFF): \common.pb.uart.tx_mod.symclk.count [13] = 0
FF init value for cell $auto$simplemap.cc:420:simplemap_dff$21868 (SB_DFF): \common.pb.uart.tx_mod.symclk.count [14] = 0
FF init value for cell $auto$simplemap.cc:420:simplemap_dff$21869 (SB_DFF): \common.pb.uart.tx_mod.symclk.count [15] = 0
FF init value for cell $auto$simplemap.cc:420:simplemap_dff$21870 (SB_DFF): \common.pb.uart.tx_mod.symclk.count [16] = 0
FF init value for cell $auto$simplemap.cc:420:simplemap_dff$21871 (SB_DFF): \common.pb.uart.tx_mod.symclk.count [17] = 0
FF init value for cell $auto$simplemap.cc:420:simplemap_dff$21872 (SB_DFF): \common.pb.uart.tx_mod.symclk.count [18] = 0
FF init value for cell $auto$simplemap.cc:420:simplemap_dff$21873 (SB_DFF): \common.pb.uart.tx_mod.symclk.count [19] = 0
FF init value for cell $auto$simplemap.cc:420:simplemap_dff$21874 (SB_DFF): \common.pb.uart.tx_mod.symclk.count [20] = 0
FF init value for cell $auto$simplemap.cc:420:simplemap_dff$21875 (SB_DFF): \common.pb.uart.tx_mod.symclk.count [21] = 0
FF init value for cell $auto$simplemap.cc:420:simplemap_dff$21876 (SB_DFF): \common.pb.uart.tx_mod.symclk.count [22] = 0
FF init value for cell $auto$simplemap.cc:420:simplemap_dff$21877 (SB_DFF): \common.pb.uart.tx_mod.symclk.count [23] = 0
FF init value for cell $auto$simplemap.cc:420:simplemap_dff$22061 (SB_DFF): \common.pb.uart.rx_mod.symclk.count [1] = 0
FF init value for cell $auto$simplemap.cc:420:simplemap_dff$21854 (SB_DFF): \common.pb.uart.tx_mod.symclk.count [0] = 0
FF init value for cell $auto$simplemap.cc:420:simplemap_dff$21878 (SB_DFF): \common.pb.uart.tx_mod.symclk.symend = 0
FF init value for cell $auto$simplemap.cc:420:simplemap_dff$22059 (SB_DFF): \common.pb.uart.rx_mod.symclk.sample = 0
FF init value for cell $auto$simplemap.cc:420:simplemap_dff$22062 (SB_DFF): \common.pb.uart.rx_mod.symclk.count [2] = 0
FF init value for cell $auto$simplemap.cc:420:simplemap_dff$22063 (SB_DFF): \common.pb.uart.rx_mod.symclk.count [3] = 0
FF init value for cell $auto$simplemap.cc:420:simplemap_dff$22064 (SB_DFF): \common.pb.uart.rx_mod.symclk.count [4] = 0
FF init value for cell $auto$simplemap.cc:420:simplemap_dff$22065 (SB_DFF): \common.pb.uart.rx_mod.symclk.count [5] = 0
FF init value for cell $auto$simplemap.cc:420:simplemap_dff$22066 (SB_DFF): \common.pb.uart.rx_mod.symclk.count [6] = 0
FF init value for cell $auto$simplemap.cc:420:simplemap_dff$22067 (SB_DFF): \common.pb.uart.rx_mod.symclk.count [7] = 0
FF init value for cell $auto$simplemap.cc:420:simplemap_dff$22068 (SB_DFF): \common.pb.uart.rx_mod.symclk.count [8] = 0
FF init value for cell $auto$simplemap.cc:420:simplemap_dff$22069 (SB_DFF): \common.pb.uart.rx_mod.symclk.count [9] = 0
FF init value for cell $auto$simplemap.cc:420:simplemap_dff$22070 (SB_DFF): \common.pb.uart.rx_mod.symclk.count [10] = 0
FF init value for cell $auto$simplemap.cc:420:simplemap_dff$22071 (SB_DFF): \common.pb.uart.rx_mod.symclk.count [11] = 0
FF init value for cell $auto$simplemap.cc:420:simplemap_dff$22072 (SB_DFF): \common.pb.uart.rx_mod.symclk.count [12] = 0
FF init value for cell $auto$simplemap.cc:420:simplemap_dff$22073 (SB_DFF): \common.pb.uart.rx_mod.symclk.count [13] = 0
FF init value for cell $auto$simplemap.cc:420:simplemap_dff$22074 (SB_DFF): \common.pb.uart.rx_mod.symclk.count [14] = 0
FF init value for cell $auto$simplemap.cc:420:simplemap_dff$22075 (SB_DFF): \common.pb.uart.rx_mod.symclk.count [15] = 0
FF init value for cell $auto$simplemap.cc:420:simplemap_dff$22076 (SB_DFF): \common.pb.uart.rx_mod.symclk.count [16] = 0
FF init value for cell $auto$simplemap.cc:420:simplemap_dff$22077 (SB_DFF): \common.pb.uart.rx_mod.symclk.count [17] = 0
FF init value for cell $auto$simplemap.cc:420:simplemap_dff$22078 (SB_DFF): \common.pb.uart.rx_mod.symclk.count [18] = 0
FF init value for cell $auto$simplemap.cc:420:simplemap_dff$22079 (SB_DFF): \common.pb.uart.rx_mod.symclk.count [19] = 0
FF init value for cell $auto$simplemap.cc:420:simplemap_dff$22080 (SB_DFF): \common.pb.uart.rx_mod.symclk.count [20] = 0
FF init value for cell $auto$simplemap.cc:420:simplemap_dff$22081 (SB_DFF): \common.pb.uart.rx_mod.symclk.count [21] = 0
FF init value for cell $auto$simplemap.cc:420:simplemap_dff$22082 (SB_DFF): \common.pb.uart.rx_mod.symclk.count [22] = 0
FF init value for cell $auto$simplemap.cc:420:simplemap_dff$22083 (SB_DFF): \common.pb.uart.rx_mod.symclk.count [23] = 0
FF init value for cell $auto$simplemap.cc:420:simplemap_dff$17702 (SB_DFF): \common.pb.timer_idle_active = 0
FF init value for cell $auto$simplemap.cc:420:simplemap_dff$22060 (SB_DFF): \common.pb.uart.rx_mod.symclk.count [0] = 0
FF init value for cell $auto$simplemap.cc:420:simplemap_dff$22084 (SB_DFF): \common.pb.uart.rx_mod.symclk.symend = 0

2.38. Executing ICE40_FFSSR pass (merge synchronous set/reset into FF cells).
Merging set/reset $_MUX_ cells into SB_FFs in top_module.
  Merging $auto$simplemap.cc:277:simplemap_mux$16317 (A=1'0, B=$techmap\common.led_blink.$procmux$9288_Y, S=\common.pb.n_reset) into $auto$simplemap.cc:420:simplemap_dff$16251 (SB_DFF).
  Merging $auto$simplemap.cc:277:simplemap_mux$17835 (A=1'0, B=$techmap\common.pb.$procmux$14662_Y, S=$techmap\common.pb.$and$profibus_phy_mod.v:1047$6261_Y) into $auto$simplemap.cc:420:simplemap_dff$16252 (SB_DFF).
  Merging $auto$simplemap.cc:277:simplemap_mux$20923 (A=1'0, B=$techmap\common.pb.uart.tx_mod.symclk.$procmux$15655_Y [6], S=\common.pb.uart.tx_mod.symclk_n_reset) into $auto$simplemap.cc:420:simplemap_dff$21860 (SB_DFF).
  Merging $auto$simplemap.cc:277:simplemap_mux$16482 (A=1'0, B=$techmap\common.led_blink.$procmux$9260_Y [1], S=\common.pb.n_reset) into $auto$simplemap.cc:420:simplemap_dff$16254 (SB_DFFE).
  Merging $auto$simplemap.cc:277:simplemap_mux$16483 (A=1'0, B=$techmap\common.led_blink.$procmux$9260_Y [2], S=\common.pb.n_reset) into $auto$simplemap.cc:420:simplemap_dff$16255 (SB_DFFE).
  Merging $auto$simplemap.cc:277:simplemap_mux$16484 (A=1'0, B=$techmap\common.led_blink.$procmux$9260_Y [3], S=\common.pb.n_reset) into $auto$simplemap.cc:420:simplemap_dff$16256 (SB_DFFE).
  Merging $auto$simplemap.cc:277:simplemap_mux$16485 (A=1'0, B=$techmap\common.led_blink.$procmux$9260_Y [4], S=\common.pb.n_reset) into $auto$simplemap.cc:420:simplemap_dff$16257 (SB_DFFE).
  Merging $auto$simplemap.cc:277:simplemap_mux$16486 (A=1'0, B=$techmap\common.led_blink.$procmux$9260_Y [5], S=\common.pb.n_reset) into $auto$simplemap.cc:420:simplemap_dff$16258 (SB_DFFE).
  Merging $auto$simplemap.cc:277:simplemap_mux$16487 (A=1'0, B=$techmap\common.led_blink.$procmux$9260_Y [6], S=\common.pb.n_reset) into $auto$simplemap.cc:420:simplemap_dff$16259 (SB_DFFE).
  Merging $auto$simplemap.cc:277:simplemap_mux$16488 (A=1'0, B=$techmap\common.led_blink.$procmux$9260_Y [7], S=\common.pb.n_reset) into $auto$simplemap.cc:420:simplemap_dff$16260 (SB_DFFE).
  Merging $auto$simplemap.cc:277:simplemap_mux$16489 (A=1'0, B=$techmap\common.led_blink.$procmux$9260_Y [8], S=\common.pb.n_reset) into $auto$simplemap.cc:420:simplemap_dff$16261 (SB_DFFE).
  Merging $auto$simplemap.cc:277:simplemap_mux$16490 (A=1'0, B=$techmap\common.led_blink.$procmux$9260_Y [9], S=\common.pb.n_reset) into $auto$simplemap.cc:420:simplemap_dff$16262 (SB_DFFE).
  Merging $auto$simplemap.cc:277:simplemap_mux$16491 (A=1'0, B=$techmap\common.led_blink.$procmux$9260_Y [10], S=\common.pb.n_reset) into $auto$simplemap.cc:420:simplemap_dff$16263 (SB_DFFE).
  Merging $auto$simplemap.cc:277:simplemap_mux$16492 (A=1'0, B=$techmap\common.led_blink.$procmux$9260_Y [11], S=\common.pb.n_reset) into $auto$simplemap.cc:420:simplemap_dff$16264 (SB_DFFE).
  Merging $auto$simplemap.cc:277:simplemap_mux$16493 (A=1'0, B=$techmap\common.led_blink.$procmux$9260_Y [12], S=\common.pb.n_reset) into $auto$simplemap.cc:420:simplemap_dff$16265 (SB_DFFE).
  Merging $auto$simplemap.cc:277:simplemap_mux$16494 (A=1'0, B=$techmap\common.led_blink.$procmux$9260_Y [13], S=\common.pb.n_reset) into $auto$simplemap.cc:420:simplemap_dff$16266 (SB_DFFE).
  Merging $auto$simplemap.cc:277:simplemap_mux$16495 (A=1'0, B=$techmap\common.led_blink.$procmux$9260_Y [14], S=\common.pb.n_reset) into $auto$simplemap.cc:420:simplemap_dff$16267 (SB_DFFE).
  Merging $auto$simplemap.cc:277:simplemap_mux$16496 (A=1'0, B=$techmap\common.led_blink.$procmux$9260_Y [15], S=\common.pb.n_reset) into $auto$simplemap.cc:420:simplemap_dff$16268 (SB_DFFE).
  Merging $auto$simplemap.cc:277:simplemap_mux$16497 (A=1'0, B=$techmap\common.led_blink.$procmux$9260_Y [16], S=\common.pb.n_reset) into $auto$simplemap.cc:420:simplemap_dff$16269 (SB_DFFE).
  Merging $auto$simplemap.cc:277:simplemap_mux$16498 (A=1'0, B=$techmap\common.led_blink.$procmux$9260_Y [17], S=\common.pb.n_reset) into $auto$simplemap.cc:420:simplemap_dff$16270 (SB_DFFE).
  Merging $auto$simplemap.cc:277:simplemap_mux$16499 (A=1'0, B=$techmap\common.led_blink.$procmux$9260_Y [18], S=\common.pb.n_reset) into $auto$simplemap.cc:420:simplemap_dff$16271 (SB_DFFE).
  Merging $auto$simplemap.cc:277:simplemap_mux$16500 (A=1'0, B=$techmap\common.led_blink.$procmux$9260_Y [19], S=\common.pb.n_reset) into $auto$simplemap.cc:420:simplemap_dff$16272 (SB_DFFE).
  Merging $auto$simplemap.cc:277:simplemap_mux$16501 (A=1'0, B=$techmap\common.led_blink.$procmux$9260_Y [20], S=\common.pb.n_reset) into $auto$simplemap.cc:420:simplemap_dff$16273 (SB_DFFE).
  Merging $auto$simplemap.cc:277:simplemap_mux$16502 (A=1'0, B=$techmap\common.led_blink.$procmux$9260_Y [21], S=\common.pb.n_reset) into $auto$simplemap.cc:420:simplemap_dff$16274 (SB_DFFE).
  Merging $auto$simplemap.cc:277:simplemap_mux$16503 (A=1'0, B=$techmap\common.led_blink.$procmux$9260_Y [22], S=\common.pb.n_reset) into $auto$simplemap.cc:420:simplemap_dff$16275 (SB_DFFE).
  Merging $auto$simplemap.cc:277:simplemap_mux$16504 (A=1'0, B=$techmap\common.led_blink.$procmux$9260_Y [23], S=\common.pb.n_reset) into $auto$simplemap.cc:420:simplemap_dff$16276 (SB_DFFE).
  Merging $auto$simplemap.cc:277:simplemap_mux$16505 (A=1'0, B=$techmap\common.led_blink.$procmux$9260_Y [24], S=\common.pb.n_reset) into $auto$simplemap.cc:420:simplemap_dff$16277 (SB_DFFE).
  Merging $auto$simplemap.cc:277:simplemap_mux$16506 (A=1'0, B=$techmap\common.led_blink.$procmux$9260_Y [25], S=\common.pb.n_reset) into $auto$simplemap.cc:420:simplemap_dff$16278 (SB_DFFE).
  Merging $auto$simplemap.cc:277:simplemap_mux$16507 (A=1'0, B=$techmap\common.led_blink.$procmux$9260_Y [26], S=\common.pb.n_reset) into $auto$simplemap.cc:420:simplemap_dff$16279 (SB_DFFE).
  Merging $auto$simplemap.cc:277:simplemap_mux$16508 (A=1'0, B=$techmap\common.led_blink.$procmux$9260_Y [27], S=\common.pb.n_reset) into $auto$simplemap.cc:420:simplemap_dff$16280 (SB_DFFE).
  Merging $auto$simplemap.cc:277:simplemap_mux$16509 (A=1'0, B=$techmap\common.led_blink.$procmux$9260_Y [28], S=\common.pb.n_reset) into $auto$simplemap.cc:420:simplemap_dff$16281 (SB_DFFE).
  Merging $auto$simplemap.cc:277:simplemap_mux$16510 (A=1'0, B=$techmap\common.led_blink.$procmux$9260_Y [29], S=\common.pb.n_reset) into $auto$simplemap.cc:420:simplemap_dff$16282 (SB_DFFE).
  Merging $auto$simplemap.cc:277:simplemap_mux$16511 (A=1'0, B=$techmap\common.led_blink.$procmux$9260_Y [30], S=\common.pb.n_reset) into $auto$simplemap.cc:420:simplemap_dff$16283 (SB_DFFE).
  Merging $auto$simplemap.cc:277:simplemap_mux$16481 (A=1'0, B=$techmap\common.led_blink.$procmux$9260_Y [0], S=\common.pb.n_reset) into $auto$simplemap.cc:420:simplemap_dff$16253 (SB_DFFE).
  Merging $auto$simplemap.cc:277:simplemap_mux$16512 (A=1'0, B=$techmap\common.led_blink.$procmux$9260_Y [31], S=\common.pb.n_reset) into $auto$simplemap.cc:420:simplemap_dff$16284 (SB_DFFE).
  Merging $auto$simplemap.cc:277:simplemap_mux$16322 (A=1'0, B=$techmap\common.led_blink.$procmux$9274_Y [1], S=\common.pb.n_reset) into $auto$simplemap.cc:420:simplemap_dff$16286 (SB_DFFE).
  Merging $auto$simplemap.cc:277:simplemap_mux$16323 (A=1'0, B=$techmap\common.led_blink.$procmux$9274_Y [2], S=\common.pb.n_reset) into $auto$simplemap.cc:420:simplemap_dff$16287 (SB_DFFE).
  Merging $auto$simplemap.cc:277:simplemap_mux$16324 (A=1'0, B=$techmap\common.led_blink.$procmux$9274_Y [3], S=\common.pb.n_reset) into $auto$simplemap.cc:420:simplemap_dff$16288 (SB_DFFE).
  Merging $auto$simplemap.cc:277:simplemap_mux$16325 (A=1'0, B=$techmap\common.led_blink.$procmux$9274_Y [4], S=\common.pb.n_reset) into $auto$simplemap.cc:420:simplemap_dff$16289 (SB_DFFE).
  Merging $auto$simplemap.cc:277:simplemap_mux$16326 (A=1'0, B=$techmap\common.led_blink.$procmux$9274_Y [5], S=\common.pb.n_reset) into $auto$simplemap.cc:420:simplemap_dff$16290 (SB_DFFE).
  Merging $auto$simplemap.cc:277:simplemap_mux$16327 (A=1'0, B=$techmap\common.led_blink.$procmux$9274_Y [6], S=\common.pb.n_reset) into $auto$simplemap.cc:420:simplemap_dff$16291 (SB_DFFE).
  Merging $auto$simplemap.cc:277:simplemap_mux$16328 (A=1'0, B=$techmap\common.led_blink.$procmux$9274_Y [7], S=\common.pb.n_reset) into $auto$simplemap.cc:420:simplemap_dff$16292 (SB_DFFE).
  Merging $auto$simplemap.cc:277:simplemap_mux$16329 (A=1'0, B=$techmap\common.led_blink.$procmux$9274_Y [8], S=\common.pb.n_reset) into $auto$simplemap.cc:420:simplemap_dff$16293 (SB_DFFE).
  Merging $auto$simplemap.cc:277:simplemap_mux$16330 (A=1'0, B=$techmap\common.led_blink.$procmux$9274_Y [9], S=\common.pb.n_reset) into $auto$simplemap.cc:420:simplemap_dff$16294 (SB_DFFE).
  Merging $auto$simplemap.cc:277:simplemap_mux$16331 (A=1'0, B=$techmap\common.led_blink.$procmux$9274_Y [10], S=\common.pb.n_reset) into $auto$simplemap.cc:420:simplemap_dff$16295 (SB_DFFE).
  Merging $auto$simplemap.cc:277:simplemap_mux$16332 (A=1'0, B=$techmap\common.led_blink.$procmux$9274_Y [11], S=\common.pb.n_reset) into $auto$simplemap.cc:420:simplemap_dff$16296 (SB_DFFE).
  Merging $auto$simplemap.cc:277:simplemap_mux$16333 (A=1'0, B=$techmap\common.led_blink.$procmux$9274_Y [12], S=\common.pb.n_reset) into $auto$simplemap.cc:420:simplemap_dff$16297 (SB_DFFE).
  Merging $auto$simplemap.cc:277:simplemap_mux$16334 (A=1'0, B=$techmap\common.led_blink.$procmux$9274_Y [13], S=\common.pb.n_reset) into $auto$simplemap.cc:420:simplemap_dff$16298 (SB_DFFE).
  Merging $auto$simplemap.cc:277:simplemap_mux$16335 (A=1'0, B=$techmap\common.led_blink.$procmux$9274_Y [14], S=\common.pb.n_reset) into $auto$simplemap.cc:420:simplemap_dff$16299 (SB_DFFE).
  Merging $auto$simplemap.cc:277:simplemap_mux$16336 (A=1'0, B=$techmap\common.led_blink.$procmux$9274_Y [15], S=\common.pb.n_reset) into $auto$simplemap.cc:420:simplemap_dff$16300 (SB_DFFE).
  Merging $auto$simplemap.cc:277:simplemap_mux$16337 (A=1'0, B=$techmap\common.led_blink.$procmux$9274_Y [16], S=\common.pb.n_reset) into $auto$simplemap.cc:420:simplemap_dff$16301 (SB_DFFE).
  Merging $auto$simplemap.cc:277:simplemap_mux$16338 (A=1'0, B=$techmap\common.led_blink.$procmux$9274_Y [17], S=\common.pb.n_reset) into $auto$simplemap.cc:420:simplemap_dff$16302 (SB_DFFE).
  Merging $auto$simplemap.cc:277:simplemap_mux$16339 (A=1'0, B=$techmap\common.led_blink.$procmux$9274_Y [18], S=\common.pb.n_reset) into $auto$simplemap.cc:420:simplemap_dff$16303 (SB_DFFE).
  Merging $auto$simplemap.cc:277:simplemap_mux$16340 (A=1'0, B=$techmap\common.led_blink.$procmux$9274_Y [19], S=\common.pb.n_reset) into $auto$simplemap.cc:420:simplemap_dff$16304 (SB_DFFE).
  Merging $auto$simplemap.cc:277:simplemap_mux$16341 (A=1'0, B=$techmap\common.led_blink.$procmux$9274_Y [20], S=\common.pb.n_reset) into $auto$simplemap.cc:420:simplemap_dff$16305 (SB_DFFE).
  Merging $auto$simplemap.cc:277:simplemap_mux$16342 (A=1'0, B=$techmap\common.led_blink.$procmux$9274_Y [21], S=\common.pb.n_reset) into $auto$simplemap.cc:420:simplemap_dff$16306 (SB_DFFE).
  Merging $auto$simplemap.cc:277:simplemap_mux$16343 (A=1'0, B=$techmap\common.led_blink.$procmux$9274_Y [22], S=\common.pb.n_reset) into $auto$simplemap.cc:420:simplemap_dff$16307 (SB_DFFE).
  Merging $auto$simplemap.cc:277:simplemap_mux$16344 (A=1'0, B=$techmap\common.led_blink.$procmux$9274_Y [23], S=\common.pb.n_reset) into $auto$simplemap.cc:420:simplemap_dff$16308 (SB_DFFE).
  Merging $auto$simplemap.cc:277:simplemap_mux$16345 (A=1'0, B=$techmap\common.led_blink.$procmux$9274_Y [24], S=\common.pb.n_reset) into $auto$simplemap.cc:420:simplemap_dff$16309 (SB_DFFE).
  Merging $auto$simplemap.cc:277:simplemap_mux$16346 (A=1'0, B=$techmap\common.led_blink.$procmux$9274_Y [25], S=\common.pb.n_reset) into $auto$simplemap.cc:420:simplemap_dff$16310 (SB_DFFE).
  Merging $auto$simplemap.cc:277:simplemap_mux$16347 (A=1'0, B=$techmap\common.led_blink.$procmux$9274_Y [26], S=\common.pb.n_reset) into $auto$simplemap.cc:420:simplemap_dff$16311 (SB_DFFE).
  Merging $auto$simplemap.cc:277:simplemap_mux$16348 (A=1'0, B=$techmap\common.led_blink.$procmux$9274_Y [27], S=\common.pb.n_reset) into $auto$simplemap.cc:420:simplemap_dff$16312 (SB_DFFE).
  Merging $auto$simplemap.cc:277:simplemap_mux$16349 (A=1'0, B=$techmap\common.led_blink.$procmux$9274_Y [28], S=\common.pb.n_reset) into $auto$simplemap.cc:420:simplemap_dff$16313 (SB_DFFE).
  Merging $auto$simplemap.cc:277:simplemap_mux$16350 (A=1'0, B=$techmap\common.led_blink.$procmux$9274_Y [29], S=\common.pb.n_reset) into $auto$simplemap.cc:420:simplemap_dff$16314 (SB_DFFE).
  Merging $auto$simplemap.cc:277:simplemap_mux$16351 (A=1'0, B=$techmap\common.led_blink.$procmux$9274_Y [30], S=\common.pb.n_reset) into $auto$simplemap.cc:420:simplemap_dff$16315 (SB_DFFE).
  Merging $auto$simplemap.cc:277:simplemap_mux$20151 (A=1'0, B=$techmap$techmap\common.pb.spirx_lencalc.$procmux$14747.$ternary$/home/mb/fpga-toolchain/yosys/bin/../share/yosys/techmap.v:445$18291_Y [6], S=\common.pb.spirx_lencalc.n_reset) into $auto$simplemap.cc:420:simplemap_dff$20068 (SB_DFF).
  Merging $auto$simplemap.cc:277:simplemap_mux$17731 (A=1'0, B=\common.pb.uart.rx_mod.rx_irq, S=$techmap\common.pb.$and$profibus_phy_mod.v:1047$6261_Y) into $auto$simplemap.cc:420:simplemap_dff$17383 (SB_DFFE).
  Merging $auto$simplemap.cc:277:simplemap_mux$17704 (A=1'0, B=\common.pb.rx_buf_wr_addr_next [1], S=$techmap\common.pb.$and$profibus_phy_mod.v:1047$6261_Y) into $auto$simplemap.cc:420:simplemap_dff$17394 (SB_DFFE).
  Merging $auto$simplemap.cc:277:simplemap_mux$17705 (A=1'0, B=\common.pb.rx_buf_wr_addr_next [2], S=$techmap\common.pb.$and$profibus_phy_mod.v:1047$6261_Y) into $auto$simplemap.cc:420:simplemap_dff$17395 (SB_DFFE).
  Merging $auto$simplemap.cc:277:simplemap_mux$17706 (A=1'0, B=\common.pb.rx_buf_wr_addr_next [3], S=$techmap\common.pb.$and$profibus_phy_mod.v:1047$6261_Y) into $auto$simplemap.cc:420:simplemap_dff$17396 (SB_DFFE).
  Merging $auto$simplemap.cc:277:simplemap_mux$17707 (A=1'0, B=\common.pb.rx_buf_wr_addr_next [4], S=$techmap\common.pb.$and$profibus_phy_mod.v:1047$6261_Y) into $auto$simplemap.cc:420:simplemap_dff$17397 (SB_DFFE).
  Merging $auto$simplemap.cc:277:simplemap_mux$17708 (A=1'0, B=\common.pb.rx_buf_wr_addr_next [5], S=$techmap\common.pb.$and$profibus_phy_mod.v:1047$6261_Y) into $auto$simplemap.cc:420:simplemap_dff$17398 (SB_DFFE).
  Merging $auto$simplemap.cc:277:simplemap_mux$17709 (A=1'0, B=\common.pb.rx_buf_wr_addr_next [6], S=$techmap\common.pb.$and$profibus_phy_mod.v:1047$6261_Y) into $auto$simplemap.cc:420:simplemap_dff$17399 (SB_DFFE).
  Merging $auto$simplemap.cc:277:simplemap_mux$17710 (A=1'0, B=\common.pb.rx_buf_wr_addr_next [7], S=$techmap\common.pb.$and$profibus_phy_mod.v:1047$6261_Y) into $auto$simplemap.cc:420:simplemap_dff$17400 (SB_DFFE).
  Merging $auto$simplemap.cc:277:simplemap_mux$17804 (A=1'0, B=\common.pb.tx_buf.rd_data1 [1], S=$techmap\common.pb.$and$profibus_phy_mod.v:1047$6261_Y) into $auto$simplemap.cc:420:simplemap_dff$17402 (SB_DFFE).
  Merging $auto$simplemap.cc:277:simplemap_mux$17703 (A=1'0, B=\common.pb.rx_buf_wr_addr_next [0], S=$techmap\common.pb.$and$profibus_phy_mod.v:1047$6261_Y) into $auto$simplemap.cc:420:simplemap_dff$17393 (SB_DFFE).
  Merging $auto$simplemap.cc:277:simplemap_mux$17805 (A=1'0, B=\common.pb.tx_buf.rd_data1 [2], S=$techmap\common.pb.$and$profibus_phy_mod.v:1047$6261_Y) into $auto$simplemap.cc:420:simplemap_dff$17403 (SB_DFFE).
  Merging $auto$simplemap.cc:277:simplemap_mux$17806 (A=1'0, B=\common.pb.tx_buf.rd_data1 [3], S=$techmap\common.pb.$and$profibus_phy_mod.v:1047$6261_Y) into $auto$simplemap.cc:420:simplemap_dff$17404 (SB_DFFE).
  Merging $auto$simplemap.cc:277:simplemap_mux$17807 (A=1'0, B=\common.pb.tx_buf.rd_data1 [4], S=$techmap\common.pb.$and$profibus_phy_mod.v:1047$6261_Y) into $auto$simplemap.cc:420:simplemap_dff$17405 (SB_DFFE).
  Merging $auto$simplemap.cc:277:simplemap_mux$17808 (A=1'0, B=\common.pb.tx_buf.rd_data1 [5], S=$techmap\common.pb.$and$profibus_phy_mod.v:1047$6261_Y) into $auto$simplemap.cc:420:simplemap_dff$17406 (SB_DFFE).
  Merging $auto$simplemap.cc:277:simplemap_mux$17809 (A=1'0, B=\common.pb.tx_buf.rd_data1 [6], S=$techmap\common.pb.$and$profibus_phy_mod.v:1047$6261_Y) into $auto$simplemap.cc:420:simplemap_dff$17407 (SB_DFFE).
  Merging $auto$simplemap.cc:277:simplemap_mux$17810 (A=1'0, B=\common.pb.tx_buf.rd_data1 [7], S=$techmap\common.pb.$and$profibus_phy_mod.v:1047$6261_Y) into $auto$simplemap.cc:420:simplemap_dff$17408 (SB_DFFE).
  Merging $auto$simplemap.cc:277:simplemap_mux$17772 (A=1'0, B=$auto$simplemap.cc:309:simplemap_lut$25661 [1], S=$techmap\common.pb.$and$profibus_phy_mod.v:1047$6261_Y) into $auto$simplemap.cc:420:simplemap_dff$17410 (SB_DFFE).
  Merging $auto$simplemap.cc:277:simplemap_mux$17803 (A=1'0, B=\common.pb.tx_buf.rd_data1 [0], S=$techmap\common.pb.$and$profibus_phy_mod.v:1047$6261_Y) into $auto$simplemap.cc:420:simplemap_dff$17401 (SB_DFFE).
  Merging $auto$simplemap.cc:277:simplemap_mux$17773 (A=1'0, B=$auto$wreduce.cc:455:run$15906 [2], S=$techmap\common.pb.$and$profibus_phy_mod.v:1047$6261_Y) into $auto$simplemap.cc:420:simplemap_dff$17411 (SB_DFFE).
  Merging $auto$simplemap.cc:277:simplemap_mux$17774 (A=1'0, B=$auto$wreduce.cc:455:run$15906 [3], S=$techmap\common.pb.$and$profibus_phy_mod.v:1047$6261_Y) into $auto$simplemap.cc:420:simplemap_dff$17412 (SB_DFFE).
  Merging $auto$simplemap.cc:277:simplemap_mux$17775 (A=1'0, B=$auto$wreduce.cc:455:run$15906 [4], S=$techmap\common.pb.$and$profibus_phy_mod.v:1047$6261_Y) into $auto$simplemap.cc:420:simplemap_dff$17413 (SB_DFFE).
  Merging $auto$simplemap.cc:277:simplemap_mux$17776 (A=1'0, B=$auto$wreduce.cc:455:run$15906 [5], S=$techmap\common.pb.$and$profibus_phy_mod.v:1047$6261_Y) into $auto$simplemap.cc:420:simplemap_dff$17414 (SB_DFFE).
  Merging $auto$simplemap.cc:277:simplemap_mux$17777 (A=1'0, B=$auto$wreduce.cc:455:run$15906 [6], S=$techmap\common.pb.$and$profibus_phy_mod.v:1047$6261_Y) into $auto$simplemap.cc:420:simplemap_dff$17415 (SB_DFFE).
  Merging $auto$simplemap.cc:277:simplemap_mux$17778 (A=1'0, B=$auto$wreduce.cc:455:run$15906 [7], S=$techmap\common.pb.$and$profibus_phy_mod.v:1047$6261_Y) into $auto$simplemap.cc:420:simplemap_dff$17416 (SB_DFFE).
  Merging $auto$simplemap.cc:277:simplemap_mux$17771 (A=1'0, B=$auto$wreduce.cc:455:run$15906 [0], S=$techmap\common.pb.$and$profibus_phy_mod.v:1047$6261_Y) into $auto$simplemap.cc:420:simplemap_dff$17409 (SB_DFFE).
  Merging $auto$simplemap.cc:277:simplemap_mux$20989 (A=1'0, B=$techmap\common.pb.uart.rx_mod.$procmux$15345_Y, S=\common.pb.uart.rx_mod.n_reset) into $auto$simplemap.cc:420:simplemap_dff$20916 (SB_DFFE).
  Merging $auto$simplemap.cc:277:simplemap_mux$20485 (A=1'0, B=$techmap\common.pb.uart.$procmux$14906_Y, S=\common.pb.n_reset) into $auto$simplemap.cc:420:simplemap_dff$20484 (SB_DFF).
  Merging $auto$simplemap.cc:277:simplemap_mux$20555 (A=1'0, B=$techmap\common.pb.uart.tx_mod.$procmux$15610_Y [0], S=\common.pb.uart.tx_n_reset) into $auto$simplemap.cc:420:simplemap_dff$20551 (SB_DFFE).
  Merging $auto$simplemap.cc:277:simplemap_mux$20649 (A=1'0, B=$techmap\common.pb.uart.tx_mod.$procmux$15460_Y, S=\common.pb.uart.tx_n_reset) into $auto$simplemap.cc:420:simplemap_dff$20540 (SB_DFFE).
  Merging $auto$simplemap.cc:277:simplemap_mux$18540 (A=1'0, B=$techmap$techmap\common.pb.$procmux$14257.$ternary$/home/mb/fpga-toolchain/yosys/bin/../share/yosys/techmap.v:445$18549_Y, S=$techmap\common.pb.$and$profibus_phy_mod.v:1047$6261_Y) into $auto$simplemap.cc:420:simplemap_dff$17467 (SB_DFF).
  Merging $auto$simplemap.cc:277:simplemap_mux$18344 (A=1'0, B=$techmap$techmap\common.pb.$procmux$14316.$ternary$/home/mb/fpga-toolchain/yosys/bin/../share/yosys/techmap.v:445$18472_Y [1], S=$techmap\common.pb.$and$profibus_phy_mod.v:1047$6261_Y) into $auto$simplemap.cc:420:simplemap_dff$17479 (SB_DFF).
  Merging $auto$simplemap.cc:277:simplemap_mux$18345 (A=1'0, B=$techmap$techmap\common.pb.$procmux$14316.$ternary$/home/mb/fpga-toolchain/yosys/bin/../share/yosys/techmap.v:445$18472_Y [2], S=$techmap\common.pb.$and$profibus_phy_mod.v:1047$6261_Y) into $auto$simplemap.cc:420:simplemap_dff$17480 (SB_DFF).
  Merging $auto$simplemap.cc:277:simplemap_mux$18346 (A=1'0, B=$techmap$techmap\common.pb.$procmux$14316.$ternary$/home/mb/fpga-toolchain/yosys/bin/../share/yosys/techmap.v:445$18472_Y [3], S=$techmap\common.pb.$and$profibus_phy_mod.v:1047$6261_Y) into $auto$simplemap.cc:420:simplemap_dff$17481 (SB_DFF).
  Merging $auto$simplemap.cc:277:simplemap_mux$18347 (A=1'0, B=$techmap$techmap\common.pb.$procmux$14316.$ternary$/home/mb/fpga-toolchain/yosys/bin/../share/yosys/techmap.v:445$18472_Y [4], S=$techmap\common.pb.$and$profibus_phy_mod.v:1047$6261_Y) into $auto$simplemap.cc:420:simplemap_dff$17482 (SB_DFF).
  Merging $auto$simplemap.cc:277:simplemap_mux$18348 (A=1'0, B=$techmap$techmap\common.pb.$procmux$14316.$ternary$/home/mb/fpga-toolchain/yosys/bin/../share/yosys/techmap.v:445$18472_Y [5], S=$techmap\common.pb.$and$profibus_phy_mod.v:1047$6261_Y) into $auto$simplemap.cc:420:simplemap_dff$17483 (SB_DFF).
  Merging $auto$simplemap.cc:277:simplemap_mux$18349 (A=1'0, B=$techmap$techmap\common.pb.$procmux$14316.$ternary$/home/mb/fpga-toolchain/yosys/bin/../share/yosys/techmap.v:445$18472_Y [6], S=$techmap\common.pb.$and$profibus_phy_mod.v:1047$6261_Y) into $auto$simplemap.cc:420:simplemap_dff$17484 (SB_DFF).
  Merging $auto$simplemap.cc:277:simplemap_mux$18350 (A=1'0, B=$techmap$techmap\common.pb.$procmux$14316.$ternary$/home/mb/fpga-toolchain/yosys/bin/../share/yosys/techmap.v:445$18472_Y [7], S=$techmap\common.pb.$and$profibus_phy_mod.v:1047$6261_Y) into $auto$simplemap.cc:420:simplemap_dff$17485 (SB_DFF).
  Merging $auto$simplemap.cc:277:simplemap_mux$18351 (A=1'0, B=$techmap$techmap\common.pb.$procmux$14316.$ternary$/home/mb/fpga-toolchain/yosys/bin/../share/yosys/techmap.v:445$18472_Y [8], S=$techmap\common.pb.$and$profibus_phy_mod.v:1047$6261_Y) into $auto$simplemap.cc:420:simplemap_dff$17486 (SB_DFF).
  Merging $auto$simplemap.cc:277:simplemap_mux$18352 (A=1'0, B=$techmap$techmap\common.pb.$procmux$14316.$ternary$/home/mb/fpga-toolchain/yosys/bin/../share/yosys/techmap.v:445$18472_Y [9], S=$techmap\common.pb.$and$profibus_phy_mod.v:1047$6261_Y) into $auto$simplemap.cc:420:simplemap_dff$17487 (SB_DFF).
  Merging $auto$simplemap.cc:277:simplemap_mux$18353 (A=1'0, B=$techmap$techmap\common.pb.$procmux$14316.$ternary$/home/mb/fpga-toolchain/yosys/bin/../share/yosys/techmap.v:445$18472_Y [10], S=$techmap\common.pb.$and$profibus_phy_mod.v:1047$6261_Y) into $auto$simplemap.cc:420:simplemap_dff$17488 (SB_DFF).
  Merging $auto$simplemap.cc:277:simplemap_mux$18354 (A=1'0, B=$techmap$techmap\common.pb.$procmux$14316.$ternary$/home/mb/fpga-toolchain/yosys/bin/../share/yosys/techmap.v:445$18472_Y [11], S=$techmap\common.pb.$and$profibus_phy_mod.v:1047$6261_Y) into $auto$simplemap.cc:420:simplemap_dff$17489 (SB_DFF).
  Merging $auto$simplemap.cc:277:simplemap_mux$18355 (A=1'0, B=$techmap$techmap\common.pb.$procmux$14316.$ternary$/home/mb/fpga-toolchain/yosys/bin/../share/yosys/techmap.v:445$18472_Y [12], S=$techmap\common.pb.$and$profibus_phy_mod.v:1047$6261_Y) into $auto$simplemap.cc:420:simplemap_dff$17490 (SB_DFF).
  Merging $auto$simplemap.cc:277:simplemap_mux$18356 (A=1'0, B=$techmap$techmap\common.pb.$procmux$14316.$ternary$/home/mb/fpga-toolchain/yosys/bin/../share/yosys/techmap.v:445$18472_Y [13], S=$techmap\common.pb.$and$profibus_phy_mod.v:1047$6261_Y) into $auto$simplemap.cc:420:simplemap_dff$17491 (SB_DFF).
  Merging $auto$simplemap.cc:277:simplemap_mux$18357 (A=1'0, B=$techmap$techmap\common.pb.$procmux$14316.$ternary$/home/mb/fpga-toolchain/yosys/bin/../share/yosys/techmap.v:445$18472_Y [14], S=$techmap\common.pb.$and$profibus_phy_mod.v:1047$6261_Y) into $auto$simplemap.cc:420:simplemap_dff$17492 (SB_DFF).
  Merging $auto$simplemap.cc:277:simplemap_mux$18358 (A=1'0, B=$techmap$techmap\common.pb.$procmux$14316.$ternary$/home/mb/fpga-toolchain/yosys/bin/../share/yosys/techmap.v:445$18472_Y [15], S=$techmap\common.pb.$and$profibus_phy_mod.v:1047$6261_Y) into $auto$simplemap.cc:420:simplemap_dff$17493 (SB_DFF).
  Merging $auto$simplemap.cc:277:simplemap_mux$18359 (A=1'0, B=$techmap$techmap\common.pb.$procmux$14316.$ternary$/home/mb/fpga-toolchain/yosys/bin/../share/yosys/techmap.v:445$18472_Y [16], S=$techmap\common.pb.$and$profibus_phy_mod.v:1047$6261_Y) into $auto$simplemap.cc:420:simplemap_dff$17494 (SB_DFF).
  Merging $auto$simplemap.cc:277:simplemap_mux$18360 (A=1'0, B=$techmap$techmap\common.pb.$procmux$14316.$ternary$/home/mb/fpga-toolchain/yosys/bin/../share/yosys/techmap.v:445$18472_Y [17], S=$techmap\common.pb.$and$profibus_phy_mod.v:1047$6261_Y) into $auto$simplemap.cc:420:simplemap_dff$17495 (SB_DFF).
  Merging $auto$simplemap.cc:277:simplemap_mux$18361 (A=1'0, B=$techmap$techmap\common.pb.$procmux$14316.$ternary$/home/mb/fpga-toolchain/yosys/bin/../share/yosys/techmap.v:445$18472_Y [18], S=$techmap\common.pb.$and$profibus_phy_mod.v:1047$6261_Y) into $auto$simplemap.cc:420:simplemap_dff$17496 (SB_DFF).
  Merging $auto$simplemap.cc:277:simplemap_mux$18362 (A=1'0, B=$techmap$techmap\common.pb.$procmux$14316.$ternary$/home/mb/fpga-toolchain/yosys/bin/../share/yosys/techmap.v:445$18472_Y [19], S=$techmap\common.pb.$and$profibus_phy_mod.v:1047$6261_Y) into $auto$simplemap.cc:420:simplemap_dff$17497 (SB_DFF).
  Merging $auto$simplemap.cc:277:simplemap_mux$18363 (A=1'0, B=$techmap$techmap\common.pb.$procmux$14316.$ternary$/home/mb/fpga-toolchain/yosys/bin/../share/yosys/techmap.v:445$18472_Y [20], S=$techmap\common.pb.$and$profibus_phy_mod.v:1047$6261_Y) into $auto$simplemap.cc:420:simplemap_dff$17498 (SB_DFF).
  Merging $auto$simplemap.cc:277:simplemap_mux$18364 (A=1'0, B=$techmap$techmap\common.pb.$procmux$14316.$ternary$/home/mb/fpga-toolchain/yosys/bin/../share/yosys/techmap.v:445$18472_Y [21], S=$techmap\common.pb.$and$profibus_phy_mod.v:1047$6261_Y) into $auto$simplemap.cc:420:simplemap_dff$17499 (SB_DFF).
  Merging $auto$simplemap.cc:277:simplemap_mux$18365 (A=1'0, B=$techmap$techmap\common.pb.$procmux$14316.$ternary$/home/mb/fpga-toolchain/yosys/bin/../share/yosys/techmap.v:445$18472_Y [22], S=$techmap\common.pb.$and$profibus_phy_mod.v:1047$6261_Y) into $auto$simplemap.cc:420:simplemap_dff$17500 (SB_DFF).
  Merging $auto$simplemap.cc:277:simplemap_mux$18366 (A=1'0, B=$techmap$techmap\common.pb.$procmux$14316.$ternary$/home/mb/fpga-toolchain/yosys/bin/../share/yosys/techmap.v:445$18472_Y [23], S=$techmap\common.pb.$and$profibus_phy_mod.v:1047$6261_Y) into $auto$simplemap.cc:420:simplemap_dff$17501 (SB_DFF).
  Merging $auto$simplemap.cc:277:simplemap_mux$18312 (A=1'0, B=$techmap$techmap\common.pb.$procmux$14335.$ternary$/home/mb/fpga-toolchain/yosys/bin/../share/yosys/techmap.v:445$18291_Y [1], S=$techmap\common.pb.$and$profibus_phy_mod.v:1047$6261_Y) into $auto$simplemap.cc:420:simplemap_dff$17511 (SB_DFF).
  Merging $auto$simplemap.cc:277:simplemap_mux$18343 (A=1'0, B=$techmap$techmap\common.pb.$procmux$14316.$ternary$/home/mb/fpga-toolchain/yosys/bin/../share/yosys/techmap.v:445$18472_Y [0], S=$techmap\common.pb.$and$profibus_phy_mod.v:1047$6261_Y) into $auto$simplemap.cc:420:simplemap_dff$17478 (SB_DFF).
  Merging $auto$simplemap.cc:277:simplemap_mux$18313 (A=1'0, B=$techmap$techmap\common.pb.$procmux$14335.$ternary$/home/mb/fpga-toolchain/yosys/bin/../share/yosys/techmap.v:445$18291_Y [2], S=$techmap\common.pb.$and$profibus_phy_mod.v:1047$6261_Y) into $auto$simplemap.cc:420:simplemap_dff$17512 (SB_DFF).
  Merging $auto$simplemap.cc:277:simplemap_mux$18314 (A=1'0, B=$techmap$techmap\common.pb.$procmux$14335.$ternary$/home/mb/fpga-toolchain/yosys/bin/../share/yosys/techmap.v:445$18291_Y [3], S=$techmap\common.pb.$and$profibus_phy_mod.v:1047$6261_Y) into $auto$simplemap.cc:420:simplemap_dff$17513 (SB_DFF).
  Merging $auto$simplemap.cc:277:simplemap_mux$18315 (A=1'0, B=$techmap$techmap\common.pb.$procmux$14335.$ternary$/home/mb/fpga-toolchain/yosys/bin/../share/yosys/techmap.v:445$18291_Y [4], S=$techmap\common.pb.$and$profibus_phy_mod.v:1047$6261_Y) into $auto$simplemap.cc:420:simplemap_dff$17514 (SB_DFF).
  Merging $auto$simplemap.cc:277:simplemap_mux$18316 (A=1'0, B=$techmap$techmap\common.pb.$procmux$14335.$ternary$/home/mb/fpga-toolchain/yosys/bin/../share/yosys/techmap.v:445$18291_Y [5], S=$techmap\common.pb.$and$profibus_phy_mod.v:1047$6261_Y) into $auto$simplemap.cc:420:simplemap_dff$17515 (SB_DFF).
  Merging $auto$simplemap.cc:277:simplemap_mux$18317 (A=1'0, B=$techmap$techmap\common.pb.$procmux$14335.$ternary$/home/mb/fpga-toolchain/yosys/bin/../share/yosys/techmap.v:445$18291_Y [6], S=$techmap\common.pb.$and$profibus_phy_mod.v:1047$6261_Y) into $auto$simplemap.cc:420:simplemap_dff$17516 (SB_DFF).
  Merging $auto$simplemap.cc:277:simplemap_mux$18318 (A=1'0, B=$techmap$techmap\common.pb.$procmux$14335.$ternary$/home/mb/fpga-toolchain/yosys/bin/../share/yosys/techmap.v:445$18291_Y [7], S=$techmap\common.pb.$and$profibus_phy_mod.v:1047$6261_Y) into $auto$simplemap.cc:420:simplemap_dff$17517 (SB_DFF).
  Merging $auto$simplemap.cc:277:simplemap_mux$18311 (A=1'0, B=$techmap$techmap\common.pb.$procmux$14335.$ternary$/home/mb/fpga-toolchain/yosys/bin/../share/yosys/techmap.v:445$18291_Y [0], S=$techmap\common.pb.$and$profibus_phy_mod.v:1047$6261_Y) into $auto$simplemap.cc:420:simplemap_dff$17510 (SB_DFF).
  Merging $auto$simplemap.cc:277:simplemap_mux$18150 (A=1'0, B=$techmap$techmap\common.pb.$procmux$14444.$ternary$/home/mb/fpga-toolchain/yosys/bin/../share/yosys/techmap.v:445$18186_Y [1], S=$techmap\common.pb.$and$profibus_phy_mod.v:1047$6261_Y) into $auto$simplemap.cc:420:simplemap_dff$17536 (SB_DFF).
  Merging $auto$simplemap.cc:277:simplemap_mux$18151 (A=1'0, B=$techmap$techmap\common.pb.$procmux$14444.$ternary$/home/mb/fpga-toolchain/yosys/bin/../share/yosys/techmap.v:445$18186_Y [2], S=$techmap\common.pb.$and$profibus_phy_mod.v:1047$6261_Y) into $auto$simplemap.cc:420:simplemap_dff$17537 (SB_DFF).
  Merging $auto$simplemap.cc:277:simplemap_mux$18149 (A=1'0, B=$techmap$techmap\common.pb.$procmux$14444.$ternary$/home/mb/fpga-toolchain/yosys/bin/../share/yosys/techmap.v:445$18186_Y [0], S=$techmap\common.pb.$and$profibus_phy_mod.v:1047$6261_Y) into $auto$simplemap.cc:420:simplemap_dff$17535 (SB_DFF).
  Merging $auto$simplemap.cc:277:simplemap_mux$17906 (A=1'0, B=$techmap$techmap\common.pb.$procmux$14563.$ternary$/home/mb/fpga-toolchain/yosys/bin/../share/yosys/techmap.v:445$17894_Y [1], S=$techmap\common.pb.$and$profibus_phy_mod.v:1047$6261_Y) into $auto$simplemap.cc:420:simplemap_dff$17591 (SB_DFF).
  Merging $auto$simplemap.cc:277:simplemap_mux$17937 (A=1'0, B=$techmap$techmap\common.pb.$procmux$14541.$ternary$/home/mb/fpga-toolchain/yosys/bin/../share/yosys/techmap.v:445$17949_Y, S=$techmap\common.pb.$and$profibus_phy_mod.v:1047$6261_Y) into $auto$simplemap.cc:420:simplemap_dff$17589 (SB_DFF).
  Merging $auto$simplemap.cc:277:simplemap_mux$17907 (A=1'0, B=$techmap$techmap\common.pb.$procmux$14563.$ternary$/home/mb/fpga-toolchain/yosys/bin/../share/yosys/techmap.v:445$17894_Y [2], S=$techmap\common.pb.$and$profibus_phy_mod.v:1047$6261_Y) into $auto$simplemap.cc:420:simplemap_dff$17592 (SB_DFF).
  Merging $auto$simplemap.cc:277:simplemap_mux$17908 (A=1'0, B=$techmap$techmap\common.pb.$procmux$14563.$ternary$/home/mb/fpga-toolchain/yosys/bin/../share/yosys/techmap.v:445$17894_Y [3], S=$techmap\common.pb.$and$profibus_phy_mod.v:1047$6261_Y) into $auto$simplemap.cc:420:simplemap_dff$17593 (SB_DFF).
  Merging $auto$simplemap.cc:277:simplemap_mux$17909 (A=1'0, B=$techmap$techmap\common.pb.$procmux$14563.$ternary$/home/mb/fpga-toolchain/yosys/bin/../share/yosys/techmap.v:445$17894_Y [4], S=$techmap\common.pb.$and$profibus_phy_mod.v:1047$6261_Y) into $auto$simplemap.cc:420:simplemap_dff$17594 (SB_DFF).
  Merging $auto$simplemap.cc:277:simplemap_mux$17910 (A=1'0, B=$techmap$techmap\common.pb.$procmux$14563.$ternary$/home/mb/fpga-toolchain/yosys/bin/../share/yosys/techmap.v:445$17894_Y [5], S=$techmap\common.pb.$and$profibus_phy_mod.v:1047$6261_Y) into $auto$simplemap.cc:420:simplemap_dff$17595 (SB_DFF).
  Merging $auto$simplemap.cc:277:simplemap_mux$17911 (A=1'0, B=$techmap$techmap\common.pb.$procmux$14563.$ternary$/home/mb/fpga-toolchain/yosys/bin/../share/yosys/techmap.v:445$17894_Y [6], S=$techmap\common.pb.$and$profibus_phy_mod.v:1047$6261_Y) into $auto$simplemap.cc:420:simplemap_dff$17596 (SB_DFF).
  Merging $auto$simplemap.cc:277:simplemap_mux$17912 (A=1'0, B=$techmap$techmap\common.pb.$procmux$14563.$ternary$/home/mb/fpga-toolchain/yosys/bin/../share/yosys/techmap.v:445$17894_Y [7], S=$techmap\common.pb.$and$profibus_phy_mod.v:1047$6261_Y) into $auto$simplemap.cc:420:simplemap_dff$17597 (SB_DFF).
  Merging $auto$simplemap.cc:277:simplemap_mux$17878 (A=1'0, B=$techmap$techmap\common.pb.$procmux$14583.$ternary$/home/mb/fpga-toolchain/yosys/bin/../share/yosys/techmap.v:445$17894_Y [1], S=$techmap\common.pb.$and$profibus_phy_mod.v:1047$6261_Y) into $auto$simplemap.cc:420:simplemap_dff$17599 (SB_DFF).
  Merging $auto$simplemap.cc:277:simplemap_mux$17905 (A=1'0, B=$techmap$techmap\common.pb.$procmux$14563.$ternary$/home/mb/fpga-toolchain/yosys/bin/../share/yosys/techmap.v:445$17894_Y [0], S=$techmap\common.pb.$and$profibus_phy_mod.v:1047$6261_Y) into $auto$simplemap.cc:420:simplemap_dff$17590 (SB_DFF).
  Merging $auto$simplemap.cc:277:simplemap_mux$17879 (A=1'0, B=$techmap$techmap\common.pb.$procmux$14583.$ternary$/home/mb/fpga-toolchain/yosys/bin/../share/yosys/techmap.v:445$17894_Y [2], S=$techmap\common.pb.$and$profibus_phy_mod.v:1047$6261_Y) into $auto$simplemap.cc:420:simplemap_dff$17600 (SB_DFF).
  Merging $auto$simplemap.cc:277:simplemap_mux$17880 (A=1'0, B=$techmap$techmap\common.pb.$procmux$14583.$ternary$/home/mb/fpga-toolchain/yosys/bin/../share/yosys/techmap.v:445$17894_Y [3], S=$techmap\common.pb.$and$profibus_phy_mod.v:1047$6261_Y) into $auto$simplemap.cc:420:simplemap_dff$17601 (SB_DFF).
  Merging $auto$simplemap.cc:277:simplemap_mux$17881 (A=1'0, B=$techmap$techmap\common.pb.$procmux$14583.$ternary$/home/mb/fpga-toolchain/yosys/bin/../share/yosys/techmap.v:445$17894_Y [4], S=$techmap\common.pb.$and$profibus_phy_mod.v:1047$6261_Y) into $auto$simplemap.cc:420:simplemap_dff$17602 (SB_DFF).
  Merging $auto$simplemap.cc:277:simplemap_mux$17882 (A=1'0, B=$techmap$techmap\common.pb.$procmux$14583.$ternary$/home/mb/fpga-toolchain/yosys/bin/../share/yosys/techmap.v:445$17894_Y [5], S=$techmap\common.pb.$and$profibus_phy_mod.v:1047$6261_Y) into $auto$simplemap.cc:420:simplemap_dff$17603 (SB_DFF).
  Merging $auto$simplemap.cc:277:simplemap_mux$17883 (A=1'0, B=$techmap$techmap\common.pb.$procmux$14583.$ternary$/home/mb/fpga-toolchain/yosys/bin/../share/yosys/techmap.v:445$17894_Y [6], S=$techmap\common.pb.$and$profibus_phy_mod.v:1047$6261_Y) into $auto$simplemap.cc:420:simplemap_dff$17604 (SB_DFF).
  Merging $auto$simplemap.cc:277:simplemap_mux$17884 (A=1'0, B=$techmap$techmap\common.pb.$procmux$14583.$ternary$/home/mb/fpga-toolchain/yosys/bin/../share/yosys/techmap.v:445$17894_Y [7], S=$techmap\common.pb.$and$profibus_phy_mod.v:1047$6261_Y) into $auto$simplemap.cc:420:simplemap_dff$17605 (SB_DFF).
  Merging $auto$simplemap.cc:277:simplemap_mux$19113 (A=1'0, B=$techmap$techmap\common.pb.$procmux$12803.$reduce_or$/home/mb/fpga-toolchain/yosys/bin/../share/yosys/techmap.v:441$19145_Y, S=$techmap\common.pb.$and$profibus_phy_mod.v:1047$6261_Y) into $auto$simplemap.cc:420:simplemap_dff$17611 (SB_DFFE).
  Merging $auto$simplemap.cc:277:simplemap_mux$17877 (A=1'0, B=$techmap$techmap\common.pb.$procmux$14583.$ternary$/home/mb/fpga-toolchain/yosys/bin/../share/yosys/techmap.v:445$17894_Y [0], S=$techmap\common.pb.$and$profibus_phy_mod.v:1047$6261_Y) into $auto$simplemap.cc:420:simplemap_dff$17598 (SB_DFF).
  Merging $auto$simplemap.cc:277:simplemap_mux$17846 (A=\common.pb.softreset, B=1'0, S=$techmap\common.pb.$and$profibus_phy_mod.v:1047$6261_Y) into $auto$simplemap.cc:420:simplemap_dff$17607 (SB_DFFE).
  Merging $auto$simplemap.cc:277:simplemap_mux$17842 (A=\common.pb.n_reset, B=1'1, S=$techmap\common.pb.$and$profibus_phy_mod.v:1047$6261_Y) into $auto$simplemap.cc:420:simplemap_dff$17608 (SB_DFFE).
  Merging $auto$simplemap.cc:277:simplemap_mux$19114 (A=1'0, B=$techmap$techmap\common.pb.$procmux$12803.$reduce_or$/home/mb/fpga-toolchain/yosys/bin/../share/yosys/techmap.v:441$19146_Y, S=$techmap\common.pb.$and$profibus_phy_mod.v:1047$6261_Y) into $auto$simplemap.cc:420:simplemap_dff$17612 (SB_DFFE).
  Merging $auto$simplemap.cc:277:simplemap_mux$19115 (A=1'0, B=$techmap$techmap\common.pb.$procmux$12803.$reduce_or$/home/mb/fpga-toolchain/yosys/bin/../share/yosys/techmap.v:441$19147_Y, S=$techmap\common.pb.$and$profibus_phy_mod.v:1047$6261_Y) into $auto$simplemap.cc:420:simplemap_dff$17613 (SB_DFFE).
  Merging $auto$simplemap.cc:277:simplemap_mux$19116 (A=1'0, B=$techmap$techmap\common.pb.$procmux$12803.$reduce_or$/home/mb/fpga-toolchain/yosys/bin/../share/yosys/techmap.v:441$19148_Y, S=$techmap\common.pb.$and$profibus_phy_mod.v:1047$6261_Y) into $auto$simplemap.cc:420:simplemap_dff$17614 (SB_DFFE).
  Merging $auto$simplemap.cc:277:simplemap_mux$19119 (A=1'0, B=$techmap$techmap\common.pb.$procmux$12803.$reduce_or$/home/mb/fpga-toolchain/yosys/bin/../share/yosys/techmap.v:441$19151_Y, S=$techmap\common.pb.$and$profibus_phy_mod.v:1047$6261_Y) into $auto$simplemap.cc:420:simplemap_dff$17617 (SB_DFFE).
  Merging $auto$simplemap.cc:277:simplemap_mux$19035 (A=1'0, B=$techmap\common.pb.$procmux$12896_Y [5], S=$techmap\common.pb.$and$profibus_phy_mod.v:1047$6261_Y) into $auto$simplemap.cc:420:simplemap_dff$17626 (SB_DFFE).
  Merging $auto$simplemap.cc:277:simplemap_mux$19032 (A=1'0, B=$techmap\common.pb.$procmux$12896_Y [2], S=$techmap\common.pb.$and$profibus_phy_mod.v:1047$6261_Y) into $auto$simplemap.cc:420:simplemap_dff$17623 (SB_DFFE).
  Merging $auto$simplemap.cc:277:simplemap_mux$19118 (A=1'0, B=$techmap$techmap\common.pb.$procmux$12803.$reduce_or$/home/mb/fpga-toolchain/yosys/bin/../share/yosys/techmap.v:441$19150_Y, S=$techmap\common.pb.$and$profibus_phy_mod.v:1047$6261_Y) into $auto$simplemap.cc:420:simplemap_dff$17616 (SB_DFFE).
  Merging $auto$simplemap.cc:277:simplemap_mux$19112 (A=1'0, B=$techmap$techmap\common.pb.$procmux$12803.$reduce_or$/home/mb/fpga-toolchain/yosys/bin/../share/yosys/techmap.v:441$19144_Y, S=$techmap\common.pb.$and$profibus_phy_mod.v:1047$6261_Y) into $auto$simplemap.cc:420:simplemap_dff$17610 (SB_DFFE).
  Merging $auto$simplemap.cc:277:simplemap_mux$19106 (A=1'0, B=$techmap\common.pb.$procmux$12830_Y, S=$techmap\common.pb.$and$profibus_phy_mod.v:1047$6261_Y) into $auto$simplemap.cc:420:simplemap_dff$17618 (SB_DFFE).
  Merging $auto$simplemap.cc:277:simplemap_mux$19102 (A=1'0, B=$techmap\common.pb.$procmux$12855_Y, S=$techmap\common.pb.$and$profibus_phy_mod.v:1047$6261_Y) into $auto$simplemap.cc:420:simplemap_dff$17619 (SB_DFFE).
  Merging $auto$simplemap.cc:277:simplemap_mux$19094 (A=1'0, B=$auto$simplemap.cc:168:logic_reduce$19575, S=$techmap\common.pb.$and$profibus_phy_mod.v:1047$6261_Y) into $auto$simplemap.cc:420:simplemap_dff$17620 (SB_DFFE).
  Merging $auto$simplemap.cc:277:simplemap_mux$19034 (A=1'0, B=$techmap\common.pb.$procmux$12896_Y [4], S=$techmap\common.pb.$and$profibus_phy_mod.v:1047$6261_Y) into $auto$simplemap.cc:420:simplemap_dff$17625 (SB_DFFE).
  Merging $auto$simplemap.cc:277:simplemap_mux$19033 (A=1'0, B=$techmap\common.pb.$procmux$12896_Y [3], S=$techmap\common.pb.$and$profibus_phy_mod.v:1047$6261_Y) into $auto$simplemap.cc:420:simplemap_dff$17624 (SB_DFFE).
  Merging $auto$simplemap.cc:277:simplemap_mux$19031 (A=1'0, B=$techmap\common.pb.$procmux$12896_Y [1], S=$techmap\common.pb.$and$profibus_phy_mod.v:1047$6261_Y) into $auto$simplemap.cc:420:simplemap_dff$17622 (SB_DFFE).
  Merging $auto$simplemap.cc:277:simplemap_mux$18959 (A=1'0, B=$techmap\common.pb.$procmux$12940_Y [1], S=$techmap\common.pb.$and$profibus_phy_mod.v:1047$6261_Y) into $auto$simplemap.cc:420:simplemap_dff$17630 (SB_DFFE).
  Merging $auto$simplemap.cc:277:simplemap_mux$18961 (A=1'0, B=$techmap\common.pb.$procmux$12940_Y [3], S=$techmap\common.pb.$and$profibus_phy_mod.v:1047$6261_Y) into $auto$simplemap.cc:420:simplemap_dff$17632 (SB_DFFE).
  Merging $auto$simplemap.cc:277:simplemap_mux$19037 (A=1'0, B=$techmap\common.pb.$procmux$12896_Y [7], S=$techmap\common.pb.$and$profibus_phy_mod.v:1047$6261_Y) into $auto$simplemap.cc:420:simplemap_dff$17628 (SB_DFFE).
  Merging $auto$simplemap.cc:277:simplemap_mux$18960 (A=1'0, B=$techmap\common.pb.$procmux$12940_Y [2], S=$techmap\common.pb.$and$profibus_phy_mod.v:1047$6261_Y) into $auto$simplemap.cc:420:simplemap_dff$17631 (SB_DFFE).
  Merging $auto$simplemap.cc:277:simplemap_mux$19030 (A=1'0, B=$techmap\common.pb.$procmux$12896_Y [0], S=$techmap\common.pb.$and$profibus_phy_mod.v:1047$6261_Y) into $auto$simplemap.cc:420:simplemap_dff$17621 (SB_DFFE).
  Merging $auto$simplemap.cc:277:simplemap_mux$19036 (A=1'0, B=$techmap\common.pb.$procmux$12896_Y [6], S=$techmap\common.pb.$and$profibus_phy_mod.v:1047$6261_Y) into $auto$simplemap.cc:420:simplemap_dff$17627 (SB_DFFE).
  Merging $auto$simplemap.cc:277:simplemap_mux$20918 (A=1'0, B=$techmap\common.pb.uart.tx_mod.symclk.$procmux$15655_Y [1], S=\common.pb.uart.tx_mod.symclk_n_reset) into $auto$simplemap.cc:420:simplemap_dff$21855 (SB_DFF).
  Merging $auto$simplemap.cc:277:simplemap_mux$20348 (A=1'0, B=$techmap\common.pb.uart.$procmux$14896_Y [0], S=\common.pb.n_reset) into $auto$simplemap.cc:420:simplemap_dff$20476 (SB_DFFE).
  Merging $auto$simplemap.cc:277:simplemap_mux$18965 (A=1'0, B=$techmap\common.pb.$procmux$12940_Y [7], S=$techmap\common.pb.$and$profibus_phy_mod.v:1047$6261_Y) into $auto$simplemap.cc:420:simplemap_dff$17636 (SB_DFFE).
  Merging $auto$simplemap.cc:277:simplemap_mux$18962 (A=1'0, B=$techmap\common.pb.$procmux$12940_Y [4], S=$techmap\common.pb.$and$profibus_phy_mod.v:1047$6261_Y) into $auto$simplemap.cc:420:simplemap_dff$17633 (SB_DFFE).
  Merging $auto$simplemap.cc:277:simplemap_mux$19153 (A=1'0, B=$techmap\common.pb.$2\spi_tx_data[7:0] [1], S=$techmap\common.pb.$and$profibus_phy_mod.v:1047$6261_Y) into $auto$simplemap.cc:420:simplemap_dff$17639 (SB_DFFE).
  Merging $auto$simplemap.cc:277:simplemap_mux$18958 (A=1'0, B=$techmap\common.pb.$procmux$12940_Y [0], S=$techmap\common.pb.$and$profibus_phy_mod.v:1047$6261_Y) into $auto$simplemap.cc:420:simplemap_dff$17629 (SB_DFFE).
  Merging $auto$simplemap.cc:277:simplemap_mux$20922 (A=1'0, B=$techmap\common.pb.uart.tx_mod.symclk.$procmux$15655_Y [5], S=\common.pb.uart.tx_mod.symclk_n_reset) into $auto$simplemap.cc:420:simplemap_dff$21859 (SB_DFF).
  Merging $auto$simplemap.cc:277:simplemap_mux$20152 (A=1'0, B=$techmap$techmap\common.pb.spirx_lencalc.$procmux$14747.$ternary$/home/mb/fpga-toolchain/yosys/bin/../share/yosys/techmap.v:445$18291_Y [7], S=\common.pb.spirx_lencalc.n_reset) into $auto$simplemap.cc:420:simplemap_dff$20069 (SB_DFF).
  Merging $auto$simplemap.cc:277:simplemap_mux$19156 (A=1'0, B=$techmap\common.pb.$2\spi_tx_data[7:0] [4], S=$techmap\common.pb.$and$profibus_phy_mod.v:1047$6261_Y) into $auto$simplemap.cc:420:simplemap_dff$17642 (SB_DFFE).
  Merging $auto$simplemap.cc:277:simplemap_mux$19158 (A=1'0, B=$techmap\common.pb.$2\spi_tx_data[7:0] [6], S=$techmap\common.pb.$and$profibus_phy_mod.v:1047$6261_Y) into $auto$simplemap.cc:420:simplemap_dff$17644 (SB_DFFE).
  Merging $auto$simplemap.cc:277:simplemap_mux$19159 (A=1'0, B=$techmap\common.pb.$2\spi_tx_data[7:0] [7], S=$techmap\common.pb.$and$profibus_phy_mod.v:1047$6261_Y) into $auto$simplemap.cc:420:simplemap_dff$17645 (SB_DFFE).
  Merging $auto$simplemap.cc:277:simplemap_mux$18964 (A=1'0, B=$techmap\common.pb.$procmux$12940_Y [6], S=$techmap\common.pb.$and$profibus_phy_mod.v:1047$6261_Y) into $auto$simplemap.cc:420:simplemap_dff$17635 (SB_DFFE).
  Merging $auto$simplemap.cc:277:simplemap_mux$19152 (A=1'0, B=$techmap\common.pb.$2\spi_tx_data[7:0] [0], S=$techmap\common.pb.$and$profibus_phy_mod.v:1047$6261_Y) into $auto$simplemap.cc:420:simplemap_dff$17638 (SB_DFFE).
  Merging $auto$simplemap.cc:277:simplemap_mux$19157 (A=1'0, B=$techmap\common.pb.$2\spi_tx_data[7:0] [5], S=$techmap\common.pb.$and$profibus_phy_mod.v:1047$6261_Y) into $auto$simplemap.cc:420:simplemap_dff$17643 (SB_DFFE).
  Merging $auto$simplemap.cc:277:simplemap_mux$19353 (A=1'0, B=$techmap\common.pb.$procmux$9310_Y [1], S=$techmap\common.pb.$and$profibus_phy_mod.v:1047$6261_Y) into $auto$simplemap.cc:420:simplemap_dff$17679 (SB_DFFE).
  Merging $auto$simplemap.cc:277:simplemap_mux$19354 (A=1'0, B=$techmap\common.pb.$procmux$9310_Y [2], S=$techmap\common.pb.$and$profibus_phy_mod.v:1047$6261_Y) into $auto$simplemap.cc:420:simplemap_dff$17680 (SB_DFFE).
  Merging $auto$simplemap.cc:277:simplemap_mux$19355 (A=1'0, B=$techmap\common.pb.$procmux$9310_Y [3], S=$techmap\common.pb.$and$profibus_phy_mod.v:1047$6261_Y) into $auto$simplemap.cc:420:simplemap_dff$17681 (SB_DFFE).
  Merging $auto$simplemap.cc:277:simplemap_mux$19356 (A=1'0, B=$techmap\common.pb.$procmux$9310_Y [4], S=$techmap\common.pb.$and$profibus_phy_mod.v:1047$6261_Y) into $auto$simplemap.cc:420:simplemap_dff$17682 (SB_DFFE).
  Merging $auto$simplemap.cc:277:simplemap_mux$19357 (A=1'0, B=$techmap\common.pb.$procmux$9310_Y [5], S=$techmap\common.pb.$and$profibus_phy_mod.v:1047$6261_Y) into $auto$simplemap.cc:420:simplemap_dff$17683 (SB_DFFE).
  Merging $auto$simplemap.cc:277:simplemap_mux$19358 (A=1'0, B=$techmap\common.pb.$procmux$9310_Y [6], S=$techmap\common.pb.$and$profibus_phy_mod.v:1047$6261_Y) into $auto$simplemap.cc:420:simplemap_dff$17684 (SB_DFFE).
  Merging $auto$simplemap.cc:277:simplemap_mux$19359 (A=1'0, B=$techmap\common.pb.$procmux$9310_Y [7], S=$techmap\common.pb.$and$profibus_phy_mod.v:1047$6261_Y) into $auto$simplemap.cc:420:simplemap_dff$17685 (SB_DFFE).
  Merging $auto$simplemap.cc:277:simplemap_mux$19360 (A=1'0, B=$techmap\common.pb.$procmux$9310_Y [8], S=$techmap\common.pb.$and$profibus_phy_mod.v:1047$6261_Y) into $auto$simplemap.cc:420:simplemap_dff$17686 (SB_DFFE).
  Merging $auto$simplemap.cc:277:simplemap_mux$19361 (A=1'0, B=$techmap\common.pb.$procmux$9310_Y [9], S=$techmap\common.pb.$and$profibus_phy_mod.v:1047$6261_Y) into $auto$simplemap.cc:420:simplemap_dff$17687 (SB_DFFE).
  Merging $auto$simplemap.cc:277:simplemap_mux$19362 (A=1'0, B=$techmap\common.pb.$procmux$9310_Y [10], S=$techmap\common.pb.$and$profibus_phy_mod.v:1047$6261_Y) into $auto$simplemap.cc:420:simplemap_dff$17688 (SB_DFFE).
  Merging $auto$simplemap.cc:277:simplemap_mux$19363 (A=1'0, B=$techmap\common.pb.$procmux$9310_Y [11], S=$techmap\common.pb.$and$profibus_phy_mod.v:1047$6261_Y) into $auto$simplemap.cc:420:simplemap_dff$17689 (SB_DFFE).
  Merging $auto$simplemap.cc:277:simplemap_mux$19364 (A=1'0, B=$techmap\common.pb.$procmux$9310_Y [12], S=$techmap\common.pb.$and$profibus_phy_mod.v:1047$6261_Y) into $auto$simplemap.cc:420:simplemap_dff$17690 (SB_DFFE).
  Merging $auto$simplemap.cc:277:simplemap_mux$19365 (A=1'0, B=$techmap\common.pb.$procmux$9310_Y [13], S=$techmap\common.pb.$and$profibus_phy_mod.v:1047$6261_Y) into $auto$simplemap.cc:420:simplemap_dff$17691 (SB_DFFE).
  Merging $auto$simplemap.cc:277:simplemap_mux$19366 (A=1'0, B=$techmap\common.pb.$procmux$9310_Y [14], S=$techmap\common.pb.$and$profibus_phy_mod.v:1047$6261_Y) into $auto$simplemap.cc:420:simplemap_dff$17692 (SB_DFFE).
  Merging $auto$simplemap.cc:277:simplemap_mux$19367 (A=1'0, B=$techmap\common.pb.$procmux$9310_Y [15], S=$techmap\common.pb.$and$profibus_phy_mod.v:1047$6261_Y) into $auto$simplemap.cc:420:simplemap_dff$17693 (SB_DFFE).
  Merging $auto$simplemap.cc:277:simplemap_mux$19368 (A=1'0, B=$techmap\common.pb.$procmux$9310_Y [16], S=$techmap\common.pb.$and$profibus_phy_mod.v:1047$6261_Y) into $auto$simplemap.cc:420:simplemap_dff$17694 (SB_DFFE).
  Merging $auto$simplemap.cc:277:simplemap_mux$19369 (A=1'0, B=$techmap\common.pb.$procmux$9310_Y [17], S=$techmap\common.pb.$and$profibus_phy_mod.v:1047$6261_Y) into $auto$simplemap.cc:420:simplemap_dff$17695 (SB_DFFE).
  Merging $auto$simplemap.cc:277:simplemap_mux$19370 (A=1'0, B=$techmap\common.pb.$procmux$9310_Y [18], S=$techmap\common.pb.$and$profibus_phy_mod.v:1047$6261_Y) into $auto$simplemap.cc:420:simplemap_dff$17696 (SB_DFFE).
  Merging $auto$simplemap.cc:277:simplemap_mux$19371 (A=1'0, B=$techmap\common.pb.$procmux$9310_Y [19], S=$techmap\common.pb.$and$profibus_phy_mod.v:1047$6261_Y) into $auto$simplemap.cc:420:simplemap_dff$17697 (SB_DFFE).
  Merging $auto$simplemap.cc:277:simplemap_mux$19372 (A=1'0, B=$techmap\common.pb.$procmux$9310_Y [20], S=$techmap\common.pb.$and$profibus_phy_mod.v:1047$6261_Y) into $auto$simplemap.cc:420:simplemap_dff$17698 (SB_DFFE).
  Merging $auto$simplemap.cc:277:simplemap_mux$19373 (A=1'0, B=$techmap\common.pb.$procmux$9310_Y [21], S=$techmap\common.pb.$and$profibus_phy_mod.v:1047$6261_Y) into $auto$simplemap.cc:420:simplemap_dff$17699 (SB_DFFE).
  Merging $auto$simplemap.cc:277:simplemap_mux$19374 (A=1'0, B=$techmap\common.pb.$procmux$9310_Y [22], S=$techmap\common.pb.$and$profibus_phy_mod.v:1047$6261_Y) into $auto$simplemap.cc:420:simplemap_dff$17700 (SB_DFFE).
  Merging $auto$simplemap.cc:277:simplemap_mux$19375 (A=1'0, B=$techmap\common.pb.$procmux$9310_Y [23], S=$techmap\common.pb.$and$profibus_phy_mod.v:1047$6261_Y) into $auto$simplemap.cc:420:simplemap_dff$17701 (SB_DFFE).
  Merging $auto$simplemap.cc:277:simplemap_mux$20924 (A=1'0, B=$techmap\common.pb.uart.tx_mod.symclk.$procmux$15655_Y [7], S=\common.pb.uart.tx_mod.symclk_n_reset) into $auto$simplemap.cc:420:simplemap_dff$21861 (SB_DFF).
  Merging $auto$simplemap.cc:277:simplemap_mux$19352 (A=1'0, B=$techmap\common.pb.$procmux$9310_Y [0], S=$techmap\common.pb.$and$profibus_phy_mod.v:1047$6261_Y) into $auto$simplemap.cc:420:simplemap_dff$17678 (SB_DFFE).
  Merging $auto$simplemap.cc:277:simplemap_mux$20599 (A=1'0, B=$techmap\common.pb.uart.tx_mod.$procmux$15565_Y, S=\common.pb.uart.tx_n_reset) into $auto$simplemap.cc:420:simplemap_dff$20539 (SB_DFFE).
  Merging $auto$simplemap.cc:277:simplemap_mux$20126 (A=1'0, B=$techmap$techmap\common.pb.spirx_lencalc.$procmux$14776.$ternary$/home/mb/fpga-toolchain/yosys/bin/../share/yosys/techmap.v:445$20137_Y [1], S=\common.pb.spirx_lencalc.n_reset) into $auto$simplemap.cc:420:simplemap_dff$20071 (SB_DFF).
  Merging $auto$simplemap.cc:277:simplemap_mux$20146 (A=1'0, B=$techmap$techmap\common.pb.spirx_lencalc.$procmux$14747.$ternary$/home/mb/fpga-toolchain/yosys/bin/../share/yosys/techmap.v:445$18291_Y [1], S=\common.pb.spirx_lencalc.n_reset) into $auto$simplemap.cc:420:simplemap_dff$20063 (SB_DFF).
  Merging $auto$simplemap.cc:277:simplemap_mux$20147 (A=1'0, B=$techmap$techmap\common.pb.spirx_lencalc.$procmux$14747.$ternary$/home/mb/fpga-toolchain/yosys/bin/../share/yosys/techmap.v:445$18291_Y [2], S=\common.pb.spirx_lencalc.n_reset) into $auto$simplemap.cc:420:simplemap_dff$20064 (SB_DFF).
  Merging $auto$simplemap.cc:277:simplemap_mux$20148 (A=1'0, B=$techmap$techmap\common.pb.spirx_lencalc.$procmux$14747.$ternary$/home/mb/fpga-toolchain/yosys/bin/../share/yosys/techmap.v:445$18291_Y [3], S=\common.pb.spirx_lencalc.n_reset) into $auto$simplemap.cc:420:simplemap_dff$20065 (SB_DFF).
  Merging $auto$simplemap.cc:277:simplemap_mux$20149 (A=1'0, B=$techmap$techmap\common.pb.spirx_lencalc.$procmux$14747.$ternary$/home/mb/fpga-toolchain/yosys/bin/../share/yosys/techmap.v:445$18291_Y [4], S=\common.pb.spirx_lencalc.n_reset) into $auto$simplemap.cc:420:simplemap_dff$20066 (SB_DFF).
  Merging $auto$simplemap.cc:277:simplemap_mux$20150 (A=1'0, B=$techmap$techmap\common.pb.spirx_lencalc.$procmux$14747.$ternary$/home/mb/fpga-toolchain/yosys/bin/../share/yosys/techmap.v:445$18291_Y [5], S=\common.pb.spirx_lencalc.n_reset) into $auto$simplemap.cc:420:simplemap_dff$20067 (SB_DFF).
  Merging $auto$simplemap.cc:277:simplemap_mux$20926 (A=1'0, B=$techmap\common.pb.uart.tx_mod.symclk.$procmux$15655_Y [9], S=\common.pb.uart.tx_mod.symclk_n_reset) into $auto$simplemap.cc:420:simplemap_dff$21863 (SB_DFF).
  Merging $auto$simplemap.cc:277:simplemap_mux$20145 (A=1'0, B=$techmap$techmap\common.pb.spirx_lencalc.$procmux$14747.$ternary$/home/mb/fpga-toolchain/yosys/bin/../share/yosys/techmap.v:445$18291_Y [0], S=\common.pb.spirx_lencalc.n_reset) into $auto$simplemap.cc:420:simplemap_dff$20062 (SB_DFF).
  Merging $auto$simplemap.cc:277:simplemap_mux$20102 (A=1'0, B=$techmap$techmap\common.pb.spirx_lencalc.$procmux$14797.$ternary$/home/mb/fpga-toolchain/yosys/bin/../share/yosys/techmap.v:445$17894_Y [1], S=\common.pb.spirx_lencalc.n_reset) into $auto$simplemap.cc:420:simplemap_dff$20073 (SB_DFF).
  Merging $auto$simplemap.cc:277:simplemap_mux$20125 (A=1'0, B=$techmap$techmap\common.pb.spirx_lencalc.$procmux$14776.$ternary$/home/mb/fpga-toolchain/yosys/bin/../share/yosys/techmap.v:445$20137_Y [0], S=\common.pb.spirx_lencalc.n_reset) into $auto$simplemap.cc:420:simplemap_dff$20070 (SB_DFF).
  Merging $auto$simplemap.cc:277:simplemap_mux$20103 (A=1'0, B=$techmap$techmap\common.pb.spirx_lencalc.$procmux$14797.$ternary$/home/mb/fpga-toolchain/yosys/bin/../share/yosys/techmap.v:445$17894_Y [2], S=\common.pb.spirx_lencalc.n_reset) into $auto$simplemap.cc:420:simplemap_dff$20074 (SB_DFF).
  Merging $auto$simplemap.cc:277:simplemap_mux$20104 (A=1'0, B=$techmap$techmap\common.pb.spirx_lencalc.$procmux$14797.$ternary$/home/mb/fpga-toolchain/yosys/bin/../share/yosys/techmap.v:445$17894_Y [3], S=\common.pb.spirx_lencalc.n_reset) into $auto$simplemap.cc:420:simplemap_dff$20075 (SB_DFF).
  Merging $auto$simplemap.cc:277:simplemap_mux$20105 (A=1'0, B=$techmap$techmap\common.pb.spirx_lencalc.$procmux$14797.$ternary$/home/mb/fpga-toolchain/yosys/bin/../share/yosys/techmap.v:445$17894_Y [4], S=\common.pb.spirx_lencalc.n_reset) into $auto$simplemap.cc:420:simplemap_dff$20076 (SB_DFF).
  Merging $auto$simplemap.cc:277:simplemap_mux$20106 (A=1'0, B=$techmap$techmap\common.pb.spirx_lencalc.$procmux$14797.$ternary$/home/mb/fpga-toolchain/yosys/bin/../share/yosys/techmap.v:445$17894_Y [5], S=\common.pb.spirx_lencalc.n_reset) into $auto$simplemap.cc:420:simplemap_dff$20077 (SB_DFF).
  Merging $auto$simplemap.cc:277:simplemap_mux$20107 (A=1'0, B=$techmap$techmap\common.pb.spirx_lencalc.$procmux$14797.$ternary$/home/mb/fpga-toolchain/yosys/bin/../share/yosys/techmap.v:445$17894_Y [6], S=\common.pb.spirx_lencalc.n_reset) into $auto$simplemap.cc:420:simplemap_dff$20078 (SB_DFF).
  Merging $auto$simplemap.cc:277:simplemap_mux$20108 (A=1'0, B=$techmap$techmap\common.pb.spirx_lencalc.$procmux$14797.$ternary$/home/mb/fpga-toolchain/yosys/bin/../share/yosys/techmap.v:445$17894_Y [7], S=\common.pb.spirx_lencalc.n_reset) into $auto$simplemap.cc:420:simplemap_dff$20079 (SB_DFF).
  Merging $auto$simplemap.cc:277:simplemap_mux$20433 (A=$techmap\common.pb.spi.$procmux$14923_Y [1], B=1'0, S=\common.pb.spi.sync_ss.shiftreg [1]) into $auto$simplemap.cc:420:simplemap_dff$20358 (SB_DFFE).
  Merging $auto$simplemap.cc:277:simplemap_mux$20101 (A=1'0, B=$techmap$techmap\common.pb.spirx_lencalc.$procmux$14797.$ternary$/home/mb/fpga-toolchain/yosys/bin/../share/yosys/techmap.v:445$17894_Y [0], S=\common.pb.spirx_lencalc.n_reset) into $auto$simplemap.cc:420:simplemap_dff$20072 (SB_DFF).
  Merging $auto$simplemap.cc:277:simplemap_mux$20090 (A=1'0, B=$techmap$techmap\common.pb.spirx_lencalc.$procmux$14815.$ternary$/home/mb/fpga-toolchain/yosys/bin/../share/yosys/techmap.v:445$18549_Y, S=\common.pb.spirx_lencalc.n_reset) into $auto$simplemap.cc:420:simplemap_dff$20080 (SB_DFF).
  Merging $auto$simplemap.cc:277:simplemap_mux$20082 (A=1'0, B=$techmap$techmap\common.pb.spirx_lencalc.$procmux$14850.$ternary$/home/mb/fpga-toolchain/yosys/bin/../share/yosys/techmap.v:445$18549_Y, S=\common.pb.spirx_lencalc.n_reset) into $auto$simplemap.cc:420:simplemap_dff$20081 (SB_DFF).
  Merging $auto$simplemap.cc:277:simplemap_mux$20407 (A=$auto$rtlil.cc:1836:ReduceOr$16042, B=1'0, S=\common.pb.spi.sync_ss.shiftreg [1]) into $auto$simplemap.cc:420:simplemap_dff$20356 (SB_DFF).
  Merging $auto$simplemap.cc:277:simplemap_mux$20434 (A=$techmap\common.pb.spi.$procmux$14923_Y [2], B=1'0, S=\common.pb.spi.sync_ss.shiftreg [1]) into $auto$simplemap.cc:420:simplemap_dff$20359 (SB_DFFE).
  Merging $auto$simplemap.cc:277:simplemap_mux$20435 (A=$techmap\common.pb.spi.$procmux$14923_Y [3], B=1'0, S=\common.pb.spi.sync_ss.shiftreg [1]) into $auto$simplemap.cc:420:simplemap_dff$20360 (SB_DFFE).
  Merging $auto$simplemap.cc:277:simplemap_mux$20436 (A=$techmap\common.pb.spi.$procmux$14923_Y [4], B=1'0, S=\common.pb.spi.sync_ss.shiftreg [1]) into $auto$simplemap.cc:420:simplemap_dff$20361 (SB_DFFE).
  Merging $auto$simplemap.cc:277:simplemap_mux$20437 (A=$techmap\common.pb.spi.$procmux$14923_Y [5], B=1'0, S=\common.pb.spi.sync_ss.shiftreg [1]) into $auto$simplemap.cc:420:simplemap_dff$20362 (SB_DFFE).
  Merging $auto$simplemap.cc:277:simplemap_mux$20409 (A=$techmap\common.pb.spi.$procmux$14931_Y [1], B=1'0, S=\common.pb.spi.sync_ss.shiftreg [1]) into $auto$simplemap.cc:420:simplemap_dff$20364 (SB_DFFE).
  Merging $auto$simplemap.cc:277:simplemap_mux$20432 (A=$techmap\common.pb.spi.$procmux$14923_Y [0], B=1'0, S=\common.pb.spi.sync_ss.shiftreg [1]) into $auto$simplemap.cc:420:simplemap_dff$20357 (SB_DFFE).
  Merging $auto$simplemap.cc:277:simplemap_mux$20410 (A=$techmap\common.pb.spi.$procmux$14931_Y [2], B=1'0, S=\common.pb.spi.sync_ss.shiftreg [1]) into $auto$simplemap.cc:420:simplemap_dff$20365 (SB_DFFE).
  Merging $auto$simplemap.cc:277:simplemap_mux$20411 (A=$techmap\common.pb.spi.$procmux$14931_Y [3], B=1'0, S=\common.pb.spi.sync_ss.shiftreg [1]) into $auto$simplemap.cc:420:simplemap_dff$20366 (SB_DFFE).
  Merging $auto$simplemap.cc:277:simplemap_mux$20412 (A=$techmap\common.pb.spi.$procmux$14931_Y [4], B=1'0, S=\common.pb.spi.sync_ss.shiftreg [1]) into $auto$simplemap.cc:420:simplemap_dff$20367 (SB_DFFE).
  Merging $auto$simplemap.cc:277:simplemap_mux$20413 (A=$techmap\common.pb.spi.$procmux$14931_Y [5], B=1'0, S=\common.pb.spi.sync_ss.shiftreg [1]) into $auto$simplemap.cc:420:simplemap_dff$20368 (SB_DFFE).
  Merging $auto$simplemap.cc:277:simplemap_mux$20414 (A=$techmap\common.pb.spi.$procmux$14931_Y [6], B=1'0, S=\common.pb.spi.sync_ss.shiftreg [1]) into $auto$simplemap.cc:420:simplemap_dff$20369 (SB_DFFE).
  Merging $auto$simplemap.cc:277:simplemap_mux$20415 (A=$techmap\common.pb.spi.$procmux$14931_Y [7], B=1'0, S=\common.pb.spi.sync_ss.shiftreg [1]) into $auto$simplemap.cc:420:simplemap_dff$20370 (SB_DFFE).
  Merging $auto$simplemap.cc:277:simplemap_mux$20452 (A=\common.pb.spi.rx_shiftreg [0], B=1'0, S=\common.pb.spi.sync_ss.shiftreg [1]) into $auto$simplemap.cc:420:simplemap_dff$20372 (SB_DFFE).
  Merging $auto$simplemap.cc:277:simplemap_mux$20453 (A=\common.pb.spi.rx_shiftreg [1], B=1'0, S=\common.pb.spi.sync_ss.shiftreg [1]) into $auto$simplemap.cc:420:simplemap_dff$20373 (SB_DFFE).
  Merging $auto$simplemap.cc:277:simplemap_mux$20454 (A=\common.pb.spi.rx_shiftreg [2], B=1'0, S=\common.pb.spi.sync_ss.shiftreg [1]) into $auto$simplemap.cc:420:simplemap_dff$20374 (SB_DFFE).
  Merging $auto$simplemap.cc:277:simplemap_mux$20455 (A=\common.pb.spi.rx_shiftreg [3], B=1'0, S=\common.pb.spi.sync_ss.shiftreg [1]) into $auto$simplemap.cc:420:simplemap_dff$20375 (SB_DFFE).
  Merging $auto$simplemap.cc:277:simplemap_mux$20456 (A=\common.pb.spi.rx_shiftreg [4], B=1'0, S=\common.pb.spi.sync_ss.shiftreg [1]) into $auto$simplemap.cc:420:simplemap_dff$20376 (SB_DFFE).
  Merging $auto$simplemap.cc:277:simplemap_mux$20457 (A=\common.pb.spi.rx_shiftreg [5], B=1'0, S=\common.pb.spi.sync_ss.shiftreg [1]) into $auto$simplemap.cc:420:simplemap_dff$20377 (SB_DFFE).
  Merging $auto$simplemap.cc:277:simplemap_mux$20458 (A=\common.pb.spi.rx_shiftreg [6], B=1'0, S=\common.pb.spi.sync_ss.shiftreg [1]) into $auto$simplemap.cc:420:simplemap_dff$20378 (SB_DFFE).
  Merging $auto$simplemap.cc:277:simplemap_mux$20450 (A=\common.pb.spi.sync_mosi.shiftreg [1], B=1'0, S=\common.pb.spi.sync_ss.shiftreg [1]) into $auto$simplemap.cc:420:simplemap_dff$20371 (SB_DFFE).
  Merging $auto$simplemap.cc:277:simplemap_mux$20349 (A=1'0, B=$techmap\common.pb.uart.$procmux$14896_Y [1], S=\common.pb.n_reset) into $auto$simplemap.cc:420:simplemap_dff$20477 (SB_DFFE).
  Merging $auto$simplemap.cc:277:simplemap_mux$20388 (A=$techmap\common.pb.spi.$procmux$14951_Y, B=1'0, S=\common.pb.spi.sync_ss.shiftreg [1]) into $auto$simplemap.cc:420:simplemap_dff$20387 (SB_DFFE).
  Merging $auto$simplemap.cc:277:simplemap_mux$20350 (A=1'0, B=$techmap\common.pb.uart.$procmux$14896_Y [2], S=\common.pb.n_reset) into $auto$simplemap.cc:420:simplemap_dff$20478 (SB_DFFE).
  Merging $auto$simplemap.cc:277:simplemap_mux$20351 (A=1'0, B=$techmap\common.pb.uart.$procmux$14896_Y [3], S=\common.pb.n_reset) into $auto$simplemap.cc:420:simplemap_dff$20479 (SB_DFFE).
  Merging $auto$simplemap.cc:277:simplemap_mux$20352 (A=1'0, B=$techmap\common.pb.uart.$procmux$14896_Y [4], S=\common.pb.n_reset) into $auto$simplemap.cc:420:simplemap_dff$20480 (SB_DFFE).
  Merging $auto$simplemap.cc:277:simplemap_mux$20353 (A=1'0, B=$techmap\common.pb.uart.$procmux$14896_Y [5], S=\common.pb.n_reset) into $auto$simplemap.cc:420:simplemap_dff$20481 (SB_DFFE).
  Merging $auto$simplemap.cc:277:simplemap_mux$20354 (A=1'0, B=$techmap\common.pb.uart.$procmux$14896_Y [6], S=\common.pb.n_reset) into $auto$simplemap.cc:420:simplemap_dff$20482 (SB_DFFE).
  Merging $auto$simplemap.cc:277:simplemap_mux$20355 (A=1'0, B=$techmap\common.pb.uart.$procmux$14896_Y [7], S=\common.pb.n_reset) into $auto$simplemap.cc:420:simplemap_dff$20483 (SB_DFFE).
  Merging $auto$simplemap.cc:277:simplemap_mux$19117 (A=1'0, B=$techmap$techmap\common.pb.$procmux$12803.$reduce_or$/home/mb/fpga-toolchain/yosys/bin/../share/yosys/techmap.v:441$19149_Y, S=$techmap\common.pb.$and$profibus_phy_mod.v:1047$6261_Y) into $auto$simplemap.cc:420:simplemap_dff$17615 (SB_DFFE).
  Merging $auto$simplemap.cc:277:simplemap_mux$19154 (A=1'0, B=$techmap\common.pb.$2\spi_tx_data[7:0] [2], S=$techmap\common.pb.$and$profibus_phy_mod.v:1047$6261_Y) into $auto$simplemap.cc:420:simplemap_dff$17640 (SB_DFFE).
  Merging $auto$simplemap.cc:277:simplemap_mux$20556 (A=1'0, B=$techmap\common.pb.uart.tx_mod.$procmux$15610_Y [1], S=\common.pb.uart.tx_n_reset) into $auto$simplemap.cc:420:simplemap_dff$20552 (SB_DFFE).
  Merging $auto$simplemap.cc:277:simplemap_mux$20608 (A=1'0, B=$techmap\common.pb.uart.tx_mod.$procmux$15532_Y, S=\common.pb.uart.tx_n_reset) into $auto$simplemap.cc:420:simplemap_dff$20550 (SB_DFFE).
  Merging $auto$simplemap.cc:277:simplemap_mux$20557 (A=1'0, B=$techmap\common.pb.uart.tx_mod.$procmux$15610_Y [2], S=\common.pb.uart.tx_n_reset) into $auto$simplemap.cc:420:simplemap_dff$20553 (SB_DFFE).
  Merging $auto$simplemap.cc:277:simplemap_mux$20558 (A=1'0, B=$techmap\common.pb.uart.tx_mod.$procmux$15610_Y [3], S=\common.pb.uart.tx_n_reset) into $auto$simplemap.cc:420:simplemap_dff$20554 (SB_DFFE).
  Merging $auto$simplemap.cc:277:simplemap_mux$21119 (A=1'0, B=\common.pb.uart.sync_rx.shiftreg [1], S=$auto$simplemap.cc:168:logic_reduce$21824) into $auto$simplemap.cc:420:simplemap_dff$20945 (SB_DFFE).
  Merging $auto$simplemap.cc:277:simplemap_mux$21096 (A=1'0, B=$techmap\common.pb.uart.rx_mod.$procmux$15256_Y, S=\common.pb.uart.rx_mod.n_reset) into $auto$simplemap.cc:420:simplemap_dff$20941 (SB_DFFE).
  Merging $auto$simplemap.cc:277:simplemap_mux$21120 (A=1'0, B=\common.pb.uart.sync_rx.shiftreg [1], S=$auto$simplemap.cc:168:logic_reduce$21824) into $auto$simplemap.cc:420:simplemap_dff$20946 (SB_DFFE).
  Merging $auto$simplemap.cc:277:simplemap_mux$21121 (A=1'0, B=\common.pb.uart.sync_rx.shiftreg [1], S=$auto$simplemap.cc:168:logic_reduce$21824) into $auto$simplemap.cc:420:simplemap_dff$20947 (SB_DFFE).
  Merging $auto$simplemap.cc:277:simplemap_mux$21122 (A=1'0, B=\common.pb.uart.sync_rx.shiftreg [1], S=$auto$simplemap.cc:168:logic_reduce$21824) into $auto$simplemap.cc:420:simplemap_dff$20948 (SB_DFFE).
  Merging $auto$simplemap.cc:277:simplemap_mux$21123 (A=1'0, B=\common.pb.uart.sync_rx.shiftreg [1], S=$auto$simplemap.cc:168:logic_reduce$21824) into $auto$simplemap.cc:420:simplemap_dff$20949 (SB_DFFE).
  Merging $auto$simplemap.cc:277:simplemap_mux$21124 (A=1'0, B=\common.pb.uart.sync_rx.shiftreg [1], S=$auto$simplemap.cc:168:logic_reduce$21824) into $auto$simplemap.cc:420:simplemap_dff$20950 (SB_DFFE).
  Merging $auto$simplemap.cc:277:simplemap_mux$21125 (A=1'0, B=\common.pb.uart.sync_rx.shiftreg [1], S=$auto$simplemap.cc:168:logic_reduce$21824) into $auto$simplemap.cc:420:simplemap_dff$20951 (SB_DFFE).
  Merging $auto$simplemap.cc:277:simplemap_mux$21053 (A=1'0, B=$techmap\common.pb.uart.rx_mod.$procmux$15305_Y [1], S=\common.pb.uart.rx_mod.n_reset) into $auto$simplemap.cc:420:simplemap_dff$20953 (SB_DFFE).
  Merging $auto$simplemap.cc:277:simplemap_mux$21118 (A=1'0, B=\common.pb.uart.sync_rx.shiftreg [1], S=$auto$simplemap.cc:168:logic_reduce$21824) into $auto$simplemap.cc:420:simplemap_dff$20944 (SB_DFFE).
  Merging $auto$simplemap.cc:277:simplemap_mux$21054 (A=1'0, B=$techmap\common.pb.uart.rx_mod.$procmux$15305_Y [2], S=\common.pb.uart.rx_mod.n_reset) into $auto$simplemap.cc:420:simplemap_dff$20954 (SB_DFFE).
  Merging $auto$simplemap.cc:277:simplemap_mux$21055 (A=1'0, B=$techmap\common.pb.uart.rx_mod.$procmux$15305_Y [3], S=\common.pb.uart.rx_mod.n_reset) into $auto$simplemap.cc:420:simplemap_dff$20955 (SB_DFFE).
  Merging $auto$simplemap.cc:277:simplemap_mux$21052 (A=1'0, B=$techmap\common.pb.uart.rx_mod.$procmux$15305_Y [0], S=\common.pb.uart.rx_mod.n_reset) into $auto$simplemap.cc:420:simplemap_dff$20952 (SB_DFFE).
  Merging $auto$simplemap.cc:277:simplemap_mux$16321 (A=1'0, B=$techmap\common.led_blink.$procmux$9274_Y [0], S=\common.pb.n_reset) into $auto$simplemap.cc:420:simplemap_dff$16285 (SB_DFFE).
  Merging $auto$simplemap.cc:277:simplemap_mux$20967 (A=1'0, B=$techmap\common.pb.uart.rx_mod.$procmux$15407_Y, S=\common.pb.uart.rx_mod.n_reset) into $auto$simplemap.cc:420:simplemap_dff$20966 (SB_DFFE).
  Merging $auto$simplemap.cc:277:simplemap_mux$21951 (A=1'0, B=$techmap\common.pb.uart.tx_mod.symclk.$eq$uart_mod.v:73$17_Y, S=\common.pb.uart.tx_mod.symclk_n_reset) into $auto$simplemap.cc:420:simplemap_dff$21853 (SB_DFF).
  Merging $auto$simplemap.cc:277:simplemap_mux$20919 (A=1'0, B=$techmap\common.pb.uart.tx_mod.symclk.$procmux$15655_Y [2], S=\common.pb.uart.tx_mod.symclk_n_reset) into $auto$simplemap.cc:420:simplemap_dff$21856 (SB_DFF).
  Merging $auto$simplemap.cc:277:simplemap_mux$20920 (A=1'0, B=$techmap\common.pb.uart.tx_mod.symclk.$procmux$15655_Y [3], S=\common.pb.uart.tx_mod.symclk_n_reset) into $auto$simplemap.cc:420:simplemap_dff$21857 (SB_DFF).
  Merging $auto$simplemap.cc:277:simplemap_mux$20921 (A=1'0, B=$techmap\common.pb.uart.tx_mod.symclk.$procmux$15655_Y [4], S=\common.pb.uart.tx_mod.symclk_n_reset) into $auto$simplemap.cc:420:simplemap_dff$21858 (SB_DFF).
  Merging $auto$simplemap.cc:277:simplemap_mux$18963 (A=1'0, B=$techmap\common.pb.$procmux$12940_Y [5], S=$techmap\common.pb.$and$profibus_phy_mod.v:1047$6261_Y) into $auto$simplemap.cc:420:simplemap_dff$17634 (SB_DFFE).
  Merging $auto$simplemap.cc:277:simplemap_mux$16352 (A=1'0, B=$techmap\common.led_blink.$procmux$9274_Y [31], S=\common.pb.n_reset) into $auto$simplemap.cc:420:simplemap_dff$16316 (SB_DFFE).
  Merging $auto$simplemap.cc:277:simplemap_mux$19155 (A=1'0, B=$techmap\common.pb.$2\spi_tx_data[7:0] [3], S=$techmap\common.pb.$and$profibus_phy_mod.v:1047$6261_Y) into $auto$simplemap.cc:420:simplemap_dff$17641 (SB_DFFE).
  Merging $auto$simplemap.cc:277:simplemap_mux$20925 (A=1'0, B=$techmap\common.pb.uart.tx_mod.symclk.$procmux$15655_Y [8], S=\common.pb.uart.tx_mod.symclk_n_reset) into $auto$simplemap.cc:420:simplemap_dff$21862 (SB_DFF).
  Merging $auto$simplemap.cc:277:simplemap_mux$20927 (A=1'0, B=$techmap\common.pb.uart.tx_mod.symclk.$procmux$15655_Y [10], S=\common.pb.uart.tx_mod.symclk_n_reset) into $auto$simplemap.cc:420:simplemap_dff$21864 (SB_DFF).
  Merging $auto$simplemap.cc:277:simplemap_mux$20928 (A=1'0, B=$techmap\common.pb.uart.tx_mod.symclk.$procmux$15655_Y [11], S=\common.pb.uart.tx_mod.symclk_n_reset) into $auto$simplemap.cc:420:simplemap_dff$21865 (SB_DFF).
  Merging $auto$simplemap.cc:277:simplemap_mux$20929 (A=1'0, B=$techmap\common.pb.uart.tx_mod.symclk.$procmux$15655_Y [12], S=\common.pb.uart.tx_mod.symclk_n_reset) into $auto$simplemap.cc:420:simplemap_dff$21866 (SB_DFF).
  Merging $auto$simplemap.cc:277:simplemap_mux$20930 (A=1'0, B=$techmap\common.pb.uart.tx_mod.symclk.$procmux$15655_Y [13], S=\common.pb.uart.tx_mod.symclk_n_reset) into $auto$simplemap.cc:420:simplemap_dff$21867 (SB_DFF).
  Merging $auto$simplemap.cc:277:simplemap_mux$20931 (A=1'0, B=$techmap\common.pb.uart.tx_mod.symclk.$procmux$15655_Y [14], S=\common.pb.uart.tx_mod.symclk_n_reset) into $auto$simplemap.cc:420:simplemap_dff$21868 (SB_DFF).
  Merging $auto$simplemap.cc:277:simplemap_mux$20932 (A=1'0, B=$techmap\common.pb.uart.tx_mod.symclk.$procmux$15655_Y [15], S=\common.pb.uart.tx_mod.symclk_n_reset) into $auto$simplemap.cc:420:simplemap_dff$21869 (SB_DFF).
  Merging $auto$simplemap.cc:277:simplemap_mux$20933 (A=1'0, B=$techmap\common.pb.uart.tx_mod.symclk.$procmux$15655_Y [16], S=\common.pb.uart.tx_mod.symclk_n_reset) into $auto$simplemap.cc:420:simplemap_dff$21870 (SB_DFF).
  Merging $auto$simplemap.cc:277:simplemap_mux$20934 (A=1'0, B=$techmap\common.pb.uart.tx_mod.symclk.$procmux$15655_Y [17], S=\common.pb.uart.tx_mod.symclk_n_reset) into $auto$simplemap.cc:420:simplemap_dff$21871 (SB_DFF).
  Merging $auto$simplemap.cc:277:simplemap_mux$20935 (A=1'0, B=$techmap\common.pb.uart.tx_mod.symclk.$procmux$15655_Y [18], S=\common.pb.uart.tx_mod.symclk_n_reset) into $auto$simplemap.cc:420:simplemap_dff$21872 (SB_DFF).
  Merging $auto$simplemap.cc:277:simplemap_mux$20936 (A=1'0, B=$techmap\common.pb.uart.tx_mod.symclk.$procmux$15655_Y [19], S=\common.pb.uart.tx_mod.symclk_n_reset) into $auto$simplemap.cc:420:simplemap_dff$21873 (SB_DFF).
  Merging $auto$simplemap.cc:277:simplemap_mux$20937 (A=1'0, B=$techmap\common.pb.uart.tx_mod.symclk.$procmux$15655_Y [20], S=\common.pb.uart.tx_mod.symclk_n_reset) into $auto$simplemap.cc:420:simplemap_dff$21874 (SB_DFF).
  Merging $auto$simplemap.cc:277:simplemap_mux$20938 (A=1'0, B=$techmap\common.pb.uart.tx_mod.symclk.$procmux$15655_Y [21], S=\common.pb.uart.tx_mod.symclk_n_reset) into $auto$simplemap.cc:420:simplemap_dff$21875 (SB_DFF).
  Merging $auto$simplemap.cc:277:simplemap_mux$20939 (A=1'0, B=$techmap\common.pb.uart.tx_mod.symclk.$procmux$15655_Y [22], S=\common.pb.uart.tx_mod.symclk_n_reset) into $auto$simplemap.cc:420:simplemap_dff$21876 (SB_DFF).
  Merging $auto$simplemap.cc:277:simplemap_mux$20940 (A=1'0, B=$techmap\common.pb.uart.tx_mod.symclk.$procmux$15655_Y [23], S=\common.pb.uart.tx_mod.symclk_n_reset) into $auto$simplemap.cc:420:simplemap_dff$21877 (SB_DFF).
  Merging $auto$simplemap.cc:277:simplemap_mux$21830 (A=1'0, B=$techmap\common.pb.uart.rx_mod.symclk.$procmux$15655_Y [1], S=\common.pb.uart.rx_mod.symclk_n_reset) into $auto$simplemap.cc:420:simplemap_dff$22061 (SB_DFF).
  Merging $auto$simplemap.cc:277:simplemap_mux$20917 (A=1'0, B=$techmap\common.pb.uart.tx_mod.symclk.$procmux$15655_Y [0], S=\common.pb.uart.tx_mod.symclk_n_reset) into $auto$simplemap.cc:420:simplemap_dff$21854 (SB_DFF).
  Merging $auto$simplemap.cc:277:simplemap_mux$21952 (A=1'0, B=$techmap\common.pb.uart.tx_mod.symclk.$procmux$15622_Y, S=\common.pb.uart.tx_mod.symclk_n_reset) into $auto$simplemap.cc:420:simplemap_dff$21878 (SB_DFF).
  Merging $auto$simplemap.cc:277:simplemap_mux$22157 (A=1'0, B=$techmap\common.pb.uart.rx_mod.symclk.$procmux$15633_Y, S=\common.pb.uart.rx_mod.symclk_n_reset) into $auto$simplemap.cc:420:simplemap_dff$22059 (SB_DFF).
  Merging $auto$simplemap.cc:277:simplemap_mux$21831 (A=1'0, B=$techmap\common.pb.uart.rx_mod.symclk.$procmux$15655_Y [2], S=\common.pb.uart.rx_mod.symclk_n_reset) into $auto$simplemap.cc:420:simplemap_dff$22062 (SB_DFF).
  Merging $auto$simplemap.cc:277:simplemap_mux$21832 (A=1'0, B=$techmap\common.pb.uart.rx_mod.symclk.$procmux$15655_Y [3], S=\common.pb.uart.rx_mod.symclk_n_reset) into $auto$simplemap.cc:420:simplemap_dff$22063 (SB_DFF).
  Merging $auto$simplemap.cc:277:simplemap_mux$21833 (A=1'0, B=$techmap\common.pb.uart.rx_mod.symclk.$procmux$15655_Y [4], S=\common.pb.uart.rx_mod.symclk_n_reset) into $auto$simplemap.cc:420:simplemap_dff$22064 (SB_DFF).
  Merging $auto$simplemap.cc:277:simplemap_mux$21834 (A=1'0, B=$techmap\common.pb.uart.rx_mod.symclk.$procmux$15655_Y [5], S=\common.pb.uart.rx_mod.symclk_n_reset) into $auto$simplemap.cc:420:simplemap_dff$22065 (SB_DFF).
  Merging $auto$simplemap.cc:277:simplemap_mux$21835 (A=1'0, B=$techmap\common.pb.uart.rx_mod.symclk.$procmux$15655_Y [6], S=\common.pb.uart.rx_mod.symclk_n_reset) into $auto$simplemap.cc:420:simplemap_dff$22066 (SB_DFF).
  Merging $auto$simplemap.cc:277:simplemap_mux$21836 (A=1'0, B=$techmap\common.pb.uart.rx_mod.symclk.$procmux$15655_Y [7], S=\common.pb.uart.rx_mod.symclk_n_reset) into $auto$simplemap.cc:420:simplemap_dff$22067 (SB_DFF).
  Merging $auto$simplemap.cc:277:simplemap_mux$21837 (A=1'0, B=$techmap\common.pb.uart.rx_mod.symclk.$procmux$15655_Y [8], S=\common.pb.uart.rx_mod.symclk_n_reset) into $auto$simplemap.cc:420:simplemap_dff$22068 (SB_DFF).
  Merging $auto$simplemap.cc:277:simplemap_mux$21838 (A=1'0, B=$techmap\common.pb.uart.rx_mod.symclk.$procmux$15655_Y [9], S=\common.pb.uart.rx_mod.symclk_n_reset) into $auto$simplemap.cc:420:simplemap_dff$22069 (SB_DFF).
  Merging $auto$simplemap.cc:277:simplemap_mux$21839 (A=1'0, B=$techmap\common.pb.uart.rx_mod.symclk.$procmux$15655_Y [10], S=\common.pb.uart.rx_mod.symclk_n_reset) into $auto$simplemap.cc:420:simplemap_dff$22070 (SB_DFF).
  Merging $auto$simplemap.cc:277:simplemap_mux$21840 (A=1'0, B=$techmap\common.pb.uart.rx_mod.symclk.$procmux$15655_Y [11], S=\common.pb.uart.rx_mod.symclk_n_reset) into $auto$simplemap.cc:420:simplemap_dff$22071 (SB_DFF).
  Merging $auto$simplemap.cc:277:simplemap_mux$21841 (A=1'0, B=$techmap\common.pb.uart.rx_mod.symclk.$procmux$15655_Y [12], S=\common.pb.uart.rx_mod.symclk_n_reset) into $auto$simplemap.cc:420:simplemap_dff$22072 (SB_DFF).
  Merging $auto$simplemap.cc:277:simplemap_mux$21842 (A=1'0, B=$techmap\common.pb.uart.rx_mod.symclk.$procmux$15655_Y [13], S=\common.pb.uart.rx_mod.symclk_n_reset) into $auto$simplemap.cc:420:simplemap_dff$22073 (SB_DFF).
  Merging $auto$simplemap.cc:277:simplemap_mux$21843 (A=1'0, B=$techmap\common.pb.uart.rx_mod.symclk.$procmux$15655_Y [14], S=\common.pb.uart.rx_mod.symclk_n_reset) into $auto$simplemap.cc:420:simplemap_dff$22074 (SB_DFF).
  Merging $auto$simplemap.cc:277:simplemap_mux$21844 (A=1'0, B=$techmap\common.pb.uart.rx_mod.symclk.$procmux$15655_Y [15], S=\common.pb.uart.rx_mod.symclk_n_reset) into $auto$simplemap.cc:420:simplemap_dff$22075 (SB_DFF).
  Merging $auto$simplemap.cc:277:simplemap_mux$21845 (A=1'0, B=$techmap\common.pb.uart.rx_mod.symclk.$procmux$15655_Y [16], S=\common.pb.uart.rx_mod.symclk_n_reset) into $auto$simplemap.cc:420:simplemap_dff$22076 (SB_DFF).
  Merging $auto$simplemap.cc:277:simplemap_mux$21846 (A=1'0, B=$techmap\common.pb.uart.rx_mod.symclk.$procmux$15655_Y [17], S=\common.pb.uart.rx_mod.symclk_n_reset) into $auto$simplemap.cc:420:simplemap_dff$22077 (SB_DFF).
  Merging $auto$simplemap.cc:277:simplemap_mux$21847 (A=1'0, B=$techmap\common.pb.uart.rx_mod.symclk.$procmux$15655_Y [18], S=\common.pb.uart.rx_mod.symclk_n_reset) into $auto$simplemap.cc:420:simplemap_dff$22078 (SB_DFF).
  Merging $auto$simplemap.cc:277:simplemap_mux$21848 (A=1'0, B=$techmap\common.pb.uart.rx_mod.symclk.$procmux$15655_Y [19], S=\common.pb.uart.rx_mod.symclk_n_reset) into $auto$simplemap.cc:420:simplemap_dff$22079 (SB_DFF).
  Merging $auto$simplemap.cc:277:simplemap_mux$21849 (A=1'0, B=$techmap\common.pb.uart.rx_mod.symclk.$procmux$15655_Y [20], S=\common.pb.uart.rx_mod.symclk_n_reset) into $auto$simplemap.cc:420:simplemap_dff$22080 (SB_DFF).
  Merging $auto$simplemap.cc:277:simplemap_mux$21850 (A=1'0, B=$techmap\common.pb.uart.rx_mod.symclk.$procmux$15655_Y [21], S=\common.pb.uart.rx_mod.symclk_n_reset) into $auto$simplemap.cc:420:simplemap_dff$22081 (SB_DFF).
  Merging $auto$simplemap.cc:277:simplemap_mux$21851 (A=1'0, B=$techmap\common.pb.uart.rx_mod.symclk.$procmux$15655_Y [22], S=\common.pb.uart.rx_mod.symclk_n_reset) into $auto$simplemap.cc:420:simplemap_dff$22082 (SB_DFF).
  Merging $auto$simplemap.cc:277:simplemap_mux$21852 (A=1'0, B=$techmap\common.pb.uart.rx_mod.symclk.$procmux$15655_Y [23], S=\common.pb.uart.rx_mod.symclk_n_reset) into $auto$simplemap.cc:420:simplemap_dff$22083 (SB_DFF).
  Merging $auto$simplemap.cc:277:simplemap_mux$19496 (A=1'0, B=$techmap\common.pb.$procmux$9294_Y, S=$techmap\common.pb.$and$profibus_phy_mod.v:1047$6261_Y) into $auto$simplemap.cc:420:simplemap_dff$17702 (SB_DFF).
  Merging $auto$simplemap.cc:277:simplemap_mux$21829 (A=1'0, B=$techmap\common.pb.uart.rx_mod.symclk.$procmux$15655_Y [0], S=\common.pb.uart.rx_mod.symclk_n_reset) into $auto$simplemap.cc:420:simplemap_dff$22060 (SB_DFF).
  Merging $auto$simplemap.cc:277:simplemap_mux$22159 (A=1'0, B=$techmap\common.pb.uart.rx_mod.symclk.$procmux$15622_Y, S=\common.pb.uart.rx_mod.symclk_n_reset) into $auto$simplemap.cc:420:simplemap_dff$22084 (SB_DFF).

2.39. Executing ICE40_OPT pass (performing simple optimizations).

2.39.1. Running ICE40 specific optimizations.

2.39.2. Executing OPT_EXPR pass (perform const folding).
Optimizing module top_module.
<suppressed ~577 debug messages>

2.39.3. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\top_module'.
<suppressed ~16413 debug messages>
Removed a total of 5471 cells.

2.39.4. Executing OPT_RMDFF pass (remove dff with constant values).

2.39.5. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \top_module..
Removed 323 unused cells and 7744 unused wires.
<suppressed ~324 debug messages>

2.39.6. Rerunning OPT passes. (Removed registers in this run.)

2.39.7. Running ICE40 specific optimizations.

2.39.8. Executing OPT_EXPR pass (perform const folding).
Optimizing module top_module.
<suppressed ~51 debug messages>

2.39.9. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\top_module'.
Removed a total of 0 cells.

2.39.10. Executing OPT_RMDFF pass (remove dff with constant values).

2.39.11. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \top_module..

2.39.12. Rerunning OPT passes. (Removed registers in this run.)

2.39.13. Running ICE40 specific optimizations.

2.39.14. Executing OPT_EXPR pass (perform const folding).
Optimizing module top_module.

2.39.15. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\top_module'.
Removed a total of 0 cells.

2.39.16. Executing OPT_RMDFF pass (remove dff with constant values).

2.39.17. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \top_module..

2.39.18. Finished OPT passes. (There is nothing left to do.)

2.40. Executing TECHMAP pass (map to technology primitives).

2.40.1. Executing Verilog-2005 frontend: /home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/latches_map.v
Parsing Verilog input from `/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/latches_map.v' to AST representation.
Generating RTLIL representation for module `\$_DLATCH_N_'.
Generating RTLIL representation for module `\$_DLATCH_P_'.
Successfully finished Verilog frontend.

2.40.2. Continuing TECHMAP pass.
No more expansions possible.

2.41. Executing ABC pass (technology mapping using ABC).

2.41.1. Extracting gate netlist of module `\top_module' to `<abc-temp-dir>/input.blif'..
Extracted 3546 gates and 4316 wires to a netlist network with 768 inputs and 620 outputs.

2.41.1.1. Executing ABC.
Running ABC command: <yosys-exe-dir>/yosys-abc -s -f <abc-temp-dir>/abc.script 2>&1
ABC: ABC command line: "source <abc-temp-dir>/abc.script".
ABC: 
ABC: + read_blif <abc-temp-dir>/input.blif 
ABC: + read_lut <abc-temp-dir>/lutdefs.txt 
ABC: + strash 
ABC: + ifraig 
ABC: + scorr 
ABC: Warning: The network is combinational (run "fraig" or "fraig_sweep").
ABC: + dc2 
ABC: + dretime 
ABC: + retime 
ABC: + strash 
ABC: + dch -f 
ABC: + if 
ABC: + mfs2 
ABC: + lutpack -S 1 
ABC: + dress 
ABC: Total number of equiv classes                =     813.
ABC: Participating nodes from both networks       =    1840.
ABC: Participating nodes from the first network   =     814. (  67.11 % of nodes)
ABC: Participating nodes from the second network  =    1026. (  84.58 % of nodes)
ABC: Node pairs (any polarity)                    =     814. (  67.11 % of names can be moved)
ABC: Node pairs (same polarity)                   =     687. (  56.64 % of names can be moved)
ABC: Total runtime =     0.23 sec
ABC: + write_blif <abc-temp-dir>/output.blif 

2.41.1.2. Re-integrating ABC results.
ABC RESULTS:              $lut cells:     1212
ABC RESULTS:        internal signals:     2928
ABC RESULTS:           input signals:      768
ABC RESULTS:          output signals:      620
Removing temp directory.
Removed 0 unused cells and 2330 unused wires.

2.42. Executing ICE40_UNLUT pass (convert SB_LUT4 to $lut).
Mapping SB_LUT4 cell top_module.$auto$alumacc.cc:474:replace_alu$16118.slice[0].adder to $lut.
Mapping SB_LUT4 cell top_module.$auto$alumacc.cc:474:replace_alu$16118.slice[10].adder to $lut.
Mapping SB_LUT4 cell top_module.$auto$alumacc.cc:474:replace_alu$16118.slice[11].adder to $lut.
Mapping SB_LUT4 cell top_module.$auto$alumacc.cc:474:replace_alu$16118.slice[12].adder to $lut.
Mapping SB_LUT4 cell top_module.$auto$alumacc.cc:474:replace_alu$16118.slice[13].adder to $lut.
Mapping SB_LUT4 cell top_module.$auto$alumacc.cc:474:replace_alu$16118.slice[14].adder to $lut.
Mapping SB_LUT4 cell top_module.$auto$alumacc.cc:474:replace_alu$16118.slice[15].adder to $lut.
Mapping SB_LUT4 cell top_module.$auto$alumacc.cc:474:replace_alu$16118.slice[16].adder to $lut.
Mapping SB_LUT4 cell top_module.$auto$alumacc.cc:474:replace_alu$16118.slice[17].adder to $lut.
Mapping SB_LUT4 cell top_module.$auto$alumacc.cc:474:replace_alu$16118.slice[18].adder to $lut.
Mapping SB_LUT4 cell top_module.$auto$alumacc.cc:474:replace_alu$16118.slice[19].adder to $lut.
Mapping SB_LUT4 cell top_module.$auto$alumacc.cc:474:replace_alu$16118.slice[20].adder to $lut.
Mapping SB_LUT4 cell top_module.$auto$alumacc.cc:474:replace_alu$16118.slice[21].adder to $lut.
Mapping SB_LUT4 cell top_module.$auto$alumacc.cc:474:replace_alu$16118.slice[22].adder to $lut.
Mapping SB_LUT4 cell top_module.$auto$alumacc.cc:474:replace_alu$16118.slice[23].adder to $lut.
Mapping SB_LUT4 cell top_module.$auto$alumacc.cc:474:replace_alu$16118.slice[24].adder to $lut.
Mapping SB_LUT4 cell top_module.$auto$alumacc.cc:474:replace_alu$16118.slice[25].adder to $lut.
Mapping SB_LUT4 cell top_module.$auto$alumacc.cc:474:replace_alu$16118.slice[26].adder to $lut.
Mapping SB_LUT4 cell top_module.$auto$alumacc.cc:474:replace_alu$16118.slice[27].adder to $lut.
Mapping SB_LUT4 cell top_module.$auto$alumacc.cc:474:replace_alu$16118.slice[28].adder to $lut.
Mapping SB_LUT4 cell top_module.$auto$alumacc.cc:474:replace_alu$16118.slice[29].adder to $lut.
Mapping SB_LUT4 cell top_module.$auto$alumacc.cc:474:replace_alu$16118.slice[2].adder to $lut.
Mapping SB_LUT4 cell top_module.$auto$alumacc.cc:474:replace_alu$16118.slice[30].adder to $lut.
Mapping SB_LUT4 cell top_module.$auto$alumacc.cc:474:replace_alu$16118.slice[31].adder to $lut.
Mapping SB_LUT4 cell top_module.$auto$alumacc.cc:474:replace_alu$16118.slice[3].adder to $lut.
Mapping SB_LUT4 cell top_module.$auto$alumacc.cc:474:replace_alu$16118.slice[4].adder to $lut.
Mapping SB_LUT4 cell top_module.$auto$alumacc.cc:474:replace_alu$16118.slice[5].adder to $lut.
Mapping SB_LUT4 cell top_module.$auto$alumacc.cc:474:replace_alu$16118.slice[6].adder to $lut.
Mapping SB_LUT4 cell top_module.$auto$alumacc.cc:474:replace_alu$16118.slice[7].adder to $lut.
Mapping SB_LUT4 cell top_module.$auto$alumacc.cc:474:replace_alu$16118.slice[8].adder to $lut.
Mapping SB_LUT4 cell top_module.$auto$alumacc.cc:474:replace_alu$16118.slice[9].adder to $lut.
Mapping SB_LUT4 cell top_module.$auto$alumacc.cc:474:replace_alu$16121.slice[0].adder to $lut.
Mapping SB_LUT4 cell top_module.$auto$alumacc.cc:474:replace_alu$16121.slice[10].adder to $lut.
Mapping SB_LUT4 cell top_module.$auto$alumacc.cc:474:replace_alu$16121.slice[11].adder to $lut.
Mapping SB_LUT4 cell top_module.$auto$alumacc.cc:474:replace_alu$16121.slice[12].adder to $lut.
Mapping SB_LUT4 cell top_module.$auto$alumacc.cc:474:replace_alu$16121.slice[13].adder to $lut.
Mapping SB_LUT4 cell top_module.$auto$alumacc.cc:474:replace_alu$16121.slice[14].adder to $lut.
Mapping SB_LUT4 cell top_module.$auto$alumacc.cc:474:replace_alu$16121.slice[15].adder to $lut.
Mapping SB_LUT4 cell top_module.$auto$alumacc.cc:474:replace_alu$16121.slice[16].adder to $lut.
Mapping SB_LUT4 cell top_module.$auto$alumacc.cc:474:replace_alu$16121.slice[17].adder to $lut.
Mapping SB_LUT4 cell top_module.$auto$alumacc.cc:474:replace_alu$16121.slice[18].adder to $lut.
Mapping SB_LUT4 cell top_module.$auto$alumacc.cc:474:replace_alu$16121.slice[19].adder to $lut.
Mapping SB_LUT4 cell top_module.$auto$alumacc.cc:474:replace_alu$16121.slice[20].adder to $lut.
Mapping SB_LUT4 cell top_module.$auto$alumacc.cc:474:replace_alu$16121.slice[21].adder to $lut.
Mapping SB_LUT4 cell top_module.$auto$alumacc.cc:474:replace_alu$16121.slice[22].adder to $lut.
Mapping SB_LUT4 cell top_module.$auto$alumacc.cc:474:replace_alu$16121.slice[23].adder to $lut.
Mapping SB_LUT4 cell top_module.$auto$alumacc.cc:474:replace_alu$16121.slice[24].adder to $lut.
Mapping SB_LUT4 cell top_module.$auto$alumacc.cc:474:replace_alu$16121.slice[25].adder to $lut.
Mapping SB_LUT4 cell top_module.$auto$alumacc.cc:474:replace_alu$16121.slice[26].adder to $lut.
Mapping SB_LUT4 cell top_module.$auto$alumacc.cc:474:replace_alu$16121.slice[27].adder to $lut.
Mapping SB_LUT4 cell top_module.$auto$alumacc.cc:474:replace_alu$16121.slice[28].adder to $lut.
Mapping SB_LUT4 cell top_module.$auto$alumacc.cc:474:replace_alu$16121.slice[29].adder to $lut.
Mapping SB_LUT4 cell top_module.$auto$alumacc.cc:474:replace_alu$16121.slice[2].adder to $lut.
Mapping SB_LUT4 cell top_module.$auto$alumacc.cc:474:replace_alu$16121.slice[30].adder to $lut.
Mapping SB_LUT4 cell top_module.$auto$alumacc.cc:474:replace_alu$16121.slice[31].adder to $lut.
Mapping SB_LUT4 cell top_module.$auto$alumacc.cc:474:replace_alu$16121.slice[3].adder to $lut.
Mapping SB_LUT4 cell top_module.$auto$alumacc.cc:474:replace_alu$16121.slice[4].adder to $lut.
Mapping SB_LUT4 cell top_module.$auto$alumacc.cc:474:replace_alu$16121.slice[5].adder to $lut.
Mapping SB_LUT4 cell top_module.$auto$alumacc.cc:474:replace_alu$16121.slice[6].adder to $lut.
Mapping SB_LUT4 cell top_module.$auto$alumacc.cc:474:replace_alu$16121.slice[7].adder to $lut.
Mapping SB_LUT4 cell top_module.$auto$alumacc.cc:474:replace_alu$16121.slice[8].adder to $lut.
Mapping SB_LUT4 cell top_module.$auto$alumacc.cc:474:replace_alu$16121.slice[9].adder to $lut.
Mapping SB_LUT4 cell top_module.$auto$alumacc.cc:474:replace_alu$16124.slice[0].adder to $lut.
Mapping SB_LUT4 cell top_module.$auto$alumacc.cc:474:replace_alu$16124.slice[10].adder to $lut.
Mapping SB_LUT4 cell top_module.$auto$alumacc.cc:474:replace_alu$16124.slice[11].adder to $lut.
Mapping SB_LUT4 cell top_module.$auto$alumacc.cc:474:replace_alu$16124.slice[12].adder to $lut.
Mapping SB_LUT4 cell top_module.$auto$alumacc.cc:474:replace_alu$16124.slice[13].adder to $lut.
Mapping SB_LUT4 cell top_module.$auto$alumacc.cc:474:replace_alu$16124.slice[14].adder to $lut.
Mapping SB_LUT4 cell top_module.$auto$alumacc.cc:474:replace_alu$16124.slice[15].adder to $lut.
Mapping SB_LUT4 cell top_module.$auto$alumacc.cc:474:replace_alu$16124.slice[16].adder to $lut.
Mapping SB_LUT4 cell top_module.$auto$alumacc.cc:474:replace_alu$16124.slice[17].adder to $lut.
Mapping SB_LUT4 cell top_module.$auto$alumacc.cc:474:replace_alu$16124.slice[18].adder to $lut.
Mapping SB_LUT4 cell top_module.$auto$alumacc.cc:474:replace_alu$16124.slice[19].adder to $lut.
Mapping SB_LUT4 cell top_module.$auto$alumacc.cc:474:replace_alu$16124.slice[20].adder to $lut.
Mapping SB_LUT4 cell top_module.$auto$alumacc.cc:474:replace_alu$16124.slice[21].adder to $lut.
Mapping SB_LUT4 cell top_module.$auto$alumacc.cc:474:replace_alu$16124.slice[22].adder to $lut.
Mapping SB_LUT4 cell top_module.$auto$alumacc.cc:474:replace_alu$16124.slice[23].adder to $lut.
Mapping SB_LUT4 cell top_module.$auto$alumacc.cc:474:replace_alu$16124.slice[2].adder to $lut.
Mapping SB_LUT4 cell top_module.$auto$alumacc.cc:474:replace_alu$16124.slice[3].adder to $lut.
Mapping SB_LUT4 cell top_module.$auto$alumacc.cc:474:replace_alu$16124.slice[4].adder to $lut.
Mapping SB_LUT4 cell top_module.$auto$alumacc.cc:474:replace_alu$16124.slice[5].adder to $lut.
Mapping SB_LUT4 cell top_module.$auto$alumacc.cc:474:replace_alu$16124.slice[6].adder to $lut.
Mapping SB_LUT4 cell top_module.$auto$alumacc.cc:474:replace_alu$16124.slice[7].adder to $lut.
Mapping SB_LUT4 cell top_module.$auto$alumacc.cc:474:replace_alu$16124.slice[8].adder to $lut.
Mapping SB_LUT4 cell top_module.$auto$alumacc.cc:474:replace_alu$16124.slice[9].adder to $lut.
Mapping SB_LUT4 cell top_module.$auto$alumacc.cc:474:replace_alu$16127.slice[0].adder to $lut.
Mapping SB_LUT4 cell top_module.$auto$alumacc.cc:474:replace_alu$16127.slice[2].adder to $lut.
Mapping SB_LUT4 cell top_module.$auto$alumacc.cc:474:replace_alu$16127.slice[3].adder to $lut.
Mapping SB_LUT4 cell top_module.$auto$alumacc.cc:474:replace_alu$16127.slice[4].adder to $lut.
Mapping SB_LUT4 cell top_module.$auto$alumacc.cc:474:replace_alu$16127.slice[5].adder to $lut.
Mapping SB_LUT4 cell top_module.$auto$alumacc.cc:474:replace_alu$16127.slice[6].adder to $lut.
Mapping SB_LUT4 cell top_module.$auto$alumacc.cc:474:replace_alu$16127.slice[7].adder to $lut.
Mapping SB_LUT4 cell top_module.$auto$alumacc.cc:474:replace_alu$16130.slice[0].adder to $lut.
Mapping SB_LUT4 cell top_module.$auto$alumacc.cc:474:replace_alu$16130.slice[2].adder to $lut.
Mapping SB_LUT4 cell top_module.$auto$alumacc.cc:474:replace_alu$16130.slice[3].adder to $lut.
Mapping SB_LUT4 cell top_module.$auto$alumacc.cc:474:replace_alu$16130.slice[4].adder to $lut.
Mapping SB_LUT4 cell top_module.$auto$alumacc.cc:474:replace_alu$16130.slice[5].adder to $lut.
Mapping SB_LUT4 cell top_module.$auto$alumacc.cc:474:replace_alu$16130.slice[6].adder to $lut.
Mapping SB_LUT4 cell top_module.$auto$alumacc.cc:474:replace_alu$16130.slice[7].adder to $lut.
Mapping SB_LUT4 cell top_module.$auto$alumacc.cc:474:replace_alu$16133.slice[0].adder to $lut.
Mapping SB_LUT4 cell top_module.$auto$alumacc.cc:474:replace_alu$16133.slice[2].adder to $lut.
Mapping SB_LUT4 cell top_module.$auto$alumacc.cc:474:replace_alu$16133.slice[3].adder to $lut.
Mapping SB_LUT4 cell top_module.$auto$alumacc.cc:474:replace_alu$16133.slice[4].adder to $lut.
Mapping SB_LUT4 cell top_module.$auto$alumacc.cc:474:replace_alu$16133.slice[5].adder to $lut.
Mapping SB_LUT4 cell top_module.$auto$alumacc.cc:474:replace_alu$16133.slice[6].adder to $lut.
Mapping SB_LUT4 cell top_module.$auto$alumacc.cc:474:replace_alu$16133.slice[7].adder to $lut.
Mapping SB_LUT4 cell top_module.$auto$alumacc.cc:474:replace_alu$16136.slice[0].adder to $lut.
Mapping SB_LUT4 cell top_module.$auto$alumacc.cc:474:replace_alu$16136.slice[2].adder to $lut.
Mapping SB_LUT4 cell top_module.$auto$alumacc.cc:474:replace_alu$16136.slice[3].adder to $lut.
Mapping SB_LUT4 cell top_module.$auto$alumacc.cc:474:replace_alu$16136.slice[4].adder to $lut.
Mapping SB_LUT4 cell top_module.$auto$alumacc.cc:474:replace_alu$16136.slice[5].adder to $lut.
Mapping SB_LUT4 cell top_module.$auto$alumacc.cc:474:replace_alu$16136.slice[6].adder to $lut.
Mapping SB_LUT4 cell top_module.$auto$alumacc.cc:474:replace_alu$16136.slice[7].adder to $lut.
Mapping SB_LUT4 cell top_module.$auto$alumacc.cc:474:replace_alu$16139.slice[0].adder to $lut.
Mapping SB_LUT4 cell top_module.$auto$alumacc.cc:474:replace_alu$16139.slice[10].adder to $lut.
Mapping SB_LUT4 cell top_module.$auto$alumacc.cc:474:replace_alu$16139.slice[11].adder to $lut.
Mapping SB_LUT4 cell top_module.$auto$alumacc.cc:474:replace_alu$16139.slice[12].adder to $lut.
Mapping SB_LUT4 cell top_module.$auto$alumacc.cc:474:replace_alu$16139.slice[13].adder to $lut.
Mapping SB_LUT4 cell top_module.$auto$alumacc.cc:474:replace_alu$16139.slice[14].adder to $lut.
Mapping SB_LUT4 cell top_module.$auto$alumacc.cc:474:replace_alu$16139.slice[15].adder to $lut.
Mapping SB_LUT4 cell top_module.$auto$alumacc.cc:474:replace_alu$16139.slice[16].adder to $lut.
Mapping SB_LUT4 cell top_module.$auto$alumacc.cc:474:replace_alu$16139.slice[17].adder to $lut.
Mapping SB_LUT4 cell top_module.$auto$alumacc.cc:474:replace_alu$16139.slice[18].adder to $lut.
Mapping SB_LUT4 cell top_module.$auto$alumacc.cc:474:replace_alu$16139.slice[19].adder to $lut.
Mapping SB_LUT4 cell top_module.$auto$alumacc.cc:474:replace_alu$16139.slice[20].adder to $lut.
Mapping SB_LUT4 cell top_module.$auto$alumacc.cc:474:replace_alu$16139.slice[21].adder to $lut.
Mapping SB_LUT4 cell top_module.$auto$alumacc.cc:474:replace_alu$16139.slice[22].adder to $lut.
Mapping SB_LUT4 cell top_module.$auto$alumacc.cc:474:replace_alu$16139.slice[23].adder to $lut.
Mapping SB_LUT4 cell top_module.$auto$alumacc.cc:474:replace_alu$16139.slice[6].adder to $lut.
Mapping SB_LUT4 cell top_module.$auto$alumacc.cc:474:replace_alu$16139.slice[7].adder to $lut.
Mapping SB_LUT4 cell top_module.$auto$alumacc.cc:474:replace_alu$16139.slice[8].adder to $lut.
Mapping SB_LUT4 cell top_module.$auto$alumacc.cc:474:replace_alu$16139.slice[9].adder to $lut.
Mapping SB_LUT4 cell top_module.$auto$alumacc.cc:474:replace_alu$16142.slice[0].adder to $lut.
Mapping SB_LUT4 cell top_module.$auto$alumacc.cc:474:replace_alu$16142.slice[2].adder to $lut.
Mapping SB_LUT4 cell top_module.$auto$alumacc.cc:474:replace_alu$16142.slice[3].adder to $lut.
Mapping SB_LUT4 cell top_module.$auto$alumacc.cc:474:replace_alu$16142.slice[4].adder to $lut.
Mapping SB_LUT4 cell top_module.$auto$alumacc.cc:474:replace_alu$16142.slice[5].adder to $lut.
Mapping SB_LUT4 cell top_module.$auto$alumacc.cc:474:replace_alu$16142.slice[6].adder to $lut.
Mapping SB_LUT4 cell top_module.$auto$alumacc.cc:474:replace_alu$16142.slice[7].adder to $lut.
Mapping SB_LUT4 cell top_module.$auto$alumacc.cc:474:replace_alu$16145.slice[0].adder to $lut.
Mapping SB_LUT4 cell top_module.$auto$alumacc.cc:474:replace_alu$16145.slice[2].adder to $lut.
Mapping SB_LUT4 cell top_module.$auto$alumacc.cc:474:replace_alu$16145.slice[3].adder to $lut.
Mapping SB_LUT4 cell top_module.$auto$alumacc.cc:474:replace_alu$16145.slice[4].adder to $lut.
Mapping SB_LUT4 cell top_module.$auto$alumacc.cc:474:replace_alu$16145.slice[5].adder to $lut.
Mapping SB_LUT4 cell top_module.$auto$alumacc.cc:474:replace_alu$16145.slice[6].adder to $lut.
Mapping SB_LUT4 cell top_module.$auto$alumacc.cc:474:replace_alu$16145.slice[7].adder to $lut.
Mapping SB_LUT4 cell top_module.$auto$alumacc.cc:474:replace_alu$16148.slice[0].adder to $lut.
Mapping SB_LUT4 cell top_module.$auto$alumacc.cc:474:replace_alu$16148.slice[2].adder to $lut.
Mapping SB_LUT4 cell top_module.$auto$alumacc.cc:474:replace_alu$16148.slice[3].adder to $lut.
Mapping SB_LUT4 cell top_module.$auto$alumacc.cc:474:replace_alu$16148.slice[4].adder to $lut.
Mapping SB_LUT4 cell top_module.$auto$alumacc.cc:474:replace_alu$16148.slice[5].adder to $lut.
Mapping SB_LUT4 cell top_module.$auto$alumacc.cc:474:replace_alu$16148.slice[6].adder to $lut.
Mapping SB_LUT4 cell top_module.$auto$alumacc.cc:474:replace_alu$16148.slice[7].adder to $lut.
Mapping SB_LUT4 cell top_module.$auto$alumacc.cc:474:replace_alu$16151.slice[0].adder to $lut.
Mapping SB_LUT4 cell top_module.$auto$alumacc.cc:474:replace_alu$16151.slice[2].adder to $lut.
Mapping SB_LUT4 cell top_module.$auto$alumacc.cc:474:replace_alu$16151.slice[3].adder to $lut.
Mapping SB_LUT4 cell top_module.$auto$alumacc.cc:474:replace_alu$16151.slice[4].adder to $lut.
Mapping SB_LUT4 cell top_module.$auto$alumacc.cc:474:replace_alu$16151.slice[5].adder to $lut.
Mapping SB_LUT4 cell top_module.$auto$alumacc.cc:474:replace_alu$16154.slice[0].adder to $lut.
Mapping SB_LUT4 cell top_module.$auto$alumacc.cc:474:replace_alu$16154.slice[3].adder to $lut.
Mapping SB_LUT4 cell top_module.$auto$alumacc.cc:474:replace_alu$16154.slice[4].adder to $lut.
Mapping SB_LUT4 cell top_module.$auto$alumacc.cc:474:replace_alu$16154.slice[5].adder to $lut.
Mapping SB_LUT4 cell top_module.$auto$alumacc.cc:474:replace_alu$16154.slice[6].adder to $lut.
Mapping SB_LUT4 cell top_module.$auto$alumacc.cc:474:replace_alu$16154.slice[7].adder to $lut.
Mapping SB_LUT4 cell top_module.$auto$alumacc.cc:474:replace_alu$16157.slice[0].adder to $lut.
Mapping SB_LUT4 cell top_module.$auto$alumacc.cc:474:replace_alu$16157.slice[2].adder to $lut.
Mapping SB_LUT4 cell top_module.$auto$alumacc.cc:474:replace_alu$16157.slice[3].adder to $lut.
Mapping SB_LUT4 cell top_module.$auto$alumacc.cc:474:replace_alu$16160.slice[0].adder to $lut.
Mapping SB_LUT4 cell top_module.$auto$alumacc.cc:474:replace_alu$16160.slice[3].adder to $lut.
Mapping SB_LUT4 cell top_module.$auto$alumacc.cc:474:replace_alu$16160.slice[4].adder to $lut.
Mapping SB_LUT4 cell top_module.$auto$alumacc.cc:474:replace_alu$16163.slice[0].adder to $lut.
Mapping SB_LUT4 cell top_module.$auto$alumacc.cc:474:replace_alu$16163.slice[10].adder to $lut.
Mapping SB_LUT4 cell top_module.$auto$alumacc.cc:474:replace_alu$16163.slice[11].adder to $lut.
Mapping SB_LUT4 cell top_module.$auto$alumacc.cc:474:replace_alu$16163.slice[12].adder to $lut.
Mapping SB_LUT4 cell top_module.$auto$alumacc.cc:474:replace_alu$16163.slice[13].adder to $lut.
Mapping SB_LUT4 cell top_module.$auto$alumacc.cc:474:replace_alu$16163.slice[14].adder to $lut.
Mapping SB_LUT4 cell top_module.$auto$alumacc.cc:474:replace_alu$16163.slice[15].adder to $lut.
Mapping SB_LUT4 cell top_module.$auto$alumacc.cc:474:replace_alu$16163.slice[16].adder to $lut.
Mapping SB_LUT4 cell top_module.$auto$alumacc.cc:474:replace_alu$16163.slice[17].adder to $lut.
Mapping SB_LUT4 cell top_module.$auto$alumacc.cc:474:replace_alu$16163.slice[18].adder to $lut.
Mapping SB_LUT4 cell top_module.$auto$alumacc.cc:474:replace_alu$16163.slice[19].adder to $lut.
Mapping SB_LUT4 cell top_module.$auto$alumacc.cc:474:replace_alu$16163.slice[20].adder to $lut.
Mapping SB_LUT4 cell top_module.$auto$alumacc.cc:474:replace_alu$16163.slice[21].adder to $lut.
Mapping SB_LUT4 cell top_module.$auto$alumacc.cc:474:replace_alu$16163.slice[22].adder to $lut.
Mapping SB_LUT4 cell top_module.$auto$alumacc.cc:474:replace_alu$16163.slice[23].adder to $lut.
Mapping SB_LUT4 cell top_module.$auto$alumacc.cc:474:replace_alu$16163.slice[2].adder to $lut.
Mapping SB_LUT4 cell top_module.$auto$alumacc.cc:474:replace_alu$16163.slice[3].adder to $lut.
Mapping SB_LUT4 cell top_module.$auto$alumacc.cc:474:replace_alu$16163.slice[4].adder to $lut.
Mapping SB_LUT4 cell top_module.$auto$alumacc.cc:474:replace_alu$16163.slice[5].adder to $lut.
Mapping SB_LUT4 cell top_module.$auto$alumacc.cc:474:replace_alu$16163.slice[6].adder to $lut.
Mapping SB_LUT4 cell top_module.$auto$alumacc.cc:474:replace_alu$16163.slice[7].adder to $lut.
Mapping SB_LUT4 cell top_module.$auto$alumacc.cc:474:replace_alu$16163.slice[8].adder to $lut.
Mapping SB_LUT4 cell top_module.$auto$alumacc.cc:474:replace_alu$16163.slice[9].adder to $lut.
Mapping SB_LUT4 cell top_module.$auto$alumacc.cc:474:replace_alu$16166.slice[0].adder to $lut.
Mapping SB_LUT4 cell top_module.$auto$alumacc.cc:474:replace_alu$16166.slice[10].adder to $lut.
Mapping SB_LUT4 cell top_module.$auto$alumacc.cc:474:replace_alu$16166.slice[11].adder to $lut.
Mapping SB_LUT4 cell top_module.$auto$alumacc.cc:474:replace_alu$16166.slice[12].adder to $lut.
Mapping SB_LUT4 cell top_module.$auto$alumacc.cc:474:replace_alu$16166.slice[13].adder to $lut.
Mapping SB_LUT4 cell top_module.$auto$alumacc.cc:474:replace_alu$16166.slice[14].adder to $lut.
Mapping SB_LUT4 cell top_module.$auto$alumacc.cc:474:replace_alu$16166.slice[15].adder to $lut.
Mapping SB_LUT4 cell top_module.$auto$alumacc.cc:474:replace_alu$16166.slice[16].adder to $lut.
Mapping SB_LUT4 cell top_module.$auto$alumacc.cc:474:replace_alu$16166.slice[17].adder to $lut.
Mapping SB_LUT4 cell top_module.$auto$alumacc.cc:474:replace_alu$16166.slice[18].adder to $lut.
Mapping SB_LUT4 cell top_module.$auto$alumacc.cc:474:replace_alu$16166.slice[19].adder to $lut.
Mapping SB_LUT4 cell top_module.$auto$alumacc.cc:474:replace_alu$16166.slice[20].adder to $lut.
Mapping SB_LUT4 cell top_module.$auto$alumacc.cc:474:replace_alu$16166.slice[21].adder to $lut.
Mapping SB_LUT4 cell top_module.$auto$alumacc.cc:474:replace_alu$16166.slice[22].adder to $lut.
Mapping SB_LUT4 cell top_module.$auto$alumacc.cc:474:replace_alu$16166.slice[23].adder to $lut.
Mapping SB_LUT4 cell top_module.$auto$alumacc.cc:474:replace_alu$16166.slice[2].adder to $lut.
Mapping SB_LUT4 cell top_module.$auto$alumacc.cc:474:replace_alu$16166.slice[3].adder to $lut.
Mapping SB_LUT4 cell top_module.$auto$alumacc.cc:474:replace_alu$16166.slice[4].adder to $lut.
Mapping SB_LUT4 cell top_module.$auto$alumacc.cc:474:replace_alu$16166.slice[5].adder to $lut.
Mapping SB_LUT4 cell top_module.$auto$alumacc.cc:474:replace_alu$16166.slice[6].adder to $lut.
Mapping SB_LUT4 cell top_module.$auto$alumacc.cc:474:replace_alu$16166.slice[7].adder to $lut.
Mapping SB_LUT4 cell top_module.$auto$alumacc.cc:474:replace_alu$16166.slice[8].adder to $lut.
Mapping SB_LUT4 cell top_module.$auto$alumacc.cc:474:replace_alu$16166.slice[9].adder to $lut.
Mapping SB_LUT4 cell top_module.$auto$alumacc.cc:474:replace_alu$16169.slice[0].adder to $lut.
Mapping SB_LUT4 cell top_module.$auto$alumacc.cc:474:replace_alu$16169.slice[10].adder to $lut.
Mapping SB_LUT4 cell top_module.$auto$alumacc.cc:474:replace_alu$16169.slice[11].adder to $lut.
Mapping SB_LUT4 cell top_module.$auto$alumacc.cc:474:replace_alu$16169.slice[12].adder to $lut.
Mapping SB_LUT4 cell top_module.$auto$alumacc.cc:474:replace_alu$16169.slice[13].adder to $lut.
Mapping SB_LUT4 cell top_module.$auto$alumacc.cc:474:replace_alu$16169.slice[14].adder to $lut.
Mapping SB_LUT4 cell top_module.$auto$alumacc.cc:474:replace_alu$16169.slice[15].adder to $lut.
Mapping SB_LUT4 cell top_module.$auto$alumacc.cc:474:replace_alu$16169.slice[16].adder to $lut.
Mapping SB_LUT4 cell top_module.$auto$alumacc.cc:474:replace_alu$16169.slice[17].adder to $lut.
Mapping SB_LUT4 cell top_module.$auto$alumacc.cc:474:replace_alu$16169.slice[18].adder to $lut.
Mapping SB_LUT4 cell top_module.$auto$alumacc.cc:474:replace_alu$16169.slice[19].adder to $lut.
Mapping SB_LUT4 cell top_module.$auto$alumacc.cc:474:replace_alu$16169.slice[20].adder to $lut.
Mapping SB_LUT4 cell top_module.$auto$alumacc.cc:474:replace_alu$16169.slice[21].adder to $lut.
Mapping SB_LUT4 cell top_module.$auto$alumacc.cc:474:replace_alu$16169.slice[22].adder to $lut.
Mapping SB_LUT4 cell top_module.$auto$alumacc.cc:474:replace_alu$16169.slice[23].adder to $lut.
Mapping SB_LUT4 cell top_module.$auto$alumacc.cc:474:replace_alu$16169.slice[24].adder to $lut.
Mapping SB_LUT4 cell top_module.$auto$alumacc.cc:474:replace_alu$16169.slice[2].adder to $lut.
Mapping SB_LUT4 cell top_module.$auto$alumacc.cc:474:replace_alu$16169.slice[3].adder to $lut.
Mapping SB_LUT4 cell top_module.$auto$alumacc.cc:474:replace_alu$16169.slice[4].adder to $lut.
Mapping SB_LUT4 cell top_module.$auto$alumacc.cc:474:replace_alu$16169.slice[5].adder to $lut.
Mapping SB_LUT4 cell top_module.$auto$alumacc.cc:474:replace_alu$16169.slice[6].adder to $lut.
Mapping SB_LUT4 cell top_module.$auto$alumacc.cc:474:replace_alu$16169.slice[7].adder to $lut.
Mapping SB_LUT4 cell top_module.$auto$alumacc.cc:474:replace_alu$16169.slice[8].adder to $lut.
Mapping SB_LUT4 cell top_module.$auto$alumacc.cc:474:replace_alu$16169.slice[9].adder to $lut.
Mapping SB_LUT4 cell top_module.$auto$alumacc.cc:474:replace_alu$16172.slice[0].adder to $lut.
Mapping SB_LUT4 cell top_module.$auto$alumacc.cc:474:replace_alu$16172.slice[2].adder to $lut.
Mapping SB_LUT4 cell top_module.$auto$alumacc.cc:474:replace_alu$16172.slice[3].adder to $lut.
Mapping SB_LUT4 cell top_module.$auto$alumacc.cc:474:replace_alu$16175.slice[0].adder to $lut.
Mapping SB_LUT4 cell top_module.$auto$alumacc.cc:474:replace_alu$16178.slice[0].adder to $lut.
Mapping SB_LUT4 cell top_module.$auto$alumacc.cc:474:replace_alu$16178.slice[10].adder to $lut.
Mapping SB_LUT4 cell top_module.$auto$alumacc.cc:474:replace_alu$16178.slice[11].adder to $lut.
Mapping SB_LUT4 cell top_module.$auto$alumacc.cc:474:replace_alu$16178.slice[12].adder to $lut.
Mapping SB_LUT4 cell top_module.$auto$alumacc.cc:474:replace_alu$16178.slice[13].adder to $lut.
Mapping SB_LUT4 cell top_module.$auto$alumacc.cc:474:replace_alu$16178.slice[14].adder to $lut.
Mapping SB_LUT4 cell top_module.$auto$alumacc.cc:474:replace_alu$16178.slice[15].adder to $lut.
Mapping SB_LUT4 cell top_module.$auto$alumacc.cc:474:replace_alu$16178.slice[16].adder to $lut.
Mapping SB_LUT4 cell top_module.$auto$alumacc.cc:474:replace_alu$16178.slice[17].adder to $lut.
Mapping SB_LUT4 cell top_module.$auto$alumacc.cc:474:replace_alu$16178.slice[18].adder to $lut.
Mapping SB_LUT4 cell top_module.$auto$alumacc.cc:474:replace_alu$16178.slice[19].adder to $lut.
Mapping SB_LUT4 cell top_module.$auto$alumacc.cc:474:replace_alu$16178.slice[20].adder to $lut.
Mapping SB_LUT4 cell top_module.$auto$alumacc.cc:474:replace_alu$16178.slice[21].adder to $lut.
Mapping SB_LUT4 cell top_module.$auto$alumacc.cc:474:replace_alu$16178.slice[22].adder to $lut.
Mapping SB_LUT4 cell top_module.$auto$alumacc.cc:474:replace_alu$16178.slice[23].adder to $lut.
Mapping SB_LUT4 cell top_module.$auto$alumacc.cc:474:replace_alu$16178.slice[2].adder to $lut.
Mapping SB_LUT4 cell top_module.$auto$alumacc.cc:474:replace_alu$16178.slice[3].adder to $lut.
Mapping SB_LUT4 cell top_module.$auto$alumacc.cc:474:replace_alu$16178.slice[4].adder to $lut.
Mapping SB_LUT4 cell top_module.$auto$alumacc.cc:474:replace_alu$16178.slice[5].adder to $lut.
Mapping SB_LUT4 cell top_module.$auto$alumacc.cc:474:replace_alu$16178.slice[6].adder to $lut.
Mapping SB_LUT4 cell top_module.$auto$alumacc.cc:474:replace_alu$16178.slice[7].adder to $lut.
Mapping SB_LUT4 cell top_module.$auto$alumacc.cc:474:replace_alu$16178.slice[8].adder to $lut.
Mapping SB_LUT4 cell top_module.$auto$alumacc.cc:474:replace_alu$16178.slice[9].adder to $lut.

2.42.1. Executing OPT_LUT pass (optimize LUTs).
Discovering LUTs.
Number of LUTs:     1478
  1-LUT              169
  2-LUT              320
  3-LUT              404
  4-LUT              585
  with \SB_CARRY     226

Eliminating LUTs.
Number of LUTs:     1474
  1-LUT              165
  2-LUT              320
  3-LUT              404
  4-LUT              585
  with \SB_CARRY     226

Combining LUTs.
Number of LUTs:     1362
  1-LUT              154
  2-LUT              213
  3-LUT              319
  4-LUT              676
  with \SB_CARRY     226

Eliminated 4 LUTs.
Combined 112 LUTs.
<suppressed ~8426 debug messages>

2.42.2. Executing TECHMAP pass (map to technology primitives).

2.42.2.1. Executing Verilog-2005 frontend: /home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v
Parsing Verilog input from `/home/mb/fpga-toolchain/yosys/bin/../share/yosys/ice40/cells_map.v' to AST representation.
Generating RTLIL representation for module `\$_DFF_N_'.
Generating RTLIL representation for module `\$_DFF_P_'.
Generating RTLIL representation for module `\$_DFFE_NN_'.
Generating RTLIL representation for module `\$_DFFE_PN_'.
Generating RTLIL representation for module `\$_DFFE_NP_'.
Generating RTLIL representation for module `\$_DFFE_PP_'.
Generating RTLIL representation for module `\$_DFF_NN0_'.
Generating RTLIL representation for module `\$_DFF_NN1_'.
Generating RTLIL representation for module `\$_DFF_PN0_'.
Generating RTLIL representation for module `\$_DFF_PN1_'.
Generating RTLIL representation for module `\$_DFF_NP0_'.
Generating RTLIL representation for module `\$_DFF_NP1_'.
Generating RTLIL representation for module `\$_DFF_PP0_'.
Generating RTLIL representation for module `\$_DFF_PP1_'.
Generating RTLIL representation for module `\$__DFFE_NN0'.
Generating RTLIL representation for module `\$__DFFE_NN1'.
Generating RTLIL representation for module `\$__DFFE_PN0'.
Generating RTLIL representation for module `\$__DFFE_PN1'.
Generating RTLIL representation for module `\$__DFFE_NP0'.
Generating RTLIL representation for module `\$__DFFE_NP1'.
Generating RTLIL representation for module `\$__DFFE_PP0'.
Generating RTLIL representation for module `\$__DFFE_PP1'.
Generating RTLIL representation for module `\$lut'.
Successfully finished Verilog frontend.

2.42.2.2. Continuing TECHMAP pass.
Using template $paramod\$lut\WIDTH=2\LUT=4'1000 for cells of type $lut.
Using template $paramod\$lut\WIDTH=2\LUT=4'0100 for cells of type $lut.
Using template $paramod\$lut\WIDTH=3\LUT=8'01000000 for cells of type $lut.
Using template $paramod\$lut\WIDTH=3\LUT=8'00011110 for cells of type $lut.
Using template $paramod\$lut\WIDTH=3\LUT=8'01100000 for cells of type $lut.
Using template $paramod\$lut\WIDTH=3\LUT=8'00000001 for cells of type $lut.
Using template $paramod\$lut\WIDTH=3\LUT=8'00010000 for cells of type $lut.
Using template $paramod\$lut\WIDTH=4\LUT=16'1111111111111000 for cells of type $lut.
Using template $paramod\$lut\WIDTH=2\LUT=4'0001 for cells of type $lut.
Using template $paramod\$lut\WIDTH=4\LUT=16'0000000001001111 for cells of type $lut.
Using template $paramod\$lut\WIDTH=4\LUT=16'1111010100110000 for cells of type $lut.
Using template $paramod\$lut\WIDTH=4\LUT=16'0100011101000111 for cells of type $lut.
Using template $paramod\$lut\WIDTH=4\LUT=16'1110101000000001 for cells of type $lut.
Using template $paramod\$lut\WIDTH=4\LUT=16'0000110100000000 for cells of type $lut.
Using template $paramod\$lut\WIDTH=4\LUT=16'0000000011101111 for cells of type $lut.
Using template $paramod\$lut\WIDTH=3\LUT=8'11110001 for cells of type $lut.
Using template $paramod\$lut\WIDTH=4\LUT=16'0110100110010110 for cells of type $lut.
Using template $paramod\$lut\WIDTH=2\LUT=4'1110 for cells of type $lut.
Using template $paramod\$lut\WIDTH=4\LUT=16'1001000000001001 for cells of type $lut.
Using template $paramod\$lut\WIDTH=4\LUT=16'1011000010111011 for cells of type $lut.
Using template $paramod\$lut\WIDTH=4\LUT=16'1011000000001011 for cells of type $lut.
Using template $paramod\$lut\WIDTH=4\LUT=16'1001000000000000 for cells of type $lut.
Using template $paramod\$lut\WIDTH=4\LUT=16'0000101100000000 for cells of type $lut.
Using template $paramod\$lut\WIDTH=4\LUT=16'1000000000000000 for cells of type $lut.
Using template $paramod\$lut\WIDTH=4\LUT=16'1011111101000000 for cells of type $lut.
Using template $paramod\$lut\WIDTH=4\LUT=16'1110101100010100 for cells of type $lut.
Using template $paramod\$lut\WIDTH=2\LUT=4'1001 for cells of type $lut.
Using template $paramod\$lut\WIDTH=3\LUT=8'10010000 for cells of type $lut.
Using template $paramod\$lut\WIDTH=4\LUT=16'1011000000000000 for cells of type $lut.
Using template $paramod\$lut\WIDTH=2\LUT=4'0110 for cells of type $lut.
Using template $paramod\$lut\WIDTH=4\LUT=16'1011111001000001 for cells of type $lut.
Using template $paramod\$lut\WIDTH=4\LUT=16'0100000000000000 for cells of type $lut.
Using template $paramod\$lut\WIDTH=4\LUT=16'0000000001111111 for cells of type $lut.
Using template $paramod\$lut\WIDTH=3\LUT=8'10110000 for cells of type $lut.
Using template $paramod\$lut\WIDTH=4\LUT=16'0100000100000000 for cells of type $lut.
Using template $paramod\$lut\WIDTH=4\LUT=16'0000111011100000 for cells of type $lut.
Using template $paramod\$lut\WIDTH=4\LUT=16'0000000000000001 for cells of type $lut.
Using template $paramod\$lut\WIDTH=3\LUT=8'10000000 for cells of type $lut.
Using template $paramod\$lut\WIDTH=4\LUT=16'1111111000000000 for cells of type $lut.
Using template $paramod\$lut\WIDTH=3\LUT=8'00010100 for cells of type $lut.
Using template $paramod\$lut\WIDTH=4\LUT=16'1101000000000000 for cells of type $lut.
Using template $paramod\$lut\WIDTH=4\LUT=16'0000000011010111 for cells of type $lut.
Using template $paramod\$lut\WIDTH=4\LUT=16'0000000011111110 for cells of type $lut.
Using template $paramod\$lut\WIDTH=4\LUT=16'0000000100000000 for cells of type $lut.
Using template $paramod\$lut\WIDTH=4\LUT=16'0001000000000000 for cells of type $lut.
Using template $paramod\$lut\WIDTH=4\LUT=16'0100111100000000 for cells of type $lut.
Using template $paramod\$lut\WIDTH=3\LUT=8'11100011 for cells of type $lut.
Using template $paramod\$lut\WIDTH=4\LUT=16'0111000001110111 for cells of type $lut.
Using template $paramod\$lut\WIDTH=2\LUT=4'1011 for cells of type $lut.
Using template $paramod\$lut\WIDTH=4\LUT=16'0000000001111101 for cells of type $lut.
Using template $paramod\$lut\WIDTH=3\LUT=8'01001111 for cells of type $lut.
Using template $paramod\$lut\WIDTH=4\LUT=16'1000111110001000 for cells of type $lut.
Using template $paramod\$lut\WIDTH=4\LUT=16'1111010000000000 for cells of type $lut.
Using template $paramod\$lut\WIDTH=4\LUT=16'0000010100001100 for cells of type $lut.
Using template $paramod\$lut\WIDTH=4\LUT=16'0111111100000000 for cells of type $lut.
Using template $paramod\$lut\WIDTH=4\LUT=16'0000000010001111 for cells of type $lut.
Using template $paramod\$lut\WIDTH=4\LUT=16'0010000000001100 for cells of type $lut.
Using template $paramod\$lut\WIDTH=3\LUT=8'00110101 for cells of type $lut.
Using template $paramod\$lut\WIDTH=4\LUT=16'0001000111110000 for cells of type $lut.
Using template $paramod\$lut\WIDTH=4\LUT=16'1111010111000000 for cells of type $lut.
Using template $paramod\$lut\WIDTH=4\LUT=16'1100000000001011 for cells of type $lut.
Using template $paramod\$lut\WIDTH=4\LUT=16'1111110001001111 for cells of type $lut.
Using template $paramod\$lut\WIDTH=4\LUT=16'1111111111110010 for cells of type $lut.
Using template $paramod\$lut\WIDTH=3\LUT=8'11010000 for cells of type $lut.
Using template $paramod\$lut\WIDTH=4\LUT=16'1001011001101001 for cells of type $lut.
Using template $paramod\$lut\WIDTH=4\LUT=16'0000000010111111 for cells of type $lut.
Using template $paramod\$lut\WIDTH=4\LUT=16'0000000011111000 for cells of type $lut.
Using template $paramod\$lut\WIDTH=4\LUT=16'0001111100000000 for cells of type $lut.
Using template $paramod\$lut\WIDTH=4\LUT=16'1000111100000000 for cells of type $lut.
Using template $paramod\$lut\WIDTH=4\LUT=16'0000000000000111 for cells of type $lut.
Using template $paramod\$lut\WIDTH=4\LUT=16'0000111011111111 for cells of type $lut.
Using template $paramod\$lut\WIDTH=3\LUT=8'00000111 for cells of type $lut.
Using template $paramod\$lut\WIDTH=3\LUT=8'11101111 for cells of type $lut.
Using template $paramod\$lut\WIDTH=4\LUT=16'0111110100000000 for cells of type $lut.
Using template $paramod\$lut\WIDTH=3\LUT=8'11100000 for cells of type $lut.
Using template $paramod\$lut\WIDTH=3\LUT=8'01101001 for cells of type $lut.
Using template $paramod\$lut\WIDTH=3\LUT=8'00001110 for cells of type $lut.
Using template $paramod\$lut\WIDTH=3\LUT=8'10000011 for cells of type $lut.
Using template $paramod\$lut\WIDTH=3\LUT=8'11110100 for cells of type $lut.
Using template $paramod\$lut\WIDTH=4\LUT=16'0001010000000000 for cells of type $lut.
Using template $paramod\$lut\WIDTH=4\LUT=16'1100101000000000 for cells of type $lut.
Using template $paramod\$lut\WIDTH=4\LUT=16'1010110000000000 for cells of type $lut.
Using template $paramod\$lut\WIDTH=1\LUT=2'01 for cells of type $lut.
Using template $paramod\$lut\WIDTH=4\LUT=16'0011111101010000 for cells of type $lut.
Using template $paramod\$lut\WIDTH=4\LUT=16'1111001100000101 for cells of type $lut.
Using template $paramod\$lut\WIDTH=4\LUT=16'1100111110100000 for cells of type $lut.
Using template $paramod\$lut\WIDTH=4\LUT=16'0001010000101000 for cells of type $lut.
Using template $paramod\$lut\WIDTH=4\LUT=16'0000011101110111 for cells of type $lut.
Using template $paramod\$lut\WIDTH=4\LUT=16'0110000000000000 for cells of type $lut.
Using template $paramod\$lut\WIDTH=4\LUT=16'0111011101110000 for cells of type $lut.
Using template $paramod\$lut\WIDTH=4\LUT=16'0111111111111111 for cells of type $lut.
Using template $paramod\$lut\WIDTH=3\LUT=8'10010110 for cells of type $lut.
Using template $paramod\$lut\WIDTH=4\LUT=16'0000010111110011 for cells of type $lut.
Using template $paramod\$lut\WIDTH=3\LUT=8'10101100 for cells of type $lut.
Using template $paramod\$lut\WIDTH=4\LUT=16'1111001111110101 for cells of type $lut.
Using template $paramod\$lut\WIDTH=4\LUT=16'0000101111111111 for cells of type $lut.
Using template $paramod\$lut\WIDTH=3\LUT=8'00001011 for cells of type $lut.
Using template $paramod\$lut\WIDTH=4\LUT=16'1111111100010000 for cells of type $lut.
Using template $paramod\$lut\WIDTH=4\LUT=16'0110111111110000 for cells of type $lut.
Using template $paramod\$lut\WIDTH=4\LUT=16'0000011100001000 for cells of type $lut.
Using template $paramod\$lut\WIDTH=4\LUT=16'1100010100001100 for cells of type $lut.
Using template $paramod\$lut\WIDTH=3\LUT=8'00001101 for cells of type $lut.
Using template $paramod\$lut\WIDTH=3\LUT=8'01110000 for cells of type $lut.
Using template $paramod\$lut\WIDTH=4\LUT=16'1100110111111100 for cells of type $lut.
Using template $paramod\$lut\WIDTH=4\LUT=16'0000111110111011 for cells of type $lut.
Using template $paramod\$lut\WIDTH=4\LUT=16'1111111101110000 for cells of type $lut.
Using template $paramod\$lut\WIDTH=4\LUT=16'0100101100000000 for cells of type $lut.
Using template $paramod\$lut\WIDTH=3\LUT=8'01000001 for cells of type $lut.
Using template $paramod\$lut\WIDTH=4\LUT=16'1111111110110000 for cells of type $lut.
Using template $paramod\$lut\WIDTH=2\LUT=4'0010 for cells of type $lut.
Using template $paramod\$lut\WIDTH=4\LUT=16'0000000011110100 for cells of type $lut.
Using template $paramod\$lut\WIDTH=4\LUT=16'0111011100001111 for cells of type $lut.
Using template $paramod\$lut\WIDTH=4\LUT=16'0000000011110001 for cells of type $lut.
Using template $paramod\$lut\WIDTH=3\LUT=8'10001111 for cells of type $lut.
Using template $paramod\$lut\WIDTH=4\LUT=16'0000011100000000 for cells of type $lut.
Using template $paramod\$lut\WIDTH=4\LUT=16'0111000000000000 for cells of type $lut.
Using template $paramod\$lut\WIDTH=4\LUT=16'1011111100000000 for cells of type $lut.
Using template $paramod\$lut\WIDTH=4\LUT=16'0100111101000100 for cells of type $lut.
Using template $paramod\$lut\WIDTH=3\LUT=8'11001010 for cells of type $lut.
Using template $paramod\$lut\WIDTH=4\LUT=16'1011000011111111 for cells of type $lut.
Using template $paramod\$lut\WIDTH=4\LUT=16'1000000011111111 for cells of type $lut.
Using template $paramod\$lut\WIDTH=4\LUT=16'0100001100000000 for cells of type $lut.
Using template $paramod\$lut\WIDTH=4\LUT=16'0001011000000000 for cells of type $lut.
Using template $paramod\$lut\WIDTH=3\LUT=8'10111111 for cells of type $lut.
Using template $paramod\$lut\WIDTH=4\LUT=16'0000111000000000 for cells of type $lut.
Using template $paramod\$lut\WIDTH=4\LUT=16'0011101011111111 for cells of type $lut.
Using template $paramod\$lut\WIDTH=4\LUT=16'0000000000011111 for cells of type $lut.
Using template $paramod\$lut\WIDTH=4\LUT=16'1110111100000000 for cells of type $lut.
Using template $paramod\$lut\WIDTH=4\LUT=16'0000000000001101 for cells of type $lut.
Using template $paramod\$lut\WIDTH=4\LUT=16'1111101011000000 for cells of type $lut.
Using template $paramod\$lut\WIDTH=4\LUT=16'0000111101010101 for cells of type $lut.
Using template $paramod\$lut\WIDTH=4\LUT=16'0000001100001010 for cells of type $lut.
Using template $paramod\$lut\WIDTH=4\LUT=16'1111111111100000 for cells of type $lut.
Using template $paramod\$lut\WIDTH=4\LUT=16'0010100011010111 for cells of type $lut.
Using template $paramod\$lut\WIDTH=4\LUT=16'0011101100110000 for cells of type $lut.
Using template $paramod\$lut\WIDTH=4\LUT=16'1001011000000000 for cells of type $lut.
Using template $paramod\$lut\WIDTH=4\LUT=16'0110100100000000 for cells of type $lut.
Using template $paramod\$lut\WIDTH=4\LUT=16'1110111111111111 for cells of type $lut.
Using template $paramod\$lut\WIDTH=4\LUT=16'0000000000001011 for cells of type $lut.
Using template $paramod\$lut\WIDTH=4\LUT=16'1000111111111111 for cells of type $lut.
Using template $paramod\$lut\WIDTH=2\LUT=4'0111 for cells of type $lut.
Using template $paramod\$lut\WIDTH=4\LUT=16'1111111100001011 for cells of type $lut.
Using template $paramod\$lut\WIDTH=4\LUT=16'1111010011111111 for cells of type $lut.
Using template $paramod\$lut\WIDTH=4\LUT=16'1111111111110100 for cells of type $lut.
Using template $paramod\$lut\WIDTH=3\LUT=8'01111111 for cells of type $lut.
Using template $paramod\$lut\WIDTH=4\LUT=16'0100000011111111 for cells of type $lut.
Using template $paramod\$lut\WIDTH=3\LUT=8'00011111 for cells of type $lut.
Using template $paramod\$lut\WIDTH=4\LUT=16'0110011000000000 for cells of type $lut.
Using template $paramod\$lut\WIDTH=4\LUT=16'1111111100000110 for cells of type $lut.
Using template $paramod\$lut\WIDTH=4\LUT=16'1001011011111111 for cells of type $lut.
Using template $paramod\$lut\WIDTH=4\LUT=16'0100100010000100 for cells of type $lut.
Using template $paramod\$lut\WIDTH=4\LUT=16'0000011011001110 for cells of type $lut.
Using template $paramod\$lut\WIDTH=4\LUT=16'1111111110010110 for cells of type $lut.
Using template $paramod\$lut\WIDTH=4\LUT=16'0000000010010110 for cells of type $lut.
Using template $paramod\$lut\WIDTH=4\LUT=16'0000000001100110 for cells of type $lut.
Using template $paramod\$lut\WIDTH=4\LUT=16'0000011000000110 for cells of type $lut.
Using template $paramod\$lut\WIDTH=4\LUT=16'0110000001100000 for cells of type $lut.
Using template $paramod\$lut\WIDTH=4\LUT=16'0001001000100001 for cells of type $lut.
Using template $paramod\$lut\WIDTH=4\LUT=16'1111111111111110 for cells of type $lut.
Using template $paramod\$lut\WIDTH=4\LUT=16'0000110001101110 for cells of type $lut.
No more expansions possible.
<suppressed ~3122 debug messages>
Removed 0 unused cells and 2839 unused wires.

2.42.3. Executing HIERARCHY pass (managing design hierarchy).

2.42.3.1. Analyzing design hierarchy..
Top module:  \top_module

2.42.3.2. Analyzing design hierarchy..
Top module:  \top_module
Removed 0 unused modules.

2.42.4. Printing statistics.

=== top_module ===

   Number of wires:               1625
   Number of wire bits:           3074
   Number of public wires:         283
   Number of public wire bits:    1142
   Number of memories:               0
   Number of memory bits:            0
   Number of processes:              0
   Number of cells:               2341
     $_TBUF_                         1
     SB_CARRY                      430
     SB_DFF                         10
     SB_DFFE                       203
     SB_DFFESR                     201
     SB_DFFESS                       1
     SB_DFFSR                      130
     SB_LUT4                      1362
     SB_PLL40_CORE                   1
     SB_RAM40_4K                     2

2.42.5. Executing CHECK pass (checking for obvious problems).
checking module top_module..
found and reported 0 problems.

2.42.6. Executing BLIF backend.

2.42.7. Executing JSON backend.

End of script. Logfile hash: 05f3a6cac6
CPU: user 16.70s system 0.06s, MEM: 80.22 MB total, 71.15 MB resident
Yosys 0.8+615 (git sha1 6538671c, clang 7.0.1-8 -march=native -mtune=native -O2 -fpermissive -fPIC -Os)
Time spent: 20% 26x opt_expr (3 sec), 19% 26x opt_clean (3 sec), ...
